"NU180" - A U180 drop-in replacement for the 3458A.

[wanghar]

Zonda, all the resistors I used were bought from LCSC. These 10ppm resistors are nothing special—the manufacturer, RESI, is a local Chinese components supplier. The datasheet is over 12MB. I tried to attach but the system won't allow that large file. Please refer to this link ： https://www.lcsc.com/datasheet/C351577.pdf

[wanghar]

I ran the 30 PLC test first is to get a better look at the INL performance, since that's probably one of the more critical parameters. I wanted to evaluate this while I still had access to the other 3458A. As for how to measure DNL – I don't have a concrete idea yet.

[Zondar]

Wanghar, I just meant I'd like a list to confirm what values you used and what tolerance and ppm's for each resistor, e.g., "37.5k, 0.1%, 10 ppm" for each value. If they are all the same, then just confirm what R values you are using. That's all. Thanks.

I have one board on hand that's been used already, but I can probably clean it up enough to build a third board (nope, it's too far gone). I have three new boards coming, but sooo frustratingly slowly! The outfit changed the board's status to "panelized" and then sat on it for almost a week before finally putting it in production, which takes another ~9 days, then ~5 days to arrive. I must find a faster way for future spins.

[wanghar]

The res used were list as such. Only change is that using additional 200ohm to combine with 2pcs of 33k to form a 16.7K.
https://www.eevblog.com/forum/metrology/nu180-a-u180-drop-in-project-for-the-3468a-dvm/msg6074027/#msg6074027

[Zondar]

OK, thank you.

I will have to be patient and wait for the pending boards to arrive before I can do too much more. Meanwhile, I have to get another board iteration out the door that will accept 2512 resistors, etc. Unless people have suggestions, I haven't seen any reason to change anything else.

Anyway, wanghar seems to be demonstrating that the design has real potential as a replacement. That's super encouraging!

[MiDi]

Whilst replacing the LT1001 in the ref buffers with ADA4522 one at a time to see improvement on noise, ±12ref were fine, but +5Vref amp replacement resulted in a significantly higher noise level of measurements.
The fix was to add a capacitor between +5ref (TP151) and neg. input of ADA4522 (+5_sum / C151 & C152).
The original LT1001 is a much slower part and stability should not be a problem, but an additional cap e.g. 10-100nF parallel to the 10k of the +5ref R-divider should not do any harm either.

Does it make any difference on the occurence of the rundown convergence error between AZ and AZ off?
Any difference between NPLC >=1 and NPLC <=0.005 (slow vs. fast runup)?

As Kleinstein already suggested, a scope measurement of the rundown on the integrator (TP112) and slope amp (TP140) with trigger e.g. on rising edge of RUS should give a clue what is going on.
A comparison between a successful acquisition and a failed one with convergence error would be good.
Use x10 probes and BW limit for noise reduction.
Example of rundown measurement from https://www.eevblog.com/forum/metrology/so-i-have-a-mint-condition-agilent-3458a/msg6046739/#msg6046739

[Kleinstein]

Replacing U160/U165 with AZ amplifiers can backfire. There is a chance to get interference with the ADC modulation (some 330 kHz). The more straight forward choice would be more OPA205 as sluightly lower noise BJT based OP-amps. The 5 V ref. level is anyway less cricital. If one needs to replace, maybe an OPA202, that is good in driving a capacitive load.
For lower noise my choice would be more a little filtering (could be as little as 2 K and 100 nF) for the reference.
With a U180 replacement, if lowest noise is the target, it would be more the change of the ref. voltages and resistors to +-15 V and 100 K instead of +-12 and 80 K. This would also allow using 100 K resistor arrays instead of separate resistors.

Looking at the failed conversion would really make sense. It would be however likely be TP112 or TP140 and not both at the same time. Due to noise it would be looking at single captures. The scope trace from Midi shows quite some interference from the digital signals (likely via probe ground).

[wanghar]

Yes MiDi, BW limit helps alot. Now we can capture the waveform during normal run, but we still need the right moment to get the waveform for the 114 error.

[Kleinstein]

From the scope trace it looks like the -S1 slope is rather close to zero and is reaching the end more from a noise spike than actual integration.
There is quite some overshoot in the reaction (more by design, not a fault of NU180) and it makes also sense as there also seem to be wiggles at the start of the slopes. So I would not expect an issue with to short a phase, but more with too long needed for the last step. Or maybe triggering the comparator already from the wigglel when switching from S4 to -S1.  A possible issue might be capacitive pickup from A3 (U150 area) to the NU180 board.

It might by worth testing some shield between U150 and the NU180.

My guess is that the wiggle seen at the finish mark is the engaging of the reset part and removal of the ladder part and thus from the charge injection from the switches. The ringing at the integrator looks OK, but the slope amplifier seems to be ringing quite a bit. This may be via ground bounce, not just the integrator.

[Zondar]

I keep looking at my board for areas of improvement, and one thing that has bothered me was the treatment of the various grounds.

I had kept GND, AGND1, AGND2 and AGND3 separate out of paranoia, even though they were shown as all connected together in the available A3 schematic.

If those 4 were connected together, the board design would be simplified by unifying the four to a single ground plane, and there would be 4 pins connecting from A3 to that plane instead of a meager single pin.

What do people think? What other board-related changes might be considered?

[Kleinstein]

It would make sense to still have the power ground for the CPLD and switches separate from the analog ground.

I would still habe at least a dummy resistor for the supply modulation.
If possible (may well work with 4 layers) have be bottum part that goes over U150 shielded with ground or similar.
If there is space maybe consider space for another resistor (or up to 3 in series to get to the 30 M range) from pin 23 or 24 for possible "offset trim" to either +12 V or -12 V.

[wanghar]

Tried making some adjustments to make the waveforms easier to read. First, I recorded rundown waveforms from 0.002 PLC to 10 PLC. For a specific board, the waveform consistency is very high, with no significant differences visible. Then  a basic comparison between Board #1 and Board #2 is conducted at 0.01PLC.

The main difference lies in the -S1 stage. From the slope_Amp waveform, it can be seen that Board #2 is relatively flat, while Board #1 has a slight rising slope, though not very steep. Then, I removed the 1M resistor connected in parallel with the 24K on Board #1. Under this condition, Error 114 is reported 20-30 seconds after startup. At this point, the waveform of Board #1 shows a steeper slope in the -S1 stage (still need to look at slope_Amp).

Here's the counterintuitive part: Board #2's relatively flat -S1 stage seems somewhat unreasonable, yet it can run continuously for over ten hours without any Error 114. On the other hand, Board #1 (after removing the 1M resistor) has a rising slope in -S1 that looks more reasonable, but it can't last 30 seconds before throwing Error 114.

Can we find something else important from these charts?

[Kleinstein]

With the missing or even wrong slope for #2 board the question is, why the final -s1 part actually terminates. From the curves the comparator should not trigger and thus a termination more from reaching the time limit. This would be the point where I would expect getting the error from.
The times for the -S1 phase look all rather similar.

One possibility could be that a timeout at -S1 may not be so rare (could happen from noise) and the error would be triggered from a time out with the S4 phase. The slightly larger slope for S4 that comes with the smaller -S1 slope could be what makes the difference.
One could do a test with even stronger trim to see at what point an error comes up.

If possible, maybe do another measurement, with the slope amplifier and the comparator output (could be tricky with interference).
Another point could be having a tiny voltage (like a few mV with 0.01 PLC, 10 V range) at the input, to see in which range the timing does change.

[MiDi]

For comparison freshly captured rundown from A3 with 0V input with original U180 (triggered on +S64 slope on driver input).
The end of rundown looks like it is a fixed time from start of rundown.
As there is no error if the -S1 slope does not finish in time or even has wrong direction (no zero crossing), is it used for the result at all?

[wanghar]

Looks like the total rundown time is fixed. After adding the comparator signal, it's a bit odd that #2 board can reliably trigger the comparator to flip in the final stage.
 Or, could it possibly be triggered by RUS instead?

Referring to the schematic, if RUS is connected to -in through R144, a signal going down to GND will lower the comparator's threshold.

[Kleinstein]

As there is no error if the -S1 slope does not finish in time or even has wrong direction (no zero crossing), is it used for the result at all?

For the longer integration, like 1 PLC and more the result from the -S1 part is not really needed and usually burried in noise.
However for the really fast conversion the last part and quantization noise could still matter.
Even if it sometimes fails the -S1 part could still be included in the result. It would need some extra care to not add extra noise.

One should be able to see the influence of the fine slopes at the highest speeds. AFAIR here the quantization steps are limiting. A failing -S1 step should produce more noise and visible DNL error, that should be visible in a histogram test (high speed, 10 V range non AZ with a ~ 100 mV triangle wave).

Looks like the total rundown time is fixed. After adding the comparator signal, it's a bit odd that #2 board can reliably trigger the comparator to flip in the final stage.

The comparator seems to trigger just before the wiggle at the slope amplifier. This is a bit too short for a reaction to the comparator and than start the reset.

[wanghar]

Added the RUS signal into the waveforms. I'm leaning towards the idea that the RUS signal changes the comparator's threshold at the last moment, triggering the flip. This happens not only on board #2 but also on board #1. Resistors R142, R143, and R144 do indeed exist on the A3 board (they were not shown in the schematic of HP CLIP). The RUS signal acts as a role of timekeeper throughout the rundown stage, and this fixed duration is approximately 5uS.

[Kleinstein]

The rundown time of 5 µs may not be sufficient in all cases. Depending on the input voltage and resulting voltage in the integrator at the end of run_up the fast initial rundown part alone may need up to 5 µs. AFAIK it can be close to 2 run-up steps.

It really looks like the RUS signal is finally triggering the comparator. It nearly looks like a hack to make sure that the -S1 finally reaches the end and not cause an error.

[MiDi]

Looks like the total rundown time is fixed. After adding the comparator signal, it's a bit odd that #2 board can reliably trigger the comparator to flip in the final stage.
 Or, could it possibly be triggered by RUS instead?

Referring to the schematic, if RUS is connected to -in through R144, a signal going down to GND will lower the comparator's threshold.

The arrangement and values of R142, R143 & R144 changed with 66503 REV D (~1995), see attached schematic.
In the analyzed rundown switching -1S off causes the comparator to trigger.
After the comparator zero crossing RUR and RUS switch off.
In your screen captures it looks different as you described.

I had kept GND, AGND1, AGND2 and AGND3 separate out of paranoia, even though they were shown as all connected together in the available A3 schematic.

If those 4 were connected together, the board design would be simplified by unifying the four to a single ground plane, and there would be 4 pins connecting from A3 to that plane instead of a meager single pin.

What do people think? What other board-related changes might be considered?

All grounds are connected on A3 PCB, but AGND2 & AGND3 go through L124 to GND - see attachment.
In my U180 replacement REV B (see 2nd attachment - released soon on GH) they are all connected via GND plane already on U180 PCB incl. all unused pins that are connected to GND on A3.

Tried making some adjustments to make the waveforms easier to read. First, I recorded rundown waveforms from 0.002 PLC to 10 PLC. For a specific board, the waveform consistency is very high, with no significant differences visible. Then  a basic comparison between Board #1 and Board #2 is conducted at 0.01PLC.

The main difference lies in the -S1 stage. From the slope_Amp waveform, it can be seen that Board #2 is relatively flat, while Board #1 has a slight rising slope, though not very steep. Then, I removed the 1M resistor connected in parallel with the 24K on Board #1. Under this condition, Error 114 is reported 20-30 seconds after startup. At this point, the waveform of Board #1 shows a steeper slope in the -S1 stage (still need to look at slope_Amp).

Here's the counterintuitive part: Board #2's relatively flat -S1 stage seems somewhat unreasonable, yet it can run continuously for over ten hours without any Error 114. On the other hand, Board #1 (after removing the 1M resistor) has a rising slope in -S1 that looks more reasonable, but it can't last 30 seconds before throwing Error 114.

Can we find something else important from these charts?

The main difference that I can spot are the glitches when the switches change at the beginning of rundown (-S256) and when -S256 disconnects (S64 engages) - looks to me as charge injection.
Do the original switches have so much lower charge injection in comparison?

[Kleinstein]

Turning on and off the S256 slope is via the HC14 chip at the 5 V. So classic charge injection of the switches would not be an issue. It would be more capacitive coupling inside the NU180 or from the HC14 chip to the board. The switches are the same as with the original.

[MiDi]

Hold before rundown start is done via -12ref1 & +12ref2 80k paths.
At rundown start -S256 is -12ref1 & -12ref2 80k path (switching from +12ref2 to -12ref2 80k: glitch/spike).
Hold before +S64 engages is +12ref1 & -12ref2 80k path (switching from -12ref1 to +12ref1 80k: glitch/spike, but looks similar to original).
Then +S64 engages and -S256 disengages (+12ref1 & -12ref2 80k path off: glitch/spike).
Only +S64, -S16, +S4, -S1 are from 37k5/16k7 ladder with external switches HC14.

[Kleinstein]

You are correct the S256 is via the main ref. switches. The disturbance from switching looks comparable to the one at the end of rundown / start of reset.
In the curves with the original U180 there is also quite some spike for the start of the reset, but the S256 switching looks a bit cleaner.

So the charge injection from the switches is a little different, but not much larger than with the original U180.

[wanghar]

Tested the waveform of the original U180, and it's indeed triggered by -S1 to toggle comparator. This suggests something interesting—the 114 error doesn't seem to be directly related to -S1, or at least not in a significant way.

Paralleling a trimmer on the 24K resistor to increase the +5ref voltage does effectively clear the 114 error. However, raising the +5ref voltage might actually prevent -S1 from triggering the comparator. This whole situation is just full of contradictions.

[iMo]

..This whole situation is just full of contradictions.

Due to those contradictions Keysight has not been able to develop a replacement to this day.. 

[Kleinstein]

Not having all the details on the FPGA logic makes the design not easier and requires some guesswork. To some surprise error 114 seems to be not from a timeout for the S1 step, but likely more with an issue (e.g. time out) aready with the S4 step.  It is still a bit disapointing that the self test seems to not detect if the S1 slope is so far off that it essentially never finishes with the S1 step.
It makes some sense to not directly give an error for every time out, as noise or EMI may be enough to cause an occasional timeout with S1. The self test should however ideally detect an issue with S1.
Even if the S1 step does no work the extra quatization noise would mainly be an issue with short integration (< 1 PLC). At 1 PLC the extra quantization noise would only be some 170 nV RMS with an observe total noise in the 500-700 nV range.