Great initiative!
Regarding stack up, first viable stack-up is 6 layers, you need your gnd planes intact, no split planes so you have S G P/S P/S G S, there is no point in attempting this on 2 layer and there is zero benefit of alu pcb.
When it comes to outline, I agree with Kleinstein, it will be impossible, but it does not matter, there is quite a bit of space so I would not worry about this.
When it comes to the resistors it is very important to remember it is the ratio stability that matters, this will be hard if not impossible to do with single resistors unless you have very deep pockets, but even simple TDP/NOMCA will most likely function well as they are on the same die, and they are cheap!
For FPGA, don’t limit the choices to extern output, level shifters are for that job. So 3.3v logic FPGA is fine, personally I would look at one of the tiny MAX10, but that is just because I am biased and use them myself.
But as I wrote in the 3458a thread, I think we should break it down, first try to make a 8.5 digit ADC with necessary speed for DC(10 nplc should be a goal at least), then translate to U180.
Resolution, INL and noise is the real challenge here, and if one can’t reach that at 10 nplc, I consider it waste of time and better to sell meter and get a nice 7.5 digit meter.
But flip the negativity, if we do succeed, the platform for a new meter is very much in place and rest is “easy” in comparison so it would really be a great milestone for DIY 8.5 digit. There are ways to do that now as well, with off the self ADCs and oversampling, but it is not easy and requires great care/temp control. But there has already been a lot of work done on DIY MS ADC(Look at kleinstein), if we move this over, improve ratio stability and switch driving(moving from jitter prone MCU to FPGA), we can get quite good results on off the shelf parts. If it can exceed the U180? Probably not, it has the benefit of resistor network and switches in same packages, but if we trade speed to resolution, I think we can.