Flags in verilog/cross talk between modules

[gauravmp]

Hi,

I have multiple modules and a top level module in verilog and I plan on used these subsidiary modules like functions in c when you program a microcontroller. Could someone tell me an easy way to have a state machine run within a subsidiary module an 'x' number of times with a command from the top level module?

I've thought about it and I wanted to implement something like a flag that would go off in the top level module with the flag port being accessed by the subsidiary module thus reacting to it. However, I've reached a roadblock and i have not figured out how to give that flag.

Any help would be appreciated.

Thanks,

Gaurav

[rstofer]

Load a counter?  The sub module looks at the counter and makes one pass per count?

[Sal Ammoniac]

Post your code. That'll help us help you.

[gauravmp]

Thanks for your replies. Here's my code for UART:

module uart(
    clk,
    tx,
    data,
    send_req,               //this would be high for one clock period
    sent,
    tx_busy,
    //debugging purposes
    transmit_flag,
    state,
    tick,
    count
    );
   
input clk;
input data;
input send_req;

output count;
output tick;
output state;
output transmit_flag;
output tx;
output sent;
output tx_busy;

reg[14:0] count;
reg[3:0] state;
reg muxbit;
reg[7:0] tx_data;
reg start;
reg transmit_flag;
reg tx_busy;
reg sent;

wire[7:0] data;
wire tick;

initial
begin
    /*sent <= 0;*/
    transmit_flag <= 0; 
    tx_busy <= 0;
    count <= 0;
end

//baud rate generator:
always @(posedge clk)
begin
    count<=count+1;
    if(count == 5208)
        count <= 0;           
end
assign tick = (count==5208);

//manager
//always @(posedge clk)
//begin
//    if((send_req)&(~tx_busy))
//        begin
//        tx_data <= data;
//        transmit_flag <= transmit_flag + 1;
//        end
//    if(done)
   
//end


//transmission
always @(posedge tick)
begin
    if((send_req)&(~tx_busy))
        begin
        tx_data <= data;
        transmit_flag <= transmit_flag + 1;
        end
    case(state)
    4'b0000: begin
                sent <= 0;
                if(transmit_flag)                   
                    begin
                    tx_busy <= 1;
                    transmit_flag <= transmit_flag - 1;
                    state <= 4'b0100;
                    end
             end
    4'b0100: begin state <= 4'b1000; end // start
    4'b1000: state <= 4'b1001; // bit 0
    4'b1001: state <= 4'b1010; // bit 1
    4'b1010: state <= 4'b1011; // bit 2
    4'b1011: state <= 4'b1100; // bit 3
    4'b1100: state <= 4'b1101; // bit 4
    4'b1101: state <= 4'b1110; // bit 5
    4'b1110: state <= 4'b1111; // bit 6
    4'b1111: state <= 4'b0001; // bit 7
    4'b0001: begin state <= 4'b0000; tx_busy <= 0; sent <= 1; end// stop1
    default: state <= 4'b0000;
endcase
end

always @(state[2:0])
case(state[2:0])
  0: muxbit <= tx_data[0];
  1: muxbit <= tx_data[1];
  2: muxbit <= tx_data[2];
  3: muxbit <= tx_data[3];
  4: muxbit <= tx_data[4];
  5: muxbit <= tx_data[5];
  6: muxbit <= tx_data[6];
  7: muxbit <= tx_data[7];
endcase

// combine start, data, and stop bits together
assign tx = (state<4) | (state[3] & muxbit);

endmodule



A signal send_req from the top level module will activate it. Sure, but I want to change it so I could control this module to be executed just once or an x number of times.
Any help would be appreciated.

[antti]

RULE #1 FPGAs do not EXECUTE the code you write
RULE #2 FPGAs do not EXECUTE the code you write
RULE #3 FPGAs do not EXECUTE the code you write

FGPAs implement the HARDWARE you  DESCRIBE

and this hardware you have DESCRIBED does exactly what you described what it should do.

you should understand this first, then you can ask questions properly

FPGAs are like magic, they become whatever you want them to be, you just have to know how to describe your wish.

verilog is one of the languges you can use to describe your wishes.