Couple of notes on this:
Supermicro is said to still be doing free (customer ships to Supermicro at customer's expense) RMAs even out of warranty. Worth a shot for anyone with affected Supermicro motherboards:
https://www.truenas.com/community/threads/fyi-intel-c2000-family-of-processors-system-fault-may-lead-to-dead-system.50314/post-707843The workaround that was/in applied by some vendors (those that don't replace the SoC wholesale) involves pulling up not just the LPC clock, but also the LPC data lines. I believe that this is because the degradation is not limited to the Clock pins - there have been cases of people with boards that still boot, but where the host cannot communicate with the BMC over LPC (Note 1), and also cases (me included) where a dead board is brought back to life with the external pull up, but the BMC is unreachable over LPC.
I'm still trying to wrap my head around why exactly systems fail to boot (see also link above). It turns out you can't boot from LPC, only from SPI - but this behavior is configurable by setting a pin of the SoC (FLEX_CLK_SE0 / AH59). At boot, the SoC pulls it up with 20k and reads the pin - high is SPI boot, low is LPC boot.
I've come to suspect that this clock, and not the LPC clock proper, is being used by most/all vendors to run the LPC bus, and thus being run out to the TPM header. This would probably be needed to enable a 33 MHz LPC bus, because the LPC clock pins are fixed at 25 MHz.
Note 1: The BMC has a bunch of tentacles into the host system. PCIe is used for graphics and USB is used to provide remote I/O devices. LPC is used to provide SuperIO functionality and in-band management of the BMC.