WCH $0.10 USD RISC-V MCU

[mon2]

Hi. Perhaps old news elsewhere but new here ?

WCH has some more devices of interest in the pipeline...

$0.10 USD RISC-V MCU

English manual:

https://github.com/openwch/ch32v003/blob/main/CH32V003RM-EN.pdf

https://www.cnx-software.com/2022/10/22/10-cents-ch32v003-risc-v-mcu-offers-2kb-sram-16kb-flash-in-sop8-to-qfn20-packages/

https://www.reddit.com/r/RISCV/comments/y2nw0f/ch32v003_price_is_less_than_010/

https://www.hackster.io/Makergo/ch32v003-development-board-the-chips-are-just-10-cents-7712c9

Kit is out of stock except on Tindie at this time of writing.

https://www.tindie.com/search/?q=CH32V003+

Update (11-03-2022):

1) LCSC has the device and kit now marked as EOL. We pinged WCH for advice and they suggested for us to purchase from their Aliexpress webstore.

2) WCH has recently posted the MCU & kit on their Aliexpress portal at even a lower resale (for the kit & debugger):

https://www.aliexpress.com/item/1005004895791296.html?spm=a2g0o.store_pc_newArrival.8148356.7.356e5c5bzrwqwv&pdp_npi=2%40dis%21USD%21US%20%245.80%21US%20%245.51%21%21%21%21%21%402100bddb16674753165278582e62a5%2112000030932586121%21sh

[DavidAlfa]

1.1 cent, 20KB / 496 bytes MB95F354EPF-G-SNE2

1.3 cent, 36KB / 1KB MB95F656EPFT-G-SNE2

There're plenty of such deals. But they're rarely stable, once the 1 cent starts selling well, it either goes $0.90 (Or more), or goes out of stock forever.

[wraper]

For 1 cent, 20KB flash (Not OTP), 496 bytes RAM

https://lcsc.com/mobile/product-detail/Microcontroller-Units-MCUs-MPUs-SOCs_Cypress-Semicon-MB95F354EPF-G-SNE2_C2944972.html

It's not a real price and zero in stock. Here is realistic price https://eu.mouser.com/ProductDetail/Infineon-Technologies/MB95F354EPF-G-SNE2?qs=%2FPVulymFwT2EPYkJ23r4XA%3D%3D

[SiliconWizard]

For 1 cent, 20KB flash (Not OTP), 496 bytes RAM

https://lcsc.com/mobile/product-detail/Microcontroller-Units-MCUs-MPUs-SOCs_Cypress-Semicon-MB95F354EPF-G-SNE2_C2944972.html

It's not a real price and zero in stock. Here is realistic price https://eu.mouser.com/ProductDetail/Infineon-Technologies/MB95F354EPF-G-SNE2?qs=%2FPVulymFwT2EPYkJ23r4XA%3D%3D

Yes. It's also EOL.

[DavidAlfa]

Yeah, but if you buy 20.000 and does the job, what's the problem? It all depends on the project.
Lots of non-EOL products have flown away for months, you're never safe.

Edit:
Ooops, I forgot to click "Apply" after checking "In stock".

[ataradov]

I have a plan to play with WCH RISC-V devices. I really like what they do with SWD and interrupt controller on their devices. They skipped standard RISC-V nonsense and use ARM approach instead. Not sure how well it all works in practice.

If this seems to be usable, and the price and availability remain reasonable, it might be a good generic MCU.

Although this specific device seems to have some one wire programming interface. So, this is something to investigate too.

Too bad ICs are not readily available from reasonable sources yet. Would be an interesting project for the new year break.

[HwAoRrDk]

I really like the look of these.

WCH are obviously gunning for the market served by the STM8S003 - hence the naming convention, the fact the pinout is virtually identical (basically drop-in for TSSOP20 package, all major peripherals on the same pins), and the price.

One thing I don't like, though, is that if the description of being a "RISC-V2A core" is any indication of CPU capabilities, while it has the 'A' atomic extensions, it doesn't appear to have the 'M' integer multiplication/division extensions. Or is that a given for most RISC-V cores, so they don't feel it worth a mention?

What is the space efficiency like of the RISC-V instruction set? That is, is 16KB of flash considered large or small for a RISC-V chip?

[ataradov]

"QingKe V2A" is just a random core name. Architecture is RV32EC, so basic instruction set with 16 registers with compression supported. In my tests RV use of compressed instruction set makes the code on par or 10-20 % bigger than comparable Thumb-2 code. It depends on the code specifics.

There is no hardware multiplier/divider in this device.

[ali_asadzadeh]

They look very interesting indeed.

[brucehoult]

Hi. Perhaps old news elsewhere but new here ?

Yup

https://www.reddit.com/r/RISCV/comments/y2nw0f/ch32v003_price_is_less_than_010/

My post, 19 days ago :-)

Kit is out of stock except on Tindie at this time of writing.

And the chips there are the 20 pin version for $5 for 5.

I assume it's the 8 pin ones are supposed to be under $0.10. I don't know how much for the bigger packages.

That $0.10 price is from the company CEO. As his tweet said, they should be on LCSC, but so far only the dev board has appeared there.

[brucehoult]

"QingKe V2A" is just a random core name. Architecture is RV32EC, so basic instruction set with 16 registers with compression supported.

Oooh .. I hadn't seen the manual or information that they are RV32E not RV32I.

In my tests RV use of compressed instruction set makes the code on par or 10-20 % bigger than comparable Thumb-2 code. It depends on the code specifics.

From what I can see the difference is usually from single-bit instructions, where bit-banding is used on ARM. Assuming the RISC-V is compiled with -msave-restore to get function prolog/epilog out of line at the cost of 3 jumps (which is usually negligible). Sometimes array addressing can have an impact, but it's unusual to be significant in optimized code.

The B extension makes a big difference with both, but that hasn't made its way into cheap hardware yet.

There is no hardware multiplier/divider in this device.

Interesting, but not surprising. The 8 bit CPUs this is aimed at tend not to also.

I wonder what the performance of the shift instructions is. All the other RISC-V microcontrollers I know of have RV32IMAC, often with slow multipliers but 1-cycle arbitrary shifts. But maybe they have cheaped out on the shifter too.

[brucehoult]

What is the space efficiency like of the RISC-V instruction set? That is, is 16KB of flash considered large or small for a RISC-V chip?

It's great compared to PIC, AVR, 8051, 6502, z80 ... especially if dealing with data bigger than 8 bits.

Not quite as good as Thumb2 with the base ISA (which was optimised for workstation benchmarks such as SPEC including SPECfp), but recent ISA extensions (not present in this chip) have brought it closer and the upcoming Zc* extension makes it better according to people in companies such as Huawei who have been instrumental in the design and have been deploying an early version in production devices for a year or two already.

https://www.reddit.com/r/RISCV/comments/y3p7wi/public_review_for_standard_extensions_zc/

[HwAoRrDk]

There is no hardware multiplier/divider in this device.

Interesting, but not surprising. The 8 bit CPUs this is aimed at tend not to also.

Disappointing. I guess they didn't include it because they want to cut the die size down as small as possible to make it cheaper.

The silly thing is that the STM8S003 - the chip they're targeting the market for - does have hardware multiply and divide.

[mac.6]

Is RV32E well supported by toolchains? it as not the case a few years away...

I remember having compaired BLE linklayer code between cortex M0 and early pulpV toolchain, code size was horrible on pulpV (over 50% increase), this may comes from absence of option like --save-restore.
Clearly code size is the n°1 grip people have on risc-v, as most design are more constrained by flash/sram sizing than core gate count, that's where you clearly see the education origin from risc-v.

[brucehoult]

It's not education origin, it's workstation origin. RISC-V has by far the most compact code of any 64 bit ISA. The 16 bit "C" extension opcodes were allocated with the assumption that you are doing lots of floating point. 

Microcontrollers and even 32 bit in general were very much an afterthought. That it comes so close to ARMv7 is quite remarkable. It should beat Cortex M0 with its much weaker than ARMv7 ISA.

In every case I've seen where someone complained that "RISC-V code is much bigger than ARM code" it was actually that the C library they were using was an inappropriate one designed for another purpose and that's where all the space went. Not any difference in the ISAs.

[ataradov]

Yes, MCU stuff based on RISC-V is below average. Not only in code size, but also in general architecture. This is why I appreciate WCH effort to keep as much of ARM-like stuff as possible while replacing the core. I have not tried how well this works in practice, but it can't be worse than "native" RISC-V MCUs.

[SiliconWizard]

Regarding price/performance, Nuvoton has pretty cool ARM-based stuff and at this point, for very low-cost MCUs, I would favor that.

Now it's great to see all those RISC-V MCUs flourishing - great to have more choice and break the ARM "monopoly". But yes, most of them are not quite on par with the ARM-based offering yet.

[mac.6]

In every case I've seen where someone complained that "RISC-V code is much bigger than ARM code" it was actually that the C library they were using was an inappropriate one designed for another purpose and that's where all the space went. Not any difference in the ISAs.

I am in a different mindset than general MCU user, I use risc-v for dedicated controller in a MPU, and it's a tough sell than you need to increase code size by 15 to 20% just because you went from a M0 to a risc-v unless you really need risc-v for dedicated extension.

[brucehoult]

In every case I've seen where someone complained that "RISC-V code is much bigger than ARM code" it was actually that the C library they were using was an inappropriate one designed for another purpose and that's where all the space went. Not any difference in the ISAs.

I am in a different mindset than general MCU user, I use risc-v for dedicated controller in a MPU, and it's a tough sell than you need to increase code size by 15 to 20% just because you went from a M0 to a risc-v unless you really need risc-v for dedicated extension.

Show me the code with this alleged 15 to 20% size difference between Cortex M0+ and RISC-V. I simply do not believe it, and I've seen a lot of RISC-V code.

I mean on something that threatens to fill the 16 KB flash on a chip like this, not some cherry-picked single function. And not ARM using a hyper-optimised shortcut-taking embedded C library and the RISC-V using Newlib.

[ataradov]

For a practical test of the application that may be suitable for an MCU like this (minus lack of USB here), I build this firmware https://github.com/ataradov/free-dap/tree/master/platform/samd11 with "rv32imc" target. Everything else remained the same, so that target RV MCU would have the same memory map and layout as the SAM D11 (Cortex-M0+). I had to nop out a couple instructions in the assembly sections, but that would not change the code size a lot.

The code size for Cortex-M0+ is 9184 bytes. The code size for RV is 10228 bytes. This is about 11% more. For comparison, rv32im code size is 13732 bytes, or 34% over rv32imc.

[PCB.Wiz]

Hi. Perhaps old news elsewhere but new here ?

WCH has some more devices of interest in the pipeline...

$0.10 USD RISC-V MCU

English manual:
https://github.com/openwch/ch32v003/blob/main/CH32V003RM-EN.pdf
https://www.cnx-software.com/2022/10/22/10-cents-ch32v003-risc-v-mcu-offers-2kb-sram-16kb-flash-in-sop8-to-qfn20-packages/

Interesting part, strangely limited supply voltage range and only 10b adc, but I like the crystal oscillator present in all packages.
A MSOP10 package would be nice ? 

The 10c is a banner price, at high volumes, but LCSC does have similar parts already

https://lcsc.com/product-detail/Microcontroller-Units-MCUs-MPUs-SOCs_PUYA-PY32F003L16S6TU_C5128435.html
claims 1-7~5.5V and 12b ADC and  32kF 4kR  all for 5000+   US$0.1145
I think that does have a multiplier.

[ataradov]

8 pins is a bit low. There probably are applications where this is suitable, but I could not find any for myself. I've got STM32G0 in SO-8 package just because it was cute. But I could not find any practical uses for it.

And yes, all things being equal, I'd go with ARM.

[brucehoult]

The code size for Cortex-M0+ is 9184 bytes. The code size for RV is 10228 bytes. This is about 11% more. For comparison, rv32im code size is 13732 bytes, or 34% over rv32imc.

That is much more believable.  It would be interesting to know what A32 and A64 code size is, making the same modifications as for RV. Well, and T32 too.

[DavidAlfa]

11% larger program is not that much, what about the core performance?
Anyways, the point is you can get 5x mcus for the same money.

[brucehoult]

11% larger program is not that much, what about the core performance?
Anyways, the point is you can get 5x mcus for the same money.

Obviously that means there would be some cases where the flash is 91% full using M0+, but 101% full using RV, and that's not good. Assuming they had the same flash size in the first place. But if you're using 90% or less, then it doesn't mater at all.