CC load - interesting solution current sharing between mosfets

[Yansi]

Hello

sorry for bothering with the evergreen "electronic CC load topic", but I have just recently randomly came across some interesting solution for balancing currents for multiple parallel mosfets. I have never seen this used, elsewhere.

I was looking for something related, and a schematic popped out on me, which caught my interest immediately, this one: https://community.element14.com/products/pcbprototyping/f/forum/51307/pcb-design-for-a-dc-load
(for future-proofness, attaching cutout of relevant section)

I have also manage to locate the (likely?) original source of this solution here in this youtube video by Louis Scully. He half-explains the circuit in the beginning.


The function of the circuit is relatively simple to follow, as the voltage drop at the source resistor controls the collector current, subtracting from the gate voltage via the collector (and series gate) resistor.

My question is, can this circuit work in practice? What I see, is the used combination of Rc (2k2) / Re (270k, later he uses 47k) for the NPN gives a rather very low gain, which may not be enough to create a proper negative feedback to stabilize the current.

What is the typical tempco of Vgsth voltage for a common mosfet say like IRF540N or such? These values are very rarely given in the datasheet and I am guessing wide spread of such parameter too. I admit I have never even tried to characterize that.

Knowing that, one could at least make a ballpark calculation whether such solution is feasible and could be used in practice.  Cause looking at it, significantly larger negative feedback is given just by the presence of the enormous 1 ohm resistor in the source, rather than the very low gain of the NPN.

Thank you for any opinions.

[PCB.Wiz]

My question is, can this circuit work in practice? What I see, is the used combination of Rc (2k2) / Re (270k, later he uses 47k) for the NPN gives a rather very low gain, which may not be enough to create a proper negative feedback to stabilize the current.

I have seen a broadly similar approach of local NPN used to balance gates on output MOSFETS (but cannot find the link now..)
I think you are correct, the values given are suspect. You need to generate +/-1V  ballparks at the gate to correct Vgs variations.

What is the typical tempco of Vgsth voltage for a common mosfet say like IRF540N or such? These values are very rarely given in the datasheet and I am guessing wide spread of such parameter too. I admit I have never even tried to characterize that.

Sone vendors do list that, usually -2 to -5mV/K ballparks, but the VGD threshold variation is more.

[moffy]

This is a case where a SPICE simulation might be handy, you could create four variations of the say IRF540 with different Vto values and play with the resistor values for the desired result.

[langwadt]

there's a thread here on eevblog that discussed that configuration, but I can't remember where it is

[PCB.Wiz]

This is a case where a SPICE simulation might be handy, you could create four variations of the say IRF540 with different Vto values and play with the resistor values for the desired result.

Here is an example using the same gate series R as in #1, but with Reference and Tracker differential applied to the gates.
To test it, I used different MOSFETS for reference and tracker and the gates do shift as needed to nominally match the source voltages.

[tszaboo]

I mean, even if this works, you might as well just use NPN transistors for the load. The compliance voltage is going to be high anyway, because of your 1 Ohm resistor.

[moffy]

Here is an example using the same gate series R as in #1, but with Reference and Tracker differential applied to the gates.
To test it, I used different MOSFETS for reference and tracker and the gates do shift as needed to nominally match the source voltages.

Turning the monitoring transistors into differential pairs is a clever idea, that would make it possible to drop the value of the current sensing resistor, and the compliance voltage.

[Yansi]

Yes, that is exactly what I was thinking about. If you can afford 1 ohm resistors (crazy high value) for each FET, there is no point in trying with the NPNs. Witch much lower value like 100 mR the NPNs start to make sense.  Especially the differential pair idea actually is very nice.

Would it work as a "triferential" or "quadferential" ( ) for 3 or 4 or ... N  mosfets too?  I would guess yes. 

I can create an LTspice sim, however I do not know how to modify a FET model, so I can have for example multiple fets of same type (library model) and just adjust the Vto for each individually? Can it be done or do I need separate models for each?

[Yansi]

I have tried this configuration of the "triferential" pair. Seems it works  too.

However, what current matching did you get PCB.wiz?  Seems it provides for some Vto compensation, am getting like ~8% difference in current for the fet with lower threshold voltage. I guess that is good enough for practice? As normally the threshold voltages should not be that much different (same types of all fets on the same heatsink).

[tszaboo]

Yes, that is exactly what I was thinking about. If you can afford 1 ohm resistors (crazy high value) for each FET, there is no point in trying with the NPNs. Witch much lower value like 100 mR the NPNs start to make sense.  Especially the differential pair idea actually is very nice.

Would it work as a "triferential" or "quadferential" ( ) for 3 or 4 or ... N  mosfets too?  I would guess yes. 

I can create an LTspice sim, however I do not know how to modify a FET model, so I can have for example multiple fets of same type (library model) and just adjust the Vto for each individually? Can it be done or do I need separate models for each?

No, what I mean is that you can just replace the FETs with an NPN. Much more stable in terms of oscillations and much easier to parallel.
Also, I don't usually trust these load projects, unless they are extensively tested. Heating the FETs to 75C, their characteristics changes, you run it at higher or lower temperature their characteristic changes. You have a different heatsink and whatever worked for someone else blows up the same FET. Having an opamp per FET is actually not that expensive.

[moffy]

I have tried this configuration of the "triferential" pair. Seems it works  too.

I don't believe I've ever seen your 'triferential pair' before, interesting idea, bring back the LM3046.

[Yansi]

Yes, that is exactly what I was thinking about. If you can afford 1 ohm resistors (crazy high value) for each FET, there is no point in trying with the NPNs. Witch much lower value like 100 mR the NPNs start to make sense.  Especially the differential pair idea actually is very nice.

Would it work as a "triferential" or "quadferential" ( ) for 3 or 4 or ... N  mosfets too?  I would guess yes. 

I can create an LTspice sim, however I do not know how to modify a FET model, so I can have for example multiple fets of same type (library model) and just adjust the Vto for each individually? Can it be done or do I need separate models for each?

No, what I mean is that you can just replace the FETs with an NPN. Much more stable in terms of oscillations and much easier to parallel.
Also, I don't usually trust these load projects, unless they are extensively tested. Heating the FETs to 75C, their characteristics changes, you run it at higher or lower temperature their characteristic changes. You have a different heatsink and whatever worked for someone else blows up the same FET. Having an opamp per FET is actually not that expensive.

Sure, but FETs are easier to drive - no current hungry bases.  And bipolars can make some lovely oscillations too, especially when using some modern linear one with 30+ MHz transition frequency and longer wires - as usually contained in various diy builds. Secondary breakdown is a problem for higher voltage loads.  I dunno... I would not go for bipolar transistor for a load project at all.


moffy: Yeah... still have some pieces in my drawers.   

[mawyatt]

Here's an approach that utilizes a op-amp instead of the npn sense transistors, should produce better load current balancing. Simple LM324 or LM358 should work. Whoops should be n*Vc/R!!!

Best

[mawyatt]

Seems to work

Some "ringing" on rising edge which can be felt with by simple RC compensation.

Scale Factor is 4*Vin/Rs, or 10A/V in this case.

Concept can be extended as required.

Best

[tszaboo]

Please place a resistor in between the gate and the opamp output. 47Ohm typical. Otherwise it's just oscillation galore.

[mawyatt]

Please place a resistor in between the gate and the opamp output. 47Ohm typical. Otherwise it's just oscillation galore.

That's why we indicated as the RC compensation above, actually you'll need a shunt cap between the op-amp output and negative input as well a series R to gate

BTW here's the results with 4 completely different NMOS device with different Rdsons!

Seems to work really well in balancing the NMOS source currents:-+

Edit: Here's what we were talking about wrt RC compensation. Of course we haven't done any analysis to determine the proper compensation values. BTW note that each NMOS device is totally different model, yet the source currents are balanced as shown in the plot.

Best

[PCB.Wiz]

I have tried this configuration of the "triferential" pair. Seems it works  too.

Yes, below is a quad version. This now relies on the VBE matching across multiple NPN, whilst you can easily buy matched pairs.
Again, that lower matching may be good enough. It does need slightly less total power.

You do not really care if one transistor has 10% more current, and a design might even skew the currents so the fets in the worst locations are a bit less.

However, what current matching did you get PCB.wiz?  Seems it provides for some Vto compensation, am getting like ~8% difference in current for the fet with lower threshold voltage. I guess that is good enough for practice? As normally the threshold voltages should not be that much different (same types of all fets on the same heatsink).

The % skew depends on how much you tolerate across the matching gate resistors and the % of IC that causes.
It is just a simple transistor diff so that's appx 18mV for a 2:1 current change.

The circuit below has larger drop, and less gate skew, so it manages 2.93mA dI on 498.5mA peak (0.6%) as it nulls a 463mV gate skew

[PCB.Wiz]

Here's an approach that utilizes a op-amp instead of the npn sense transistors, should produce better load current balancing.

Yes, that's very common on active loads. 
The DC skews now shift to the opamp offset specs, so a design can pick where on the price/offset curve they want to be.
Another advantage is there is less power cost in the matching elements and no negative supply is needed.

[langwadt]

Yes, that is exactly what I was thinking about. If you can afford 1 ohm resistors (crazy high value) for each FET, there is no point in trying with the NPNs. Witch much lower value like 100 mR the NPNs start to make sense.  Especially the differential pair idea actually is very nice.

Would it work as a "triferential" or "quadferential" ( ) for 3 or 4 or ... N  mosfets too?  I would guess yes. 

I can create an LTspice sim, however I do not know how to modify a FET model, so I can have for example multiple fets of same type (library model) and just adjust the Vto for each individually? Can it be done or do I need separate models for each?

No, what I mean is that you can just replace the FETs with an NPN. Much more stable in terms of oscillations and much easier to parallel.
Also, I don't usually trust these load projects, unless they are extensively tested. Heating the FETs to 75C, their characteristics changes, you run it at higher or lower temperature their characteristic changes. You have a different heatsink and whatever worked for someone else blows up the same FET. Having an opamp per FET is actually not that expensive.

Sure, but FETs are easier to drive - no current hungry bases.  And bipolars can make some lovely oscillations too, especially when using some modern linear one with 30+ MHz transition frequency and longer wires - as usually contained in various diy builds. Secondary breakdown is a problem for higher voltage loads.  I dunno... I would not go for bipolar transistor for a load project at all.


moffy: Yeah... still have some pieces in my drawers.   

FETs might not really have secondary breakdown, but lots of modern FETs doesn't exactly have impressive SOA when driven linearly

[PCB.Wiz]

One key benefit of FETS, especially in control loads, is the drain/load current is very easily sensed in the source lead.

A BJT can sense emitter current, but that is not exactly equal to collector or load current.
 

[Yansi]

Why not? Measure just the load current, instead of the emitter current (Ib+Ic).

It will still operate with single supply opamp (LM358/LT1013), the current sensed over the shunt is just presented as negative voltage to the feedback circuitry.

FETs might not really have secondary breakdown, but lots of modern FETs doesn't exactly have impressive SOA when driven linearly

Sure, one must either pay premium for some IXYS FETs made from a unicorn, or stick with old proven parts, that are known to operate safe in linear mode like BUZ11, IRF540, IRFP250, ... But god knows what awful improvements nobody asked for these got over the years.

[Yansi]

Continuing with the "quad-ferential" thing for balancing currents: I hated those 2k2 resistor in the gates, those add an awful pole in the loop together with the gate capacitance. Adding EF solves the issue very neatly. Attaching the LTspice ASC file, so you can play around with it.

Maybe after all those years, I will finally make myself a "diy CC load"?  I'd like to see this "quadferential" thing in practice, to test how well it balances current.

[udok]

That’s far too complicated. Use cheap TIP142 Darlingtons with an emitter resistor.
The MOSFETs are a poor choice from the outset: they’re not designed for continous DC current, lack a proper high-power package and need a high V_GS and are obsoleted.
More importantly, for a robust circuit you need a fast current limiter. The emitter resistors also act as a current limiter when a BC846 is added.

[mawyatt]

Seems to work

Some "ringing" on rising edge which can be felt with by simple RC compensation.

Scale Factor is 4*Vin/Rs, or 10A/V in this case.

Concept can be extended as required.

Best

Works well with Bipolar (Darlington) also. Having the high gain op-amp with low offset makes the current handling active device Power MOS or Bipolar matching almost insignificant. Discrete bipolar devices for the current sensing are not going to perform as well as a simple op-amp configuration, as they'll usually have higher Vbe offset, base/bias currents, beta and Early effects, and all with the temperature dependance. The high open-loop gain of the op-amp absorbs the differences between the active current handling devices and exhibits a low offset over temperature to maintain a balanced current sharing.

Best 

[tszaboo]

One key benefit of FETS, especially in control loads, is the drain/load current is very easily sensed in the source lead.

A BJT can sense emitter current, but that is not exactly equal to collector or load current.

I don't see why this is an issue. The local shunt/transistor is only going to be used for current sharing, you will need another shunt for the measurement anyway. Otherwise the accuracy is bad, or you need a lot of accurate shunts and measure each.

Sure, but FETs are easier to drive - no current hungry bases.  And bipolars can make some lovely oscillations too, especially when using some modern linear one with 30+ MHz transition frequency and longer wires - as usually contained in various diy builds. Secondary breakdown is a problem for higher voltage loads.  I dunno... I would not go for bipolar transistor for a load project at all.


moffy: Yeah... still have some pieces in my drawers.   

They sold probably a billion Class A or B audio amplifiers with these parts, which works very similar to a DC load.