Let me see if I can describe the problem more accurately.
The CPU is executing a JMP instruction. There is a ROM and a RAM. ROM is from 0x00 to 0x7F. RAM is from 0x80 to 0xFF. The CPU starts at 0x00, and there is a JMP to address 0x80. At 0x80 there is a JMP back to 0x00. The cpu was supposed to just loop there.
It starts well and executes the first JMP. It has to do 3 steps (3 clock cycles) to do this. It does it very well, with all control bits shown correctly via LED's. (there are 32 control bits).
Then when it gets to 0x80, it loads the JMP, and jumps back to 0x00. It does this a few times, and then it glitches, and the control bits are junk.
Since it works a few times, why would it glitch afterwards? Very strange. The fast I go on the clock the faster it glitches.
Here's the microcode for the FETCH routine.
0x00: 00100000, 00100001, 10000001, 00001000, * PC_Out, IMMVal=0, IMMOut, ALU=1001, ALUMode=0, CarryInMux=01, MAR_Wrt, type=seq(00) *
00001000, 00000000, 00000010, 00000000, * RD, IR_Wrt, type=seq (00)*
00100011, 10100001, 00000001, 00001100; * PC_Out, PC_Wrt, ALU=1001, ALUMode=0, CarryInMux=01, IMM_Out, IMMVal=1, type=post-fetch(11) *
and here's the microcode for the JMP instruction.
0x1B: 00100000, 00100001, 10000001, 00001000, * PC_Out, MAR_Wrt, IMM_Out, IMM(0), CarryInMux1=0, CarryInMux0=1, ALUOp=1001, ALUMode=0, Next=00 *
00001000, 00000000, 01000100, 00000000, * RD, MDRIn_Mux=1, MDR_Wrt, next=00 *
00100010, 10100001, 00001000, 00001000; * MDR_X_Out, PC_Wrt, IMM_Out, IMM(0), ALUOp=1001, ALUMode=0, CarryInMux1=0, CarryInMux0=1, type=10(pre_fetch) *
Each line is a clock cycle's worth. Each column is one byte from each of the 4 ROMS.