DDS Function Gen Layout Review

[jgrossman]

I would consider 220 ohm for R31, R31. R34 and R26 get than larger due to the additional loading. Probably around 270 ohm for R34 and some 400 ohm for R26. The simulation should help to get the right values here.  The loading due to the differential amplfiier is a bit tricky to calculate in the head.

When I use asymmetrical resistors for R34/R26, the OP output has a pretty bad DC offset. When R31=R32=270R and R26=R34=400R, the amplitude of the positive and negative peak are within 1% of each other (~2.9V). The voltage directly from the current source is ~400-450mV, which seems to me to be plenty of headroom from the 600mV max. I'm not really sure in SPICE how to correctly measure the load of the OP to be able to make a more informed decision other than "lets just plop some numbers down and measure some points".

@jgrossman,
Resistors R23 and R24 forming the voltage divider drive FS_adjust seem to be too high to me.  I would try to make them an order of magnitude lower than R25 (6.8KΩ).  You want the current through the divider to dominate over the current going into FS_adjust.  I don't know what the peak voltage is of a STM32 DAC to suggest values.

Refering to the AD9834 Eval Board, they have a 100nF capacitor on the FS_adjust to ground.  Seems like a good idea to reduce noise and provide a stable reference.

Yeah, that's a good point. I just plopped in the numbers given to me by the TI voltage divider tool, but they are both available in a lower decade (187 and 107). The STM32 DAC is 0-3.3V, which I'm scaling to 0-1.2V. I also think a cap on the voltage ref is a good idea, will probably do that on the input to the voltage offset circuit as well. Also going to change the range scale on that from ±2.5V to ±2.75V to give myself room on both sides, since I actually want to perform at ±2.5V, and if either end isn't perfect (and it won't be) I am basically SOL.

[MarkF]

@jgrossman,
Resistors R23 and R24 forming the voltage divider drive FS_adjust seem to be too high to me.  I would try to make them an order of magnitude lower than R25 (6.8KΩ).  You want the current through the divider to dominate over the current going into FS_adjust.  I don't know what the peak voltage is of a STM32 DAC to suggest values.

Refering to the AD9834 Eval Board, they have a 100nF capacitor on the FS_adjust to ground.  Seems like a good idea to reduce noise and provide a stable reference.

Yeah, that's a good point. I just plopped in the numbers given to me by the TI voltage divider tool, but they are both available in a lower decade (187 and 107). The STM32 DAC is 0-3.3V, which I'm scaling to 0-1.2V. I also think a cap on the voltage ref is a good idea, will probably do that on the input to the voltage offset circuit as well. Also going to change the range scale on that from ±2.5V to ±2.75V to give myself room on both sides, since I actually want to perform at ±2.5V, and if either end isn't perfect (and it won't be) I am basically SOL.

A 100nF capacitor might be a little big.  Since you have lots of program memory in the STM32, you could probably emulate an 'amplitude modulated' signal.  Setting the carrier freq in the DDS and then varying the FS_adjust.  You will have to generate a sine wave via a timer interrupt.  The STM32 might be fast enough to get up in the 100KHz if you use fixed point math.  I can point you to some online lectures from Cornell Univ. if needed for that.  Might be useful for testing some device. 

R23 = 360Ω and R24 = 200Ω might be acceptable choices.  You also need to insure you're not overloading the current capabilities of the STM32 DAC.

I actually have a cap in the feedback of the 'offset voltage' op-amp to clean it up.  Don't know if that is the right place or how I got there during testing.  As far as having the offset being symmetrical, it just has to be close.  You will correct the centering and +/- range in software when you do the calibration.  You will adjust it for center and then limit the value to the lesser of the two sides.

[jgrossman]

For a variable amplitude one could replace the inverters with AND or NOR gates and than use 4 x 200 ohm resistors as a simple 2 bit DAC by choosing how many of the outputs are active and how many are fixed GND. This would allow levels of 5 V , 3.75 V, 2.5 V and 1.25 V. With slightly different resistors (e.g. a mix with 220 and 180/150 ohm) one could get more and different levels. For the actual levels one would also need to include the output resistance of the chips (some 30-50 ohm).

As long as the parallel resistance is about 50Ohm, I can pick any values I want, right?

Looking at this quad-and:
https://www.ti.com/lit/ds/symlink/sn74hcs08-q1.pdf

In the graph, R_low ≈ 34Ohm, R_high ≈ 45Ohm, so I picked 40Ohm to use as the "average" output resistance to add to the nominal resistor values I pick.

Using these resistors, I get pretty nice levels for 3.3V, 2.5V, 1.8V, and 1V, and adding 40Ohm to each gets a 49.162 Ohm output impedance:

A 100nF capacitor might be a little big.  Since you have lots of program memory in the STM32, you could probably emulate an 'amplitude modulated' signal.  Setting the carrier freq in the DDS and then varying the FS_adjust.  You will have to generate a sine wave via a timer interrupt.  The STM32 might be fast enough to get up in the 100KHz if you use fixed point math.  I can point you to some online lectures from Cornell Univ. if needed for that.  Might be useful for testing some device. 

R23 = 360Ω and R24 = 200Ω might be acceptable choices.  You also need to insure you're not overloading the current capabilities of the STM32 DAC.

I actually have a cap in the feedback of the 'offset voltage' op-amp to clean it up.  Don't know if that is the right place or how I got there during testing.  As far as having the offset being symmetrical, it just has to be close.  You will correct the centering and +/- range in software when you do the calibration.  You will adjust it for center and then limit the value to the lesser of the two sides.

Yeah, I guess that would be compensated for with cal. So is the target equal current from IOUT/IOUTB?

I would appreciate those lectures, yeah!

[jgrossman]

Is this a valid layout for the filters following ad9834? I tried to adhere to AN-837 from analog devices. Those vias are going to an internal ground plane.

[Kleinstein]

For the resistor values for the square wave output one is not totally free, not to overload one channel. The values shown look OK with not too much differences.

The filter layout looks OK. I would prefer to have the filter a little closer to the DDS chip and the resistors R32 and R31 towards the center GND instead the outer GND. The sum of the 2 currents from the DDS chip is constant and thus a reasonable good compensation of the AC component. I see no real need to keep the 2 filter sides so far seprated. 

For the amplifier it may be better to have R27 and R29 closer to the inverting input pin of the OP-amp. One should normally keep the capacitance of the inverting input node small.

[MarkF]

Here are the two relevant lectures from the ECE 4760 course at Cornell Univ.  The course is centered around the PIC32 32-bit microcontroller.  There are 31 lectures in total.  If I remember correctly, they claim they can generate frequencies up to 900MHz.  But the PIC32 uses a 40MHz clock and I believe they used its DMA channels to accomplish those frequencies.

In addition, there are two other years available for this course.  An earlier year centered on the AVR microcontroller and currently they are using the Raspberry Pi Pico for the course.

[jgrossman]

Here are the two relevant lectures from the ECE 4760 course at Cornell Univ.  The course is centered around the PIC32 32-bit microcontroller.  There are 31 lectures in total.  If I remember correctly, they claim they can generate frequencies up to 900MHz.  But the PIC32 uses a 40MHz clock and I believe they used its DMA channels to accomplish those frequencies.

In addition, there are two other years available for this course.  An earlier year centered on the AVR microcontroller and currently they are using the Raspberry Pi Pico for the course.

Thanks for the links. I'd have to do a trade study, but given that my STM32 has 192kB of flash, I might just bake in a sine table that maps onto the FS_adjust pin and use DMA triggered at the modulation frequency to the DAC. I haven't watched these yet, but I would imagine that's similar to how a DMA-based solution would work there.

[MarkF]

Here are the two relevant lectures from the ECE 4760 course at Cornell Univ.  The course is centered around the PIC32 32-bit microcontroller.  There are 31 lectures in total.  If I remember correctly, they claim they can generate frequencies up to 900MHz.  But the PIC32 uses a 40MHz clock and I believe they used its DMA channels to accomplish those frequencies.

In addition, there are two other years available for this course.  An earlier year centered on the AVR microcontroller and currently they are using the Raspberry Pi Pico for the course.

Thanks for the links. I'd have to do a trade study, but given that my STM32 has 192kB of flash, I might just bake in a sine table that maps onto the FS_adjust pin and use DMA triggered at the modulation frequency to the DAC. I haven't watched these yet, but I would imagine that's similar to how a DMA-based solution would work there.

After watching the lectures, I built a small eval PCB and using a 256 byte sine table with the audio CD 44.1KHz sample frequency was able to cover the audio frequencies with a MCP4822 DAC.  While looping it back into the PIC32 doing a fixed point FFT on a small OLED display.  So, you don't need a lot of memory for the sine table.  I actually had two tables.  One for a sine waveform and one for a triangle waveform.  You can put any waveform shape into the lookup table as long as it's periodic.

I used DMA to get the FFT samples.  But, just a timer interrupt to generate the waveform.

[jgrossman]

Here's what I have for my updated design:

Schematic:






Board Layout (stackup is signal-gnd-pwr-signal, but inner planes omitted for clarity):




Front is actually bottom (going to mount on some motherboard standoffs+feet), back side is top, with output BNCs and OLED and rotary switch.

• I really don't like the CH2 attenuation U5/U6/U7, it's pretty much a cluster. Not sure what can be done here.
• Not really sure to what extent via stitching to power planes by U1 is necessary... kindof just went all in, since I can just take them away if too many
• I made vias that are not under the screen blind vias where possible, what is the downside, if any? The only reason is to have a cleaner user-side where I'm going to put some text to the right of the controls/output.
  

[Kleinstein]

The digital outputs should be 74AC08 or similar. 74LS... does not work with 3.3 V and has weak drivers at the high side.
With enough free pins at the µC one could skip the 2 extra logic chips to decode the amplitudes and use 4 lines from the µC instead.

With a 12 V supply one may run into limits of the power that USB can deliver. The OP amp for the output needs quite some power.

At the very least cooling of the OP-amp would need extra copper connected to the pins (except pin 2) on the top, including the NC pins.
There is little need for 0.5 % resistors at the differential amplifier.
I think the resistors at the filter ouput still don't inlcude the effect of loading by the amplifier stage.

The 50 ohm output resistor and the divider should also use larger resistors, like 1206 or maybe a combination of 2 or 4 x 0805.

The attenuator should also have a ground link already on the top layer. For mechanical stability it may be good to solder the connectors also on top and have soem ground there.

[jgrossman]

The digital outputs should be 74AC08 or similar. 74LS... does not work with 3.3 V and has weak drivers at the high side.

Yeah, I forgot to change the value in Kicad, I would be using sn74hcsXXX I linked above instead 

With enough free pins at the µC one could skip the 2 extra logic chips to decode the amplitudes and use 4 lines from the µC instead.

I was trying to make it so every combination was a "valid" one, but I mean... I don't really see why I even care. I'm sure I could route two of my many free pins over there instead. Though it's still a bit of a mess since the CH2 input is on both sides of the IC...

With a 12 V supply one may run into limits of the power that USB can deliver. The OP amp for the output needs quite some power.

Would this circuit really exceed the 500mA limit for USB 2.0?

At the very least cooling of the OP-amp would need extra copper connected to the pins (except pin 2) on the top, including the NC pins.
There is little need for 0.5 % resistors at the differential amplifier.
I think the resistors at the filter output still don't include the effect of loading by the amplifier stage.
The 50 ohm output resistor and the divider should also use larger resistors, like 1206 or maybe a combination of 2 or 4 x 0805.
The attenuator should also have a ground link already on the top layer. For mechanical stability it may be good to solder the connectors also on top and have soem ground there.

All good points. I definitely tweaked those resistors, but I forgot to copy the values over from SPICE 

Thanks 

[Kleinstein]

For the power needed it gets close with a correct 50 ohm termination at the load. Some 10 V at 100 ohm load would be 100 mA from the 12 V and this may need some 300 mA from the 5 V (or a bit less). With a short at the output the current may be higher in theory, but chances are the OP-amp with go to current limiting.

The charge would however run into problems earlier. Not sure if it likes +12 V to -12 V at all. Some of the chips have a limit more at some 16 V between both ends, so +-8 V max.

[MarkF]

Do you really need a four layer PCB?
I use a two layer PCB with a ground copper pour on both sides.  I run wide traces for +5V, +12V and -12V.
Attached are my two layers showing the copper pours.

The 50Ω output resistor is a 1210 size to handle the higher current.  Also, the traces from the op-amp to the BNC are a little wider than normal.  Same for the 'digital' BNC.

Notes on your digital output:
  - Insure the STM32 pin is PWM capable
  - If possible, have all the pins that select the ch #2 logic level be on the same port.  I say this so that when you update the level (i.e. a port write) all pins change simultaneously.  You may run into some case where you don't want any switching spikes due delays in pin edges caused by multiple CPU write cycles.

For the power needed it gets close with a correct 50 ohm termination at the load. Some 10 V at 100 ohm load would be 100 mA from the 12 V and this may need some 300 mA from the 5 V (or a bit less). With a short at the output the current may be higher in theory, but chances are the OP-amp with go to current limiting.

The charge would however run into problems earlier. Not sure if it likes +12 V to -12 V at all. Some of the chips have a limit more at some 16 V between both ends, so +-8 V max.

He's not going to get anywhere close to those kind of loads.
With a 50Ω load, 2 or 3V_p-p output is about all the lm7171 in a SOIC package is going to handle before melting.  Even with all the heat dissipation.  Ask me how I know?

I drive my lm7171 with +/-12V.  It's maximum V_max - V_min = 36V.

I was wondering if a lower supply voltage to the lm7171 (say +/-9V) might reduce the power drop and allow a larger output voltage swing???
I never looked into the relationship between power supply vs output voltage concerning heat dissipation.

[jgrossman]

Do you really need a four layer PCB?
I use a two layer PCB with a ground copper pour on both sides.  I run wide traces for +5V, +12V and -12V.

"Need" in the strict sense, no. It was just easier to layout, with the added benefit of a little more thermal mass. It made it easier to keep all SMD components on one side without a bunch of jumping to the other side of the board so that the top side with the controls would look better.

It's not like I have a ton of powered parts, It could absolutely be 2-layer with ground pour.

  - Insure the STM32 pin is PWM capable

I was wondering if a lower supply voltage to the lm7171 (say +/-9V) might reduce the power drop and allow a larger output voltage swing???
I never looked into the relationship between power supply vs output voltage concerning heat dissipation.

Funny you mention that because I did indeed royally screw the pinout in a few places after I realized that I've been using the STM32CubeMX tool to keep it all straight.

I moved from +-9 to +-12 volts only because the OLED V_cc is +12V

For the power needed it gets close with a correct 50 ohm termination at the load. Some 10 V at 100 ohm load would be 100 mA from the 12 V and this may need some 300 mA from the 5 V (or a bit less). With a short at the output the current may be higher in theory, but chances are the OP-amp with go to current limiting.

The charge would however run into problems earlier. Not sure if it likes +12 V to -12 V at all. Some of the chips have a limit more at some 16 V between both ends, so +-8 V max.

Not sure if you mean the +-12V generation or the OP, but as MarkF said the OP is 36V differential max. I switched from the MAX1044 (no A) to the MAX1044A because the former was only +-10V, which was fine when I was using +-9, but I've now moved to +-12 to satisfy OLED power.

[MarkF]

A two layer PCB will be much cheaper to get manufactured.
__________________________

I used a Waveshare OLED module that generated it's own 12V.  It only needs 3.3V power.  It has a SPI interface.
  https://www.amazon.com/gp/product/B07DB5YFGW/ref=ppx_yo_dt_b_asin_title_o02_s00?ie=UTF8&psc=1
__________________________

While you're laying out pin assignments...

Let's think of a scenario:

• You can get all the STM32 bits for the channel 2 into one 8-bit port.  Both the levels and the PWM/On/Off pin.
  
  
• Externally send a table of 256 bytes, each containing one sample, to the STM32.
  
  
• Setup a timer interrupt with the duration of each sample.
  
  
• You sequence thru the table writing each sample to your channel 2 control port when the interrupt occurs.
  
  
• You now have an arbitrary waveform generator that is able to output a short message.
  
  
• You can also simulate a runt pulse since the samples contain both high/low and the level.

[jgrossman]

Yeah, I was going to use one of these only because I had 2-3 of them anyways... but for simplicity sake I probably will go for a solution that can power itself from 3.3V or 5V. Added benefit is being able to display anything at all, the type I have are just 4 line character displays.

Given that I wouldn't need to provide the OLED V_cc directly, I could almost surely get away with any supply voltage for the OP that gives me enough headroom at the maximum/minimum DC offsets. I'm thinking of fabricating a board for the LM7171 to be able to better characterize it's temperature/current draw with different supply/output voltages, as well as the current consumption of the supply voltage generation:



Not sure if I want/need to put some constant current sources here to try and do the filter as well, since I'm mostly trying to mess with the LM7171

WRT to 2/4 layer fabrication costs, it seemed to not make a difference on JLCPCB, though I would agree that in general, 4-layer must be more expensive, just because mo' stuff is mo' money.

[MarkF]

I bought a bunch of these breakout boards from Adafruit some time ago.  Lots of varities.
   https://www.adafruit.com/category/198

You might even want to consider the through-hole DIP package for the LM7171.  Just for the dissipation.
Although, I seriously doubt you're going to be able to reach the output levels you want.

I guess JLCPCB pricing has changed since I last checked.  Must be doing a lot of business...   



Your capacitors on the power supply rails of the LM7171 on the breakout board make no sense.
They should go to ground.  Both sides of the caps connected together do nothing.   

[jgrossman]

Your capacitors on the power supply rails of the LM7171 on the breakout board make no sense.
They should go to ground.  Both sides of the caps connected together do nothing.   

  thanks

[jgrossman]

Breakout schematic:



Breakout layout:

[Kleinstein]

The OP-amps definitely need more copper area near there pads for cooling. Most SMD parts get rid of the heat via the PCB and thus need extra copper for higher power parts. Ideally also connect the NC pins to copper / ground.

[MarkF]

Question.  More for my info than anything.  Google search hasn't given me much insight.

Why use a Tee attenuator in the 50Ω output path?

More specifically, why use a Tee attenuator over a Pi configuration?
What are the advantages and disadvantages of each?
What do you base a choice on?

[jgrossman]

The OP-amps definitely need more copper area near there pads for cooling. Most SMD parts get rid of the heat via the PCB and thus need extra copper for higher power parts. Ideally also connect the NC pins to copper / ground.

Where in the goldilocks scale is this? Still too little, too much, or somewhere in between? Vcc/Vee highlighted in red, and all GND and NC are connected to the ground pour without thermal reliefs where feasiblee

[MarkF]

It won't be enough.

My op-amp at 4V_p-p into 50Ω got so hot you couldn't touch it in seconds!!!

The only way you will get near 8V is into a high impedance load.

[jgrossman]

Revisiting using a heatsink on the LM7171... as you noted I may also be better off with the DIP package to better be able to transfer heat into the board. Big reason I'm making this breakout board is to be able to see what is required thermally for LM7171, as I'd really like to get 5V_p-p unless it becomes apparent that would require an excessive amount of effort.

Are all opamps this way? What intrinsic parameters of the opamp typically contribute to higher heat (GBW, etc)? Is the signal of the op-amp relevant to the energy consumption, or just the gain, or both?

[Kleinstein]

For the heat there are 2 parts:
1) The load current at about 2/3 the amplitude so that half the voltage is at the load and 50 ohm termination resistor. With higher voltage the heat goes down again from less voltage. The FB resistors are a little extra load, often neglegible though.

2) The no load current of the OP-amp. Here it is mainly a high GBW that need more internal current, but there are also more and less power hungry ones. Newer ones may be lower power for the same speed.

For the amplitude it makes a difference if the 5 V_pp are for a high impedance load or with 50 ohm termination.
5 V_pp even with termination would need the amplifier to provide 10 V_pp and thus likely a supply of some +-7 to +-10 V.

20 V and some 6 mA of no load current would be 120 mW - not very much.
5 V to a 100 ohm load results in 50 mA and thus some 5 v * 50 mA = 250 mW of power loss. This should still be OK for an SO8 with some copper area.
Even a short with thus 2 x the current would "only" be 500+120 mW. With some 200 K/W of thermal resistance this would be some 134 K temperature rise for the chip, which is boarderline, but usually still ok. It could still need the extra copper to spread the heat and ground plane and maybe some extra heat sink to the chip or PCB.
With more than +-10 V supply a short at the output could be an issue. Some chips have thermal protection too.

RF circuits tend to run a bit hotter than LF.