De-capping & circuit analysis of hybrid modules

[D Straney]

Thought it was time to do some more detailed reverse-engineering on the various ceramic hybrid modules I've opened:

Analog Devices HTS-0010SD Track and Hold


Here's the datasheet.

This is a fairly high-speed "track and hold" (/ "sample and hold") circuit, which can rapidly sample an input waveform - commonly used as part of an analog-to-digital converter, or to downconvert a high-frequency signal for slower processing.  This one has a bandwidth of 60 Mhz (17 ns period) but needs about a 10 ns sampling window for the output to settle within 1%, so the usable frequency for a sampling oscilloscope, for example, would be more in the single-digit-Mhz range.

Here's how the internal components are divided up, and the complete schematic I traced from a microscope photo:


Most of the large squares are actually capacitors (two horizontal plates separated vertically by a thin dielectric), used for local filtering of the many power supplies.

Input buffer
This section buffers the incoming signal to drive the sampler.  The signal drives two complementary sections, whose outputs are then re-combined by R7, to produce an output which can actively source and sink current.  Having the sequential emitter-followers with an NPN followed by a PNP (and a PNP followed by an NPN) roughly cancels the DC offsets from each transistor's Vbe, if biased correctly.  I wouldn't expect the linearity to be great, as the Vbe values would change depending on load current, but the datasheet shows 0.01% non-linearity for a 1V max. input: the low signal voltage compared to the supply voltage (small change in bias current) and low output current required due to small hold capacitor value & high-impedance output buffer must help a lot.

Sampling bridge
This is a standard 4-diode sampling bridge: I can't find any references that explain their basic operation well (Edit: RoGeorge mentioned an explanation on p.66 of this Tektronix appnote), but the idea is that you forward-bias all the diodes (with a current source) to turn them all on.  Because the diodes are intentionally matched to each other, D1 and D4's forward voltages are roughly equal, and D2 and D3's forward voltages are roughly equal, so the output voltage at R9 & hold capacitor C6 follows the input voltage at R8.  To turn off the "gate", you reverse-bias all the diodes, and now hold capacitor C6 is isolated from the input signal, and stores its voltage "indefinitely" (with practical limits).

Bridge driver
This section generates the forward-bias currents and reverse-bias voltages to rapidly switch the sampling bridge on and off, controlled by an ECL input.  The one actual IC in this module is an ECL buffer (or gate with hard-wired input?), which accepts a single ECL input and generates complementary ECL outputs, to drive each side of the sampling bridge separately.  (While on, the cathode-side D1/D4 voltage needs to be low, while the anode-side D2/D3 voltage needs to be high, to turn on the diodes, and vice versa for when the sampling bridge is off)

Q8 and Q11 serve as biasing for a pair of fixed current sinks (Q6 & Q7), and a pair of fixed current sources (Q9 & Q10).  The two halves of Q5 (Q5A & Q5B) serve as switches for the current sinks.  When Q5A is off, for example, Q9 sources current / connects a positive voltage to the top side of the sampling bridge.  When Q5A turns on, it connects Q6, which now (presumably) sinks more current than Q9 is sourcing, and so overall sinks current / connects a negative voltage to the top side of the sampling bridge, instead.

The speed of the sampling bridge driver is a big limitation on the speed of the whole sampler, along with the properties of the sampling bridge diodes themselves, and so to get the most out of the sampler, the switching needs to happen quickly.  The use of ECL and current sources throughout helps here because of...
1. No transistors are ever in saturation, which means that the "storage time", a significant typically-µs-scale delay when bringing a bipolar out of saturation, doesn't slow down switching.
2. The fixed currents, if set to sufficiently high values, rapidly charge or discharge the various parasitic capacitances at the switching nodes.  This provides a simple "control knob" the designer can use for selecting a tradeoff between power consumption and switching speed.
This was the standard way of doing high-speed digital switching with bipolar transistors before fast MOSFETs and CMOS logic became common a decade or two later.

Q5 is a 5-transistor array, with the same pinout & arrangement as a CA3045/CA3046 or CA3086: 3 individual transistors, and 2 connected as a differential pair.  However, surprisingly, only two of the 5 are actually used.  I don't know why they didn't use a 2-transistor matched pair for this.


Also, one mystery here is the DC behavior of the bridge driver.  With AC-only coupling via C1 & C2, only short excursions from the default state (whether track, or hold) would be allowed, and I didn't see any mention of that in the datasheet.  Also, the only valid states for the sampling bridge are with Q5A & Q5B in opposite states: having both halves of Q5 off when idle doesn't make any sense (although R15 might have something to do with that).  I think what looks like capacitors here in the bridge driver (C1 & C2) might actually be diodes for level-shifting between the -5.2V of the ECL signals, and the -15V for the rest of the bridge driver.  I can't come up with a diode configuration which actually makes sense though (even including Q5 being PNPs instead of NPNs).

Output buffer
Q12 is a JFET used to buffer the hold capacitor's value; a JFET is used here instead of a bipolar transistor because of its infinitesimal input leakage current drains the tiny hold capacitor's voltage much slower than a bipolar's base current would.  After Q12A's buffering of the hold capacitor voltage, this drives a class-AB output stage with Q14 & Q15 creating an offset voltage to compensate for Q16 & Q19's Vbe, and create an appropriate DC collector current through Q16 & Q19 at zero voltage (to avoid excessive crossover distortion).  Q12B and Q13 create a current sink to bias Q12A and Q14/Q15 at a constant current.

Just like the input buffer, with no feedback you'd expect the output buffer's linearity to suffer here as the Vbe values change with changing current, ruining the careful balancing act, and that's reflected by the datasheet.  With a 1KΩ load on the output, harmonic distortion is listed as -68 dB, but with a much heavier 75Ω load, this drops to -50 dB.  Honestly, these are still impressive numbers overall for such a simple circuit (esp. because this includes the distortion of the input buffer & sampling bridge), and this is not to criticize the design - just to illustrate the limitations and tradeoffs.

Here's Q12, a matched pair on a single die:


Feedback
At first when tracing the circuit, I thought this might be some sort of compensation for various parasitic effects of the sampling bridge.  However, on further study, this is actually a part of the bridge driver!  Q17 and Q18 create a copy of the output voltage (and therefore, a copy of the hold capacitor voltage) at R10.

Remember how I said that the transistors in the bridge driver never were put into saturation?  Without this section of the circuit, when the sampling bridge was turned off in "voltage mode" to reverse-bias the sampling diodes, both Q9 and Q7 would be in saturation: there's no path for collector current after charging the parasitic capacitances, and so their collector voltages would rise(/fall) past their base voltages.  However, D5, D6, and R10 ensure that Q9 and Q10 always are in the active region by providing a path for their collector current, and limiting how far their collector voltages can rise or fall.  R10 sets the reverse-bias voltage on D3 & D4, as (fixed current) x (resistance).

Closing
Finally, the weird silicon(?) resistors make for some interesting shapes:


Let me know if you have any insights or questions.

[D Straney]

Clarification on the "feedback" section of the circuit:
D5, D6, and R10 make the sampling bridge's off-state voltages referenced to the hold capacitor voltage.  The D1 & D4 cathodes will always be "X" volts above C6, and the D2 & D3 anodes will always be "Y" volts below C6, etc. with "X" & "Y" determined by the bridge driver's fixed current source & sink values multiplied by each half of R10.

Besides keeping Q9 & Q7 out of saturation, I think the biggest reason to do this is actually for the bridge's turn-off & off-state behavior.  When the control voltages on the sampling bridge are flipped to reverse-bias D1-D4 and close the gate, the rising voltage on D4's cathode injects current into C6 through D4's parasitic capacitance.  At the same time, the falling voltage on D3's anode pulls current out of C6 through D3's parasitic capacitance: a simple matter of dV/dt across a capacitor.  C6 has a very small value, to allow it to sample the input signal quickly (short gate-opening times) and give it a large analog bandwidth (input buffer is limited in slewing a large capacitive load quickly), so these currents can introduce some serious error into the C6 voltage.

However, because the final D4-cathode and D3-anode voltages are fixed relative to C6's voltage, and D3 & D4 are the same type with the same parasitic capacitance characteristics, the total charge injected into C6 at turn-off through D4 is going to be almost exactly equal to the charge removed from C6 through D3.  The two errors in opposite directions cancel out.  Otherwise, if the final D4-cathode & D3-anode voltages were fixed at, let's say, +10V & -10V, it means that positive output voltages would see a consistent negative error (more charge removed by moving D3's anode a larger "distance" from Vout to -10V) and negative output voltages would see a consistent positive error (more charge injected by moving D4's anode a larger "distance" from Vout to +10V).

During the off-state, having equal reverse-bias voltages across D3 & D4 also means that the leakage currents through both of them will cancel out, therefore removing another source of error which would cause C6's voltage to drift over time.  This is especially important with the Schottky diodes used in the sampling bridge: the tradeoff vs. plain P-N junction diodes is lower forward voltage and no reverse-recovery effects, for higher capacitance and higher leakage.  The D5/D6/R10 "equal negative bias" scheme here takes care of both the capacitance & leakage effects all at once.

[David Hess]

I am surprised that it is not faster.  The sampling time in this type of design is primarily limited by the RC delay of the driver and load capacitance.

[schmitt trigger]

The 8518 label in the lid must be likely the date code?

Do you know where this track and hold device came from?

[D Straney]

The 8518 label in the lid must be likely the date code?

I agree, think that's right.

Do you know where this track and hold device came from?

An eBay batch of (unused) NOS parts, that this guy got, and was kind enough to give one to me as part of a two-way duplicate swap.  It's a standard COTS part, rather than anything application-specific.  So I don't know exactly what specific pieces of equipment used this internally.

I am surprised that it is not faster.  The sampling time in this type of design is primarily limited by the RC delay of the driver and load capacitance.

Me too!  Especially with the ECL input I was expecting some couple-ns kinds of times.  Thought it was interesting that they advertised the 5 ps jitter in the sample window timing, but the slow settling time and long sampling window needed make that less impressive in practice than it sounds - unless you're going for serious precision on a slower signal, like if building a precision multi-Mhz LVDT for some reason.

[D Straney]

Teledyne C66-1 Solid-State Relay
This comes in a metal can:

Now with lid removed:

There were a couple blobs of epoxy (one over the top-left electronics, and one over the top-right electronics) that I removed to get these photos.  Removing the epoxy moved the wirebonds, so don't pay too much attention to where the wirebonds sit in the upper half.


The output switching is done by the two big power transistors in the bottom half: these are arranged back-to-back, so that the body diodes never conduct at the same time, with a shared source connection that runs up the middle between them.


These power MOSFET gates are driven optically.  The isolated control side consists of two LEDs connected in series in the top-right corner (the two tiny squares), and these shine light on a photovoltaic array right next to them (the larger square).  I'm not sure if the light is passed sideways across a small horizontal gap, or whether the light was diffused and reflected through the white epoxy blob (from LED top surface to PV top surface) to add horizontal electrical insulation.

The LEDs & mini solar cell generate a gate voltage to turn on the power MOSFETs, but the current these can produce is very low - discrete versions of PV isolators can only produce 10s of uA, from an LED current of 10s of mA.  This charges the power MOSFET gate capacitance slowly, but multi-ms turn-on times or 10s-of-ms turn-on times are fine if you're just switching a load on and off, and not trying to do 100+ kHz switching for a power supply.  However, this is a problem for turn-off: the pull-down resistor on the MOSFET gates, to discharge the gate voltage when the input drive voltage isn't present, needs to be large enough to avoid stealing all the turn-on current, but this makes the turn-off even slower than the turn-on.


There's also an IC on the power side; I accidentally took a chip out of it with my knife while trying to carefully peel away the epoxy, so although it's pretty simple, I can't fully map the circuitry.  This is probably responsible for some kind of "fast turn-off" function, to sense when the gate voltage starts to sag as the LEDs are turned off, and actively discharge the gate capacitances for a faster turn-off.

[D Straney]

TRT 3511.150.1351
I have no idea where this part was used; I just bought it as NOS from a random Polish eBay seller for a few $.




There's only one type of IC used here:

Also you can see the laser-trimming marks in this photo, where notches were cut into the resistors (made out of resistive material printed or sputtered directly onto the ceramic substrate) to adjust their values.

If we zoom in on one, we can see that they look like the Zeptobars die shot of the TL072 dual op-amp.  The butterfly-looking structures are the input JFETs, arranged in squares with paralleled devices diagonal from each other to do some first-order cancellation of thermal gradients across the die.


The actual circuitry is pretty simple:

It holds...

• 3 copies of a filter circuit, each with 2 stages of a Sallen-Key low-pass filter.  Two of these filter blocks have identical resistor geometries, while one has different-shaped resistors (the one on the bottom-right in the photos above).
• A single stage of a Sallen-Key low-pass filter
• A non-inverting gain stage of +2 (judging by resistor geometry)
• 2 un-committed op-amps, with their connections broken out to the external pins

This is a strange collection of miscellaneous things.  Where might this be used?
The TL072 / TL082 / similar parts only have a bandwidth of a few Mhz at most, so the filter corner frequencies should be in the 10s or 100s of kHz, or lower; no RF happening here.  The '99 date code on the outside puts it outside the time period (70's & 80's) where SMT was uncommon and hybrid modules were used strictly for their physical compactness (...unless it's a very long-lifetime design, or was for a mid-90's design at a place where their processes changed very slowly).  The only other reasons to make this into a hybrid module are for environmental robustness (aerospace or military applications), or to use the laser-trimming process to achieve high initial accuracy on the resistor values.  These days you can buy SMT thin-film resistors in 0.1% tolerances off-the-shelf for reasonably cheap, but wasn't always the case.  Filters are one place where component precision matters a lot, although the ceramic caps are going to have 1% tolerances at best.  It's possible that the resistors were trimmed in production to make up for the tolerances of the caps - if you look at the corner-frequency and Q formulas for the Sallen-Key filter topology, you can see that changes to the capacitor values in both cases can be balanced out by resistor changes that leave the other parameter intact.

Anyways, the short version is that I have no idea about the background of this module!  Let me know if you know anything about it.

[schmitt trigger]

Teledyne relays. Really expensive stuff.

Many moons ago I worked for aa board assembly contractor. Among the myriad of boards, there was one small board for a US Navy project. It consisted of a few SN54xx TTL devices, a handful of passive components and a metal-can Teledyne relay.
The relay was only installed after the fully assembled board, minus relay, had successfully passed all the electrical and functional tests. This to prevent scrapping the expensive relay if the board had failed, as we weren’t allowed any repairs on the unit.

[D Straney]

Wow that's wild, that's the level of care I'd expect for a 1000-pin experimental ASIC, not a relay (even a really nice one).  I've got a couple boards with their mechanical relays in metal cans, will have to try now (carefully) removing the metal can to take a look at the mechanism.

Meanwhile, I got access to a pretty nice microscope, so here's some close-ups of dies from that Analog Devices HTS-0010SD Track and Hold.
You can see the variety of structures of the resistor arrays; most of them have marks from laser-trimming of the resistances.  The arrangement of a lot of them is with many parallel tracks of varying size (effectively a lot of large resistors in parallel), some of which are selectively cut.






Then we have the transistor array (only 2 of which are used):


...a discrete transistor:


...and what I think is the dual JFET, if I remember correctly:


Edit: updated with better photos, now that the microscope's light source is fixed

[timeandfrequency]

TRT 3511.150.1351

Hello D. Straney,

Module might come from manufacturer 'TRT Defense', subsidiary of Philips.
Location : 'Moncel les Luneville' and/or 'Lunéville', France   Departement (means county/region) n°54 : 'Meurthe et Moselle'
It was later (1990 ?) bought by Thomson-CSF (now Thales) so the name was changed to 'Thomson TRT Defense' (TTD)

TRT  means 'Télécommunications Radioélectriques et Téléphoniques'
 
Plainly military stuff : the module might be an IF or audio filter for some kind of radio receiver or radar analog processing.
Information is really sparce on the Internet

https://www.aicprat.fr/news/la-belle-histoire-de-thales-saison-4-episode-03-12238
https://copainsdavant.linternaute.com/e/t-r-t-defense-1578696
https://copainsdavant.linternaute.com/e/thomson-trt-defense-194688  (most recent date is 1997)
https://www.senat.fr/questions/base/1990/qSEQ900710730.html   (Q/A to MP)
https://questions.assemblee-nationale.fr/q9/9-57726QE.htm    (Q/A to MP)

Copy the URLs here for english translation.

No information found that is more recent than 1997.
No documentation about TRT electronic parts or modules found.

[D Straney]

Appreciate the background.  It is really hard to find information about them online!

Here's another from the same manufacturer:
TRT 3511.150.13441


This one's very simple inside: 4 sets of diodes with their cathodes connected to capacitors, and the capacitors referenced to a common circuit ground(?).  There's also a completely isolated diode (on the right).  One diode-and-capacitor section (2nd from left) has 2 diodes connected in parallel.

I'm stumped about the use case for this module.  The diode-into-capacitor connection suggests to me either "analog peak detector", or "power supply output" (such as the output-side diode and capacitor for a multi-output flyback converter).  The thick traces and very large-die-size diodes support the "power" theory, while the lack of surrounding precision circuitry (op-amps, etc.) that you'd want for good peak detection, overall says that it's likely part of a power circuit.

However, I don't think these are the output rectifiers for a multi-output power supply. In the case of a switch-mode power supply, with 100 kHz+ switching and significant harmonic content in the Mhz range, the layout geometry doesn't make sense: long, winding ground trace provides a terrible high-inductance connection and makes those capacitors halfway-useless.  In the case of an aircraft-power 400 Hz power supply (the output of a step-down transformer, for example), the capacitors are too small to be useful in a frequency range where the layout doesn't hurt it - I measured 86-92 nF across the capacitors, so they're probably 100 nF nominal.  Overall, the capacitors probably can't being relied on for any kind of significant power supply filtering: at "low" frequency they'd be useless because of low capacitance, and at "high" frequency they'd be useless because of large layout inductance.

The only situation that makes sense to me, then, is a low-frequency power application not involving ifltering.  The only thing I can think of is something like a snubber for inductive loads (valves, solenoids, large relay coils, etc.): these diodes could be serving as the anti-parallel diodes that "catch" and redirect the stored "flyback" energy when an inductive load is switched off.  In the end, though, I really have no idea.  Let me know if you have any thoughts.

[timeandfrequency]

Hello D. Straney,

Appreciate the background.  It is really hard to find information about them online!

Here's another from the same manufacturer:
TRT 3511.150.13441

IMO, it is a deliberate choice that we can't find any documentation about these modules on the Internet.
This is only for military purpose. And these people do not talk or publish anything about their former or current work. I guess similar guidelines apply in the USA.
IMO, it is rather a wise decision and it has to be like that.

Indeed, this 'TRT 3511.150.13441' module looks rather basic. All of the use cases you suggested are plausible.
I have no clues why they put such a simple circuit inside an hybrid module.
Reliability purpose ? Security reasons to hinder retro-engineering and/or duplication ?
Is it just a wired programming or parameter defintion module, that activates dedicated features on a host system ?
Was that module intended to update or correct a failed design on an existing board or sub-assembly ? So it might be a replacement part for a formerly designed module.

Did you measure the forward voltage of the diodes (and perhaps their reverse leakage current) ?



I also found that TRT settled at two other locations : Guyancourt (dept. 78, Yvelines) and 'Brive-la-Gaillarde' (dept. 19 Corrèze).
And their realm is clearly military optronics.
Thermal cam for combat tank
Tunable laser source
They were also involved in the multirole combat aircraft 'Dassault Rafale' prototype at the end of the 80' and early 90', for the frontside optical thread detection and recognition system (*).

If you're looking for more information about these module, consider asking Michel : he often dismantles military gear. As far as I know, he speaks a little bit english.


(*) called 'Optonique Secteur Frontal (OSF), with staggering requirements, as written in 1989 : 40 NM range for (passive) thread detection and target follow-up.

[D Straney]

I agree that missing info on the module is unsurprising.  I was just surprised that it's hard to find even information on the company itself    So I appreciate the background info you've found on them, that's interesting.

The "hybridization" of this module could be for a combination of diode heatsinking, and reducing the number of solder joints (I believe MIL-HBK-whatever reliability measures rated wire bonds as significantly more reliable than solder joints?  Less physical mass for vibration susceptibility, more flexibility for thermal cycling).  Military optical systems seems like a rough environment, as that's all things that have to be mounted to the outside of vehicles.  It's also possible they were making a highly-module-enclosed system anyways and so it was little effort to just make one more hybrid.

Good question on the diode ratings: took a quick forward voltage reading and I think they're likely Schottkys.  I don't know the test current that my Fluke uses in "diode check mode", but these measured ~0.4V, while other 1A junction rectifiers (1N4001-ish) measured 0.6-0.7V and some 1-3A power Schottkys I have measured more like 0.2V.

[D Straney]

Yet another TRT hybrid:
TRT 3511.181.28601


Inside, this one's more complicated, as the traces have to cross over each other in a few places.  The blue you can see is an insulating layer placed in between stacked conductive layers, and underneath wirebonds that cross traces.  I had to probe around a bit on this one to trace out the circuitry, doing continuity checks with needles.


There's two TL082 dual JFET-input op-amps:

...and an LM101 single externally-compensated op-amp:


Let's look at the schematic:

Some parts of it make sense, for example...
The Inverting Input Stage in the middle is a standard inverting amplifier.

The Active DC Removal is an integrator whose output is mixed with an input signal (via R15 & R16), which has the effect of cancelling any DC that appears at the R15/R16 junction.  The advantage over just using an RC HPF is, I think, that you can choose your R & C however you want, and still maintain fairly low output impedance for a large time constant, without having to use a massive capacitor value.
Pins 22 & 4 seem to allow selecting an additional capacitor to put in parallel, to increase the time constant more (allow lower-frequency signals).

Separately, up above, there's an Envelope Detector consisting of C2, D4, D3, and C1.  This works like the charge pump circuits used for generating double or negative-voltage power supplies, but here is used on a signal instead; C1 is charged up to (roughly) the peak-to-peak amplitude of the input signal from U2A, minus two diode forward voltages.

This envelope amplitude is filtered by a "fast rise / slow decay" filter (R3, R2, D2, C7), and compared against a fixed threshold by U3.  Strangely, the LM101 op-amp is used as a comparator here - I don't know why, when perfectly good dedicated comparators are available, and they even go as far as adding an external compensation capacitor.  I triple-checked the connections to make sure I didn't have the two inputs reversed, but no.

There's also a strange little peak detector circuit (R4, C3, etc.) which feeds the envelope signal through its own RC time constant, with a diode that may lead to an external peak-detector capacitor.  A control signal can turn on a JFET that discharges/resets this external peak-detector cap.

The part I really cannot figure out is the section at the bottom-right, marked as ??.  The signal which has already had its DC component removed by U1A is for some reason fed through another series cap (C9), and into a strange circuit which again uses an op-amp (U2B) as a comparator.  R10 & R11 add a small positive offset to In-, while In+ sees the input signal with a floating voltage added to it.  This floating voltage addition is created by tantalum capacitor C8 (the orange one in the internal photo above).

First of all, comparing an input signal against itself plus a variable offset seems strange, as that feels like the input signal itself is irrelevant.  How does C8's voltage get changed?

• Pin 7 & Q2 can discharge C8, to reset it to ~0V
• When Q3 is on (envelope detector is below threshold), C8 is slowly discharged through R14
• When Q3 is off (envelope detector is above threshold), C8 is quickly charged through R13 & D8

This feels kind of like a timing ramp, based on the detected envelope of a reflected radar or optical pulse, but done in a primitive way with very slow-reacting (µs-scale) parts - so definitely not meant for anything high-speed.  I also don't understand where the current is supposed to flow when C8 is charging through R13 & D8: there's no DC path (except to Vcc) on the negative side of C8, so this current would just charge C9's voltage higher and higher.

There's also some kind of diode-bridge possible limiter circuit up in the top-left corner.  It's completely unconnected to the rest of the circuit, except for the power rails.  The limiter action comes from the fact that output current sourcing & sinking happens only through R22 & R21, not from the input signal directly.  So by putting a load resistance to gnd on the output (let's suppose that's what the 40Ω R20 is for), the voltage dividers formed by R22/R20 & R21/R20 would set the maximum positive and negative voltages that it can output.  At higher or lower input voltages, the input diodes then simply turn off.

Anyways, to sum up, I have no idea what this is doing, beyond some kind of signal detection.  Let me know if you have any ideas.  There's one more TRT hybrid to go, so hopefully that one will have a more obvious function once I trace its circuitry.

[D Straney]

Ok, turns out I missed something important in that mystery circuit: there was actually a hidden ground connection on one side of C9.  So now it makes a lot more sense:

The Active DC Removal circuit with the U1A integrator is its own independent circuit section, that doesn't interact with the rest of the circuitry directly.

The former-mystery circuit is now shown to be a Timer.  U2B compares C8's voltage against a fixed reference (created by R10 & R11).  C8 charges when the envelope detector sees a signal above the threshold, and Q3 is off.  C8 discharges slowly (maybe barely at all?) when the envelope detector doesn't see a sufficiently large signal.  C8 is reset when an external pulse on pin 7 turns on Q2 and discharges C8 completely.

Overall, the output of U2B (pin 6) seems to go high when an input signal has been present (to the envelope detector) for a certain amount of time, and C8 is allowed to charge past the R10/R11 threshold.

[RoGeorge]

Wow, nice pics! 
Thank you.  Subscribed.

I find the accompanying schematics very interesting, made me want to experiment with certain ideas seen there. 

[timeandfrequency]

'VOIE CONTR' probably means 'VOIE de CONTRôle'
in english : control path, control circuit, control side-chain

[RoGeorge]

Sampling bridge
This is a standard 4-diode sampling bridge: I can't find any references that explain their basic operation well, but the idea is that you forward-bias all the diodes (with a current source) to turn them all on.

Some explanations are in the Tektronix' concepts series https://www.davmar.org/concepts.html at page 66 of 254 here:  https://www.davmar.org/TE/TekConcepts/TekSamplingCircuits.pdf not sure if that is well enough.

Another way at looking at it might be from the perspective of translinear circuits, as in this video at minute 13:20

Bipolar Translinear Circuits, lecture by Barrie Gilbert
Computer History Museum

Thought it was interesting that they advertised the 5 ps jitter in the sample window timing, but the slow settling time and long sampling window needed make that less impressive in practice than it sounds - unless you're going for serious precision on a slower signal, like if building a precision multi-Mhz LVDT for some reason.

My guess is the 5ps spec was useful in case somebody wants to make a sampling head, or a sampling oscilloscope like in the pdf above, where the ADC is much slower than the input signal, yet it is still possible to observe the much faster input signal because the signal is repetitive, and at each trigger only one sample is taken, but each time the sample is taken slightly later relative to the trigger moment.

[D Straney]

Some explanations are in the Tektronix' concepts series https://www.davmar.org/concepts.html at page 66 of 254 here:  https://www.davmar.org/TE/TekConcepts/TekSamplingCircuits.pdf not sure if that is well enough.

Perfect, thanks, added it to the post: didn't want to derail the circuit explanation by having to describe sampling bridge operation from scratch (badly) by myself.

My guess is the 5ps spec was useful in case somebody wants to make a sampling head, or a sampling oscilloscope like in the pdf above, where the ADC is much slower than the input signal, yet it is still possible to observe the much faster input signal because the signal is repetitive, and at each trigger only one sample is taken, but each time the sample is taken slightly later relative to the trigger moment.

That's what I would've thought for a mismatch in small-signal bandwidth & jitter, but the sampling window seems weirdly long for that, given the high small-signal bandwidth & low jitter.  With the 14 ns sampling window needed for 0.1% settling, the jitter is 1/3000th of the sampling window time - good for precision but also unnecessary because the errors from harmonic distortion, switching transient, imperfect feedthrough rejection, etc. are all much larger than that.  I'm guessing they didn't design it specifically for low jitter as the "limiting factor", but it just ended up being much lower than needed (and therefore good as a marketing point)

[D Straney]

Ok, here's the final TRT hybrid I have:
TRT 3511.181.28681

It has "G.D.S." on the lid (don't know what that stands for) and dates from 1994.

It's not that different from the previous 3511...28601 inside in general:



There's a dual JFET-input op-amp that isn't marked, but looks similar to the Zeptobars photo of the ST TL072:

Like the previous TRT hybrid, it also has an LM101 op-amp:


Let's look at the schematic I traced out:


The top section, the non-inverting gain stage, is pretty straightforward.  There's one of the JFET-input op-amps set up for non-inverting gain (set by R2 & R3), referred to a negative offset voltage created by R4 & R5.  A series resistor on the output, and a separate transistor which can selectively shunt the output signal to ground, implements some sort of "output blanking".

The bottom section starts off with an integrator based on U2, which integrates a signal coming in on pin 21.  It seems somewhat flexible; shorting pins 23 & 24 together adds an extra capacitor in parallel (slowing down the response), and there's a pin directly to the virtual ground (pin 22) that could be used for a different-value input resistor.

Anyways, the integrator is apparently only supposed to work with positive outputs: D1 across the feedback path ensures that the output can't go more than ~0.7V negative.  (If it "tries" to, then D1 turns on and turns U2 into a buffer with a grounded input)  So, the input could be positive or negative, but the integrator's output can only go positive.  C5 is a compensation capacitor which adds a Miller capacitance across the LM101's internal gain stage (see the LM101 datasheet for an internal schematic and details), but there's also C4 - by connecting the inverting input to the output of the internal differential-to-single-ended converter, this seems to actually add some positive feedback, if I'm interpreting the internal schematic correctly.

After the integrator is a comparator, using the 2nd half of the JFET-input op-amp: this sums a reference voltage with the integrator output, and compares the result with 0V.  The reference voltage is not at all precise; it's created with a zener diode from Vcc, and a much larger resistor from negative supply Vee.  I think the only way this makes sense is that when the integrator's output is 0V, U1B's input is biased negative.

What I think happens here, is that the input signal gets integrated, and when the integrated input is large enough (positive), the comparator's output goes high.  This allows JFETs Q1 & Q2 to turn on, and short the integrating capacitor, therefore resetting the integrator.  This drops the integrator's output back to 0V and so the comparator's output goes low again, and the process restarts.  The brief time during which U1B's output goes high creates an output pulse in two different formats:
The pulse output circuitry level-shifts the Vee-to-Vcc bipolar U1B up to ~0V to 2*Vcc.
The open-collector output pulses Q3 on.

This lower part of the schematic, then, seems like a voltage-to-frequency converter.  A larger (more negative) input voltage means that the integrator's output reaches the comparator threshold faster, to generate a pulse and reset the integrator, therefore creating a shorter period & higher frequency.  There's yet another auxiliary output, between D2 & Q5, which activates a (presumably negative) open-collector output to pull it up to 0V, when the integrator output is below 0V (D2 somewhat cancels the Vbe of Q5).  This feels like maybe some sort of anti-latchup feature or "wrong input polarity" output, but not sure.

Let me know if you have any circuit insights.

[D Straney]

Speaking of voltage-to-frequency (V-F) conversion, here's the...
Teledyne/Philbrick 4735 Voltage-to-Frequency Converter
The TRT V-F circuit was perfectly fine for its purpose (whatever that was), but was a rough implementation with lots of sources of error: the time required to discharge the integrator cap, the finite on-state resistance of the JFETs giving an imperfect reset, the large delays of op-amps used as comparators, the reference voltage derived from the imprecise supply voltage, etc.  Let's explore the other end, instead, of high-precision V-F converters.  The datasheet for this part lists some impressive specs: a 126 dB dynamic range (±10 µV to ±10V input), <50 ppm/K temperature sensitivity, and 50 ppm non-linearity (relative to full-scale)...up to 1 Mhz.


There's enough traces running underneath each other and underneath the ceramic resistor-network sub-subtrate where I can't follow them visually, that tracing the circuit here would be a sanity-stretching exercise.  Instead, I want to talk about the general theory of operation and the principles behind similar precision V-F converters.

First, some more photos of the inside, though:





If you look closely, you can see that the silicon dies consist of a lot of discrete diodes and transistors, plus 3 ICs.  These ICs are an LM101 op-amp:

...a PMI OP-02 op-amp:

...and a 54C04 hex logic inverter (the military-grade, CMOS version of the 7404):


The presence of these "general-purpose building block" ICs doesn't tell us anything about how it works, so first stop is the datasheet:

The 4731/4733/4735 V-to-F is a free running (astable) voltage controlled multivibrator.  See Figure 4.  The effective currents from the four inputs (A, B, C, & D) are summed at the minus input of op amp A1.  A1 and transistor Q1 form a precision current pump, producing current I from the collector of Q1, which is a linear function of the A1 input currents.  Current I charges capacitor C at a rate which is a precise linear function of the V-to-F's input signal.

When the voltage impressed on C (due to I) reaches a fixed precision threshold, the Schmitt-Trigger output changes state and triggers the one-shot (monostable) multivibrator, which in turn produces a constant width output pulse.  This pulse performs two functions.  Amplified by Q2, it is the output of the V-to-F and functionally activates the Precision Charge Dispenser (PCD).  The PCD discharges C to the same "zero" level every time an output pulse is produced.  Thus, capacitor C is repeatedly charged between two precise voltages at a rate which is a linear function of the V-to-F input signal, producing the waveforms shown in the timing diagram, Figure 7.  That is, the rate of charging C, (the repetition rate of charging C and thus the output frequency) are functions of the V-to-F voltage and/or current inputs.

So you can see that the overall principles aren't actually too different than the comparatively-rough V-F in the TRT hybrid before.  Convert input voltage to a current, use that current to charge a capacitor, and then somehow reset that capacitor when its voltage reaches a threshold.  The difficult parts are in how these steps are performed though.  It doesn't say anything about how the PCD (Precision Charge Dispenser) works, as that's most of the Special Sauce(tm) right there.  For comparison, though, let's look at some Bob Pease notes on V-Fs.

LM131
Here's a schematic from National Semiconductor (now Texas Instruments) application note AN-D, showing the internal workings of the LM131 V-F IC:

Rather than trying to reset the capacitor each cycle to a fixed voltage level, instead it removes a fixed amount of charge each cycle, which as the application note explains:

Generally speaking, the circuit is a feedback loop that keeps this capacitor charged to a voltage very slightly higher than the input voltage, VIN. If VIN is high, CL discharges relatively quickly through RL, and the circuit generates a high frequency. If VIN is low, CL discharges slowly, and the converter puts out a low frequency.

Philbrick 4701
One of the difficulties of this approach is the method of removing (adding?) charge to the timing capacitor, with a precision current source gated by a precision timer.  Because the total charge removed is current * time, imprecisions in either the current source or the one-shot timer will feed into the output, and if you're trying to achieve a very temperature-stable V-F, this adds a lot of sources of drift to worry about.  (I believe these were popular for telemetry, for industrial processes and aerospace stuff, so you can imagine the environmental requirements of both of those)  In one of his columns, "What's all this V-F converter stuff, anyhow? (Part II)", Bob Pease describes the circuit he came up with for the Philbrick 4701 V-F.

There's a lot happening there, but the key part to know is that the "precision charge dispensing" here is done by clamping the comparator's output voltage to a precise level, and then feeding back the pulse output to the timing capacitor via another capacitor.  If you put two capacitors in series and place a voltage across them, the new charge that ends up in the "bottom" capacitor only depends on the capacitance ratio and the voltage, independent of time (as long as there's enough time for everything to settle).  So, there's no precision timing to be done here - as long as the feedback capacitor value is stable, and the output voltage clamp is stable, then the charge added to the timing capacitor at every output pulse will be stable.

The bipolar output voltage clamping is done by a diode bridge (D4-7) with a zener (D10) in the middle; the forward voltages of the diodes are cancelled elsewhere by D1 & D2 (D3 & Q1 provide a "virtual ground" at Vf(D1)+Vf(D2) to bias one side of C2).  The feedback capacitor is C2, and it's "one of the best capacitors in the house" according to the article.  There's some temperature coefficient cancellation going on, where C2's tempco gets cancelled by the difference between D4-7 and D1-2's tempcos (they're run at different currents), but that's a whole separate subject.


There's more examples to point to by Jim Williams and Stephen Woodward, but hopefully you get the idea at this point: current input feeds a capacitor connected to a comparator, with a charge pump wrapped around it.  Hope this was interesting.

[schmitt trigger]

Post #8 has some beautiful photos.
What camera setup did you use?

[D Straney]

Thanks!  The one with the resistor arrays? (https://www.eevblog.com/forum/projects/de-capping-circuit-analysis-of-hybrid-modules/msg5785853/#msg5785853)  Can definitely see a jump in the microscope image quality in this thread   Last month I found out there's a very old but very nice metallurgical microscope in the basement of the lab where I study - had to replace the eyepieces, get a new xenon bulb, and clean the objective lenses, but that's what I've been using for the high-quality microscope shots.  It's an Olympus BX51M, which includes a nice bright coaxial light source, hence the good illumination - for the camera I've been using a 2MP Celestron camera (got for free from another lab shutting down) that basically replaces an eyepiece.

[D Straney]

For something very different, let's look at an all-digital part:
LMT.RP H442 clock divider
I don't know where this came from; I got it in the same batch as the TRT modules above.


You can already see a distinct lack of passives, which hints at it being full of digital logic.

The 4 dies in the middle are all 74LS107 dual J-K flip-flops.  The "107A" is written on the metal layer, while there's "73A" written in the silicon doping, which makes me suspect that the 74LS73 (also a dual J-K flip-flop) uses the same design except for a different metal layer.  The pinout of these parts is not symmetric, and you can see that the layout reflects that: things look symmetric around the horizontal center-line, but as you get further outwards towards the top and bottom, the symmetry disappears quickly.


There's a single 74S74 dual D-type flop-flop in the bottom-left corner:


The remaining 2 smaller dies are 74LS00 quad NAND gates.  These end up being severely under-used; only 1 gate is used from one die, and 2 from the other die.  I like how compact the layout is here, to the point that they put the part number markings in between the bond pads.


The internal connections were easy to trace...but making sense of it was much harder!  Here's the schematic:


Divide-by-2: produces Clk1
It starts pretty simple at the top: a clock enters, gets inverted (presumably for phase purposes?) and divided by 2, by the 74S74.  Not much to see here.  This divided-by-2 clock is then used in the middle section.

Divide-by-5: produces Clk3
Let's skip to the bottom section, because that's the next-simplest.  This section takes its clock from the middle section that we skipped.  The way that J-K flip-flops work is that on each clock cycle, complementary J & K inputs force it to a specific state (J=1, K=0 → 1, J=0, K=1 → 0), while both inputs low makes no changes to the state, and both inputs high toggles the state.  So the connections between U1A→U2B, and U2B→U1B, where the previous flip-flop's Q & !Q are connected to the next flip-flop's J & K, essentially copy the previous flip-flop's state.  The connection of U1B→U1A is a little weirder because it uses U1A's asynchronous reset to force U1A low as soon as U1B's output goes high.  If I'm interpreting correctly, this creates a divide-by-5 effect, looking at the states after each clock falling edge:


Divide-by-N/N+1
Saving the most complicated for last, take a look at the middle section.  How this behaves is controlled by an external input, pin 14.

When pin 14 is low, everything's reasonably simple: U6A's output is always high, so U6D's output is always low, and U3B never gets to toggle (J & K are always low).  If we start from an all-zeros state, U3B is continuously forced low through its async reset by U3A's output being low, so this holds U4A & U4B low through their reset pins, so U3A never gets a chance to go high and "break the loop" here.  This means that all that happens is U2A has both J & K held high (due to being connected to U3A's !Q), so U2A just sits there happily toggling its output, producing a divide-by-2 output on Clk2 to feed the bottom section (the divide-by-5).

When pin 14 goes high, though, things get weird.  Mapping out the states makes it much easier to understand what's happening:

Now, U3B is allowed to toggle sometimes because its J & K inputs are high whenever Clk3 (the divide-by-5 output) is high.  But Clk3 is a divided-by-5 version of Clk2!  So what happens here, is that it goes back and forth between states 1 & 2 for 10x Clk2 cycles (5x Clk3 cycles).  When Clk3 goes through a full cycle, it produces a falling edge on U3B's clock pin, which toggles U3B to a "high" state.  Now, U4A & U4B are no longer being forced low by U3B.  This allows it to progress through states #3-5, which produce 1x Clk2 pulse over 3 states.  After this last state, it ends up at all-zeros again, and so the whole cycle restarts.

The effect this has, is that when pin 14 is high, the middle section produces 6 output cycles (on Clk3) over 13 input cycles (on Clk2): the 10 cycles to wait for a Clk3 falling edge, plus 3 extra cycles for states #3-5.  Therefore, pin 14 switches the division ratio of this middle section between 2 and 13/6.

Purpose
When you look at the number "2" as 12/6, then the middle section makes more sense: it can either divide by 12/6, or 13/6.  This very much puts me in mind of a fractional-N frequency synthesizer's divide-by-N/divide-by-N+1 switching, just like in the SINCGARS military radio's frequency synthesizer I looked at before.  The overall division ratio is switchable between 2*12/6*5 = 20, or 2*13/6*5 = 21+2/3.

I believe this module was used in a frequency synthesizer, either for a radio, or some other kind of RF equipment (jamming, surveillance, etc.).  It was made in 1997 according to the date code on top, and I'm pretty sure there were commercial self-contained frequency synthesizers at a much higher level of integration by then - but judging by the fact that it was constructed as a hermetic hybrid, it's (1) probably some kind of aerospace or military application, and (2) may have been designed significantly earlier than that: see point #1 again.  Considering the maximum frequency of "74LS" logic, this can't have been dealing with any particularly high frequencies, probably 10 Mhz at most.

Anyways, there you have it, that's how to make your fractional-N-synthesizer's frequency divider out of discrete logic.  Given how much convoluted logic is involved with these flip-flop states, I can only imagine the poor engineer who had to twist their brain into knots to come up with this.

[timeandfrequency]

For something very different, let's look at an all-digital part:
LMT.RP H442 clock divider
I don't know where this came from; I got it in the same batch as the TRT modules above.

Perhaps a clue here.
Headquaters in Boulogne-Billancourt (departement 92, Hauts-de-Seine), France
This module might have been used in a PABX.

'.RP' : That's a bit surprising. At first sight, I'd thing about the name or acronym of a subsidiary or internal division.
But 'RP' is also a today much used acronym which means 'Région Parisienne' = Paris + its suburb.
Maybe it's just a coincidence.