Divide by 10 cct needed

[Gertjan]

Hi folks , I have a marconi 2995a coms test set , It has a bnc port for a 1 Mhz freq ref input , I also have a 10Mhz gpsdo , i need to divide the gpsdo 10 Mhz outut  down to 1 Mhz to feed the 1Mhz ref freq input on the marconi , Can anyone recomend a schematic of something i can homebrew for this?.

tl;dr
my solution is a piece of wire + switch
since that analyzer is anyway running at internal 10MHz

ext_ref_Marconi_2955.png

Yes, I think there is a much simpler solution. With a negative parts count (minus one)

The schematic is not very clear. But I think the external 1MHz is fed into a PLL, which synchronises the internal 10MHz oscillator.
The 1MHz input is divided by 10, the internal 10MHz is divided by 100 into the PLL.

So skip one divide by 10 stage (74LS390), so both ext input and oscillator will be divided by 10, and the Ext 1Mhz input has become an Ext 10Mhz input. .

OK, only half a part is saved, we still need the other half 74LS390.....

Alternatively, one could add a half 74LS390 (divide by 10) in the 1MHz path, so both are divided by 100. Less elegant, but might be easier on the PLL. Result is the same: the 1MHz input becomes a 10MHz Ext Ref input.

regards, Gertjan.

[G0HZU]

If I understand that correctly I think the loop filter components would have to also be changed to suit the factor of 10 change in division ration in the OCXO part of the loop.

When the thread started I assumed the solution would be something like a simple squarer circuit (in case the GPSDO output is a sine wave at 50R) followed by a '390 based divide by 5 plus divide by 2 to get the divide by 10 overall. The Marconi 2955 isn't exactly high end test gear, from a technical point of view it's barely mid range so I don't think this external divide by 10 needs to have state of the art performance levels. The divider noise floor of its internal LS390 chips will probably dictate the close in phase noise of the internal OCXO when it is disciplined externally via its internal PLL circuit.

[Gertjan]

If I understand that correctly I think the loop filter components would have to also be changed to suit the factor of 10 change in division ration in the OCXO part of the loop.
....

I don't think the loop filter would need adaption.

Avoiding that discussion, when choosing the solution to add an extra divide by 10 divider to the 1MHz input, nothing changes for the PLL.

regards, Gertjan.

[ME]

I think folks missunderstand what i want to do , my 2995A coms tester has a bnc input for a 1 Mhz clock , my gpsdo has a 10Mhz output , I want to turn the gpsdo 10Mhz signal into a 1 Mhz signal to feed into the marconi 2955A's 1 Mhz bnc port.

[Gertjan]

I think folks missunderstand what i want to do , my 2995A coms tester has a bnc input for a 1 Mhz clock , my gpsdo has a 10Mhz output , I want to turn the gpsdo 10Mhz signal into a 1 Mhz signal to feed into the marconi 2955A's 1 Mhz bnc port.

Hi ME,

Yes, understood.
But consider the alternative. With less effort you can adapt your 2995A to have a 10MHz input for ext ref.
10MHz is the modern universal standard reference frequency...

regards, Gertjan.

[brucehoult]

I think folks missunderstand what i want to do , my 2995A coms tester has a bnc input for a 1 Mhz clock , my gpsdo has a 10Mhz output , I want to turn the gpsdo 10Mhz signal into a 1 Mhz signal to feed into the marconi 2955A's 1 Mhz bnc port.

Everyone understood that just fine.

What we perhaps don't know is which properties of the 1 MHz signal might be important. Presumably drift-free, which rules out only the person who suggested a 1 MHz crystal. Does it need 50:50 duty cycle? Does it need low latency of the edges relative to the corresponding edge of the 10 MHz signal? Does it need no jitter or is, say, ±10ns worst case on the 500ns edges ok?

[Gyro]

There is no lack of understanding.

You have been presented with several solutions. It is for you to decide which one is appropriate for you. If you go for a simple external divider, the necessary information is in the 74LS90 or 7HC390 datasheets they just need a supply and decoupling capacitor and maybe series terminator resistors. S/W and microcontroller solutions have also been presented, together with internal modification (10MHz input) solutions.

External divider solutions (jellybean or S/W) will of course require a 5v supply. Internal modifications are ether already powered or have a logic supply available.

Your choice.

[Solder_Junkie]

80 replies to a pretty basic question, I have had test equipment that needed 1 MHz input, my current counter is happy to have 1, 5 or 10 MHz and it "sorts itself out", my signal generator is configurable as to external ref input.

I used to have a 2955 at work, what a heavy heap of junk it was too. The symmetry of the square wave reference input is not important, so if it's not 50:50 mark to space, it doesn't matter.

My rubidium standard has a home made divide by 10 board, basic TTL logic, one of my home made GPSDO units has a divide by 10 board too. It's not rocket science, a 74HC390 will do the job, input pin 4, link pins 1 and 7, output from pin 3.

[Gyro]

Don't forget to terminate the inputs (12 and 15) of the other divider of the '390. Don't leave them floating. [Edit:and tie the reset input low].

[Picuino]

How do you make 50-ohm terminations?
With a 50-ohm resistor in series with a small capacitor?

[Solder_Junkie]

Use a 74HC04 with sections in parallel. This circuit shows how to buffer the output.
https://www.qsl.net/g4aon/pdfs/GPSDO_as_built.pdf

[zapta]

CD74HC190 from TI will do the job. Apart from a decoupling cap, nothing else is needed.

Will it output 50% duty cycle?

[floobydust]

From the Marconi 2955 schematic above, the EXT 1MHz input is AC-coupled to a two transistor pre-amp, then to a 'LS90 I think configured as a "Symmetrical Bi-quinary Divide-By-Ten Counter". So I believe it corrects the duty cycle.
The 10MHz reference osc is div/100 for the PLL using two stages of 'LS390 forming the VCO control voltage. The PLL is 100 kHz.

[ME]

Quote: Hi ME,

Yes, understood.
But consider the alternative. With less effort you can adapt your 2995A to have a 10MHz input for ext ref.
10MHz is the modern universal standard reference frequency...

regards, Gertjan.
Can you explaine how i can do this then please?.

[Andy Chee]

Can you explaine how i can do this then please?.

The details are in reply #31 of this current thread

[Uunoctium]

As posted before, you can either bypass the complete internal PLL and feed the communication test set direct with 10MHz, since it runs internally already with 10MHz.
Or you insert an additional 1:10 divider behind the 1st 74390. 7490 works also sufficient with 10MHz - Yaesu did that with their Ham-frequency counter YC500 40yrs ago. (p 11 in SM shows the optional 10MHz TCXO, which is divided by 10 to meet Counters internal reference of 1Mhz. Birds view for simple wiring included  )

[G0HZU]

Well there have been lots of methods suggested...

IMO the method in post #31 using just a switch has some downsides:

If the external GPSDO gets turned off or disconnected then the 2955 will have no reference when set to external mode.
If the external GPSDO has worse phase noise (including spurious terms) than the internal OCXO then this may impact the noise performance of the 2955. This might or might not matter to the OP.

Doing it with an external /10 as originally requested is a low risk way to do it but it does mean making something to go in a suitable box and it will also need a DC supply voltage from somewhere. So this is far from a perfect solution.

The second method suggested by Gertjan where an additional \10 is added internally might be the most suitable as long as you don't ever expect to have any other test gear that also requires an external 1 MHz (or 2 MHz or 5 MHz) reference. In this case an external box with the ability to configure for multiple 1 MHz or 2 MHz or 5 MHz outputs might be worth making.

If it helps, I think the internal 10 MHz OCXO may be similar to the one used in a Marconi 2018/19 signal generator. These OCXOs are usually housed in a grey plastic box about the size of a matchbox. I've got some of these here and the close in phase noise of the 10 MHz OCXO is fairly good and is typically something like:

-112 dBc/Hz at 10 Hz offset
-130 dBc/Hz at 100 Hz offset
-145 dBc/Hz at 1 kHz offset
-150 dBc/Hz at 5 kHz offset

Some GPSDO 10 MHz outputs will be cleaner than this and some won't. However, if you stick with the original external divide by 10 or with Gertjan's second method with the \10 fitted internally, it won't matter much if the external GPSDO phase noise is a bit worse than the internal OCXO. This is because it is used to discipline the internal OCXO.

The other option is the 'do nothing' option and simply use the GPSDO to calibrate/adjust the internal OCXO once or twice a year and always run the 2955 from its internal OCXO.

[Zoli]

Divider by 50 with attiny4/5/9/10; at the moment the price of the micros on Digikey is ~$0.44CAD - competing with the logic circuits.
Setting the proper division ratio(between 2 and 256) is the user's job.
And sorry for the poor coding skills.

Code: [Select]

;Divider by 50 for attiny4/5/9/10 © 2021 Zoltan Soos, GPL3
;Schematics: 5V power supply, PB0 PWM output, PB1 external clock input, PB2&3 NC
;
;Timer count to 49(0x31), output compare at 24(0x18), direct clock(external) source
;
;ADC and AC disabled(PRR=(1<<PRADC); ACSR=(1<<ACD))
;
;Timer/Counter 0 output compare A is used for the divided signal
;
;Fast PWM mode 14(WGM0[3:0]==0b1110)
;
;ICR0H=0x00, ICR0L=0x31(TOP)
;
;OCR0AH=0x00, OCR0AL=0x18(compare match)
;
;
.include "tn10def.inc"
;Register definitions
.def TEMP =r16 ; Scratchpad 1
.def TEMP_1 =r17 ; Scratchpad 2
;End register definitions

.CSEG

.org 0
; Turn off analog comparator
ldi TEMP, (1<<ACD) ;
out ACSR, TEMP ;
; Turn off ADC
ldi TEMP,(1<<PRADC) ;
out PRR, TEMP ;
; Setup I/O Port
ldi TEMP, (1<<DDB0) ; PB0 is Output, the rest Input
out DDRB, TEMP ;
ldi TEMP, (1<<PUEB2|1<<PUEB3) ;
out PUEB, TEMP        ; Pull up PB2-3
; Setup timer
ldi TEMP, (1<<COM0A1|1<<WGM01) ;
out TCCR0A,TEMP ; Set up the timer mode
ldi TEMP, (1<<CS00|1<<WGM02|1<<WGM03) ;
out TCCR0B, TEMP ; and clock source
ldi TEMP, 0x31 ; Setting up the division factor
clr TEMP_1 ;
out ICR0H, TEMP_1 ;
out ICR0L, TEMP ;
ldi TEMP, 0x18 ; And the switching point
out OCR0AH, TEMP_1 ;
out OCR0AL, TEMP ;
ldi TEMP, (1<<SE) ; Setup idle mode
out SMCR, TEMP ;
ldi TEMP, 0xD8 ; Unprotect CLKPSR and CLKMSR reg
clr TEMP_1 ; Divide by 1
out CCP, TEMP ;
out CLKPSR, TEMP_1 ;
ldi TEMP_1, (1<<CLKMS1) ; Switch to external clock
out CCP, TEMP ;
out CLKMSR, TEMP_1 ;
main:
sleep ;
rjmp main ;



[vk6zgo]

This is a silly debate.

Whether to go down the MCU route, or specialised IC, depends on, what one has available and whether it's just a one-off or a large production run. If it's one off, just use what's on hand, but if it's a large production run, go for the specialised IC of course. Also note that software is not free. It has costs associated with it: debugging, revision control, code reviews etc.

It’s always the same story.
There are two technologies available, each with its own advantages and disadvantages. Therefore, one technology will make more sense to some people from their perspective, while another technology will make more sense to others from their perspective. Arguing over who is right—each from their own particular perspective—is quite self-centered.
The debate itself is a good thing. Presenting all points of view enriches everyone’s understanding. But presenting my point of view as the only valid one is like going through life with blinders on.

The most productive approach is to say: “I have this perspective, and from that perspective, this is better for such-and-such a reason and worse for such-and-such another reason.”

I've learned a few things from this discussion that I hadn't considered before. Please don't ruin it by trying to prove yourselves right.

In your linked pic, they are both wrong----it is a lower case "g".

[SCSKITS]

Did you ever resolve this?
The thread is getting pretty long for a basic divide by 10 circuit.

[floobydust]

Mr. Spock had it figured out

[tom66]

This thread has left me pondering on how many transistors it takes to do a simple low jitter divide of 10MHz. The extremes are, well, extreme.

You're not trying unless you're using a quad-core 64-bit Cortex-A53, which can run as many as four low-jitter dividers in parallel for as little as 2W of power consumption and 1 billion transistors.

[David Hess]

This thread has left me pondering on how many transistors it takes to do a simple low jitter divide of 10MHz. The extremes are, well, extreme.

It takes one transistor, and jitter is practically as good as a crystal oscillator - injection lock a 1 MHz crystal oscillator from the 10 MHz signal, easy-peasy. (1)  An LC or Wein bridge oscillator will work also.

(1) Which is to say this is not easy at all, but it is possible.  It would be easier with 2 separate transistor oscillators for divide-by-5 and divide-by-2 stages.

[ME]

Well two of these  have been delivered:74HC390 Dual Decade Ripple Counter Logic IC  , Can someone post a /10 schematic i can build to get a 1 Mhz output from a 10 Mhz input from a B3SAP gpsdo?

[SteveThackery]

Well two of these  have been delivered:74HC390 Dual Decade Ripple Counter Logic IC  , Can someone post a /10 schematic i can build to get a 1 Mhz output from a 10 Mhz input from a B3SAP gpsdo?

You've done it again! How about you actually make the effort yourself? This is not a place where you get someone else's work for free. Advice is free, but nobody will do the actual work for you.

Also, research involves a lot more than just asking a question on a forum, and waiting for a complete solution to be delivered back. What else have you done to educate yourself? Online books or training? Educational videos? AI-assisted deep searches? Searched out similar projects?

You've had an enormous amount of advice from the members of this forum, because they like helping people. But now it's your turn. Read the whole thread carefully; make notes; identify at a high level the possible approaches; sort the replies under those headings; fill out the details; identify areas where you need to do a bit more research.

Have you actually built anything yet? No? Why not?

Build something! Try to make it work. Try to understand why it doesn't. If you can show you've made a decent effort, the forum members will guide you further.

But right now, it's over to you. The ball is entirely in your court.