Feedback optimisation

[nihial]

Hi,

I'm currently playing with a LLC converter and I'm trying to optimize the feedback. I'd be happy to hear some insight on how I could improve the response.






The feedback circuit is the following :



The response I get for a 5mA load is the following (yellow output, magenta feedback output, blue switching node):


This case is a low load situation, I'd like to improve the ripple in this situation but I'm not sure what methodology I should use, what I should look for etc.

[TimNJ]

What controller are you using?

It looks like it is in burst mode, hence the long periods of no switching activity. This is to reduce MOSFET switching losses and losses related to the magnetizing current in the transformer. The converter is not really behaving as a linear control system in this case, because burst-mode is more or less an unstable (hysteretic?) control mode. Apart from how the control loop will respond to changes in load while in burst mode, modifying the feedback loop compensation will probably not do a whole lot.

Are there any controller options to increase the burst repetition rate while in burst mode?

[David Hess]

I'm currently playing with a LLC converter and I'm trying to optimize the feedback. I'd be happy to hear some insight on how I could improve the response.

Shouldn't C5, C6, and R13 be configured to generate phase lead instead of phase lag to better tailor the frequency compensation?  This would place them across R2 and R3 instead of R4.

[nihial]

What controller are you using?

It looks like it is in burst mode, hence the long periods of no switching activity. This is to reduce MOSFET switching losses and losses related to the magnetizing current in the transformer. The converter is not really behaving as a linear control system in this case, because burst-mode is more or less an unstable (hysteretic?) control mode. Apart from how the control loop will respond to changes in load while in burst mode, modifying the feedback loop compensation will probably not do a whole lot.

Are there any controller options to increase the burst repetition rate while in burst mode?

ncp1397

I should have mentionned, that if the feedback voltage goes high enough, it will enter skip mode. What I'm seeing is that it should stop bursting quicker when the output voltage get's too high and start back faster when it get's too low.

[mtwieg]

I should have mentionned, that if the feedback voltage goes high enough, it will enter skip mode. What I'm seeing is that it should stop bursting quicker when the output voltage get's too high and start back faster when it get's too low.

According to the NCP1397 datasheet, skip mode is controlled by the voltage at the skip/disable pin, which has a threshold around 660mV and 45mV of hysteresis. Can you check the waveform on the skip pin to confirm this is what's causing the bursting behavior? It's not clear how your opamp circuit interfaces to the NCP1397, a full schematic would be very helpful.

If this ripple is due to the skip mode, then there are a couple ways you might be able to change its amplitude or frequency. Again, need a more complete schematic to help though.

[nihial]

I'm currently playing with a LLC converter and I'm trying to optimize the feedback. I'd be happy to hear some insight on how I could improve the response.

Shouldn't C5, C6, and R13 be configured to generate phase lead instead of phase lag to better tailor the frequency compensation?  This would place them across R2 and R3 instead of R4.

Mmm yes I guess a cap there could improve things. The reason for the current placement was for having the same impedance seen from + and - inputs as per another advice for that configuration where the input signal is connected to the + input.

I hate dimensionning by trial and error and I don't really know if there's another way here. For example a cap accross R2 R3 intuitively should not less pass signal around and beyond the switching frequency but beyond that I'm clueless

[nihial]

I should have mentionned, that if the feedback voltage goes high enough, it will enter skip mode. What I'm seeing is that it should stop bursting quicker when the output voltage get's too high and start back faster when it get's too low.

According to the NCP1397 datasheet, skip mode is controlled by the voltage at the skip/disable pin, which has a threshold around 660mV and 45mV of hysteresis. Can you check the waveform on the skip pin to confirm this is what's causing the bursting behavior? It's not clear how your opamp circuit interfaces to the NCP1397, a full schematic would be very helpful.

If this ripple is due to the skip mode, then there are a couple ways you might be able to change its amplitude or frequency. Again, need a more complete schematic to help though.

Yes the ripple is because of that. I'd expect the feedback to track better the output voltage than that or at least I'd like to be able to understand the tradeoffs I can do to get a more reactive supply.

I can't post everything but I can complete with the connection of the feedback to the IC :

[David Hess]

I'm currently playing with a LLC converter and I'm trying to optimize the feedback. I'd be happy to hear some insight on how I could improve the response.

Shouldn't C5, C6, and R13 be configured to generate phase lead instead of phase lag to better tailor the frequency compensation?  This would place them across R2 and R3 instead of R4.

Mmm yes I guess a cap there could improve things. The reason for the current placement was for having the same impedance seen from + and - inputs as per another advice for that configuration where the input signal is connected to the + input.

The configuration you show could be a non-inverting integrator, but I do not know why it would be used as an error amplifier.

I hate dimensionning by trial and error and I don't really know if there's another way here. For example a cap accross R2 R3 intuitively should not less pass signal around and beyond the switching frequency but beyond that I'm clueless

I do not have any good references for the different types of frequency compensation, but this Texas Instruments application note gives some idea of what is going on and how to calculate the values:

https://www.ti.com/lit/an/slva662/slva662.pdf?ts=1738931826770&ref_url=https%253A%252F%252Fwww.google.com%252F

I start with a bode plot and work back from there to see what is required and approximate values.  If I did enough of this work regularly, then I would start with the math.

[nihial]

I'm currently playing with a LLC converter and I'm trying to optimize the feedback. I'd be happy to hear some insight on how I could improve the response.

Shouldn't C5, C6, and R13 be configured to generate phase lead instead of phase lag to better tailor the frequency compensation?  This would place them across R2 and R3 instead of R4.

Mmm yes I guess a cap there could improve things. The reason for the current placement was for having the same impedance seen from + and - inputs as per another advice for that configuration where the input signal is connected to the + input.

The configuration you show could be a non-inverting integrator, but I do not know why it would be used as an error amplifier.

I can't use an optocoupler and I know integrating invertors can be used, here the FB logic of the controller doesn't allow it directly.

I hate dimensionning by trial and error and I don't really know if there's another way here. For example a cap accross R2 R3 intuitively should not less pass signal around and beyond the switching frequency but beyond that I'm clueless

I do not have any good references for the different types of frequency compensation, but this Texas Instruments application note gives some idea of what is going on and how to calculate the values:

https://www.ti.com/lit/an/slva662/slva662.pdf?ts=1738931826770&ref_url=https%253A%252F%252Fwww.google.com%252F

I start with a bode plot and work back from there to see what is required and approximate values.  If I did enough of this work regularly, then I would start with the math.

I'll look into it !

[mtwieg]

Yes the ripple is because of that. I'd expect the feedback to track better the output voltage than that or at least I'd like to be able to understand the tradeoffs I can do to get a more reactive supply.

I can't post everything but I can complete with the connection of the feedback to the IC :

Ok, but you should understand that pulse skipping/burst mode is a good and necessary thing. As the load decreases, an LLC typically increases its drive frequency in order to reduce output power. In theory at zero load the converter would have to drive with infinite frequency to maintain regulation, which of course is infeasible. The converter has a minimum load it can regulate, and when the actual load drops below that point it must turn off entirely for a little while. It leads to increased output ripple, but it's preferable to losing regulation entirely.

So what specifically is wrong with the behavior in the first post? The ripple already looks quite low (4Vpp on a ~180V output is low IMO). Or is it generating audible noise that bothers you?

In simple terms, the amplitude of the output ripple in skip mode will be the skip pin hysteresis (45mV) divided by the gain of the feedback chain from Vout to the skip pin at the skip frequency. Though messing with that feedback network risks affecting stability when operating at heavier loads, so must be done carefully. It would be nice if the NCP1397 provided a convenient way to change the skip pin hysteresis...

[youngda9]

Let's see the Bode plot of the loop.  Put .asc file as an attachment so we can help.

[nihial]

Yes the ripple is because of that. I'd expect the feedback to track better the output voltage than that or at least I'd like to be able to understand the tradeoffs I can do to get a more reactive supply.

I can't post everything but I can complete with the connection of the feedback to the IC :

Ok, but you should understand that pulse skipping/burst mode is a good and necessary thing. As the load decreases, an LLC typically increases its drive frequency in order to reduce output power. In theory at zero load the converter would have to drive with infinite frequency to maintain regulation, which of course is infeasible. The converter has a minimum load it can regulate, and when the actual load drops below that point it must turn off entirely for a little while. It leads to increased output ripple, but it's preferable to losing regulation entirely.

So what specifically is wrong with the behavior in the first post? The ripple already looks quite low (4Vpp on a ~180V output is low IMO). Or is it generating audible noise that bothers you?

In simple terms, the amplitude of the output ripple in skip mode will be the skip pin hysteresis (45mV) divided by the gain of the feedback chain from Vout to the skip pin at the skip frequency. Though messing with that feedback network risks affecting stability when operating at heavier loads, so must be done carefully. It would be nice if the NCP1397 provided a convenient way to change the skip pin hysteresis...

Well perhaps this amplitude of ripple in this mode is totally normal, I had a target of something around 1V in mind when I started. So what I gathered is that I can do is try to increase the gain somehow until my output's going crazy with heavier loads and find some kind of middle ground.