Finished Digital Clock Design

[ChrisGreece52]

Hello 5 months ago i finished the circuit diagram for my Digital Clock Project.
I was inspired by Daves own video


I found an Instructables project that only displayed Hours Minutes and Seconds .

So i figured i could go one step further and added Milliseconds and designed the logic circuitry for Days Months and Years the most difficult part was designing the part which counts the leap year.

Linked bellow will be a scan of my circuit.

I also added another divider so i can get 1 Hz frequency to drive some leds usind a mosfet ... the leds will sit between the displays so it looks like a real clock.

So please take a look and comment on my design keeping please in mind that it is my first "big" circuit design.
Also if you need additional information please leave a reply below.
Thank you very much.

[ChrisGreece52]

Any feedback would be awesome guys.

[danadak]

Curious, why was it done in discrete logic vs an embedded controller ?

The latter of course would replace much of the logic with code that you
can enhance/change to your hearts desire. There are even parts now that
can be programmed in discrete logic using Verilog, so you get the best
of both worlds. referring to Cypress PSOC.


Regards, Dana.

[brumbarchris]

Do you have decoupling caps on the ICs?
The schematic (if that is the only schematic you have) is not showing much in that regards. But then again, it looks more like a combination between a block diagram and a real schematic.

regards,
Cristian

[ChrisGreece52]

Thank you all for your feedback.
I was so pumped after watching Dave's video that i never even considered a microcontroller or a FPGA replacing the discrete logic circuitry.

I would also like to point out that my schematic originally started out as a schematic but i then run out of paper so it became a diagram.
If i were to draw the connections between the BCD drivers and the Displays it would look ugly and probably unreadable so i went with the schematic /circuit diagram hybrid.

As for the decoupling caps i have none because I am not familiar with their placement in the circuit.
I mean i was planning on having a reasonably big cap between Vcc and Gnd but beyond that i have no idea how to couple discrete logic signals.

[bitslice]

That's pretty awesome 

Did you do any mathematical reduction for the counter logic, or just wing it?

I'm really hoping you'll sketch this up in Eagle or something, I bet lots of people would like to follow your lead but automatically assume a pencil drawing is going to contain a few errors or bits they can't decipher.

[Macbeth]

Forget Eagle, sketch it up in something like Altera Quartus (free) - you can wire up 74 series TTL and emulate it and also go ahead and flash it to a CPLD like an EPM240 board you can get from ebay for next to nothing and build your clock from that. It's all of the old school design but without the cost and headache of discrete logic IC's and mountains of wiring.

[tron9000]

Thumbs up from me, that's some painstaking schematic drawing there!

[StillTrying]

I couldn't do anything like this, when I know it could be all done with one 14pin chip, 6 switching transistors, and 180 lines of code, and that would include the 100year/400year leap year thing - just in case.

However I've got loads of old TTL chips that will never be used, I suppose I could glue them all over a board and hide the uP in the middle of them somewhere, who'd ever know. 

[Macbeth]

I'm with you until you say use procedural code and a 14 pin micro.

The point of this exercise is to do it using pure logic. 1980's style.

Which is why it should be done with an FPGA/CPLD (with >100 pins) instead. Then try doing it without the TTL circuit and do it in VHDL/Verilog instead,

But when it comes to purely making a functional clock as the only goal I'm totally with you. Far easier to program a micro than this!

[danadak]

Use a Cypress PSOC, ARM + Logic Fabric (you can program with Verilog or just use
gui logic elements in drag and drop).

+ lots of analog, DSP, Comm, display.......see attachment.


Regards, Dana.

[ZeTeX]

Why hand drawn schematic?

[oldway]

This is old way technology I like 

[Macbeth]

Why hand drawn schematic?

Because he is using DaveCAD? Perhaps without the latest animation plugin, but still good enough.

[ChrisGreece52]

That's pretty awesome 

Did you do any mathematical reduction for the counter logic, or just wing it?

I'm really hoping you'll sketch this up in Eagle or something, I bet lots of people would like to follow your lead but automatically assume a pencil drawing is going to contain a few errors or bits they can't decipher.

I am so sorry for the late answer.
I have not touched a single part of the RTC yet.
Yesterday i added a backup battery so when power goes down the counters will keep running everything was done by hand including the calculations to get 1Khz out.
I will try bringing it into a digital form to be easy to read and to modify.

[ChrisGreece52]

Forget Eagle, sketch it up in something like Altera Quartus (free) - you can wire up 74 series TTL and emulate it and also go ahead and flash it to a CPLD like an EPM240 board you can get from ebay for next to nothing and build your clock from that. It's all of the old school design but without the cost and headache of discrete logic IC's and mountains of wiring.

I will try creating both an Eagle Schematic and one using Altera Quartus after i do some research on it.
Call me a masochist but i loved wiring up chips in the past and i have no problem doing it large scale for this project

[ChrisGreece52]

I couldn't do anything like this, when I know it could be all done with one 14pin chip, 6 switching transistors, and 180 lines of code, and that would include the 100year/400year leap year thing - just in case.

However I've got loads of old TTL chips that will never be used, I suppose I could glue them all over a board and hide the uP in the middle of them somewhere, who'd ever know. 

Hahahahahah i laughed with your comment but ill stick with the logic after i am done with this i will consider your evil plan

[ChrisGreece52]

I'm with you until you say use procedural code and a 14 pin micro.

The point of this exercise is to do it using pure logic. 1980's style.

Which is why it should be done with an FPGA/CPLD (with >100 pins) instead. Then try doing it without the TTL circuit and do it in VHDL/Verilog instead,

But when it comes to purely making a functional clock as the only goal I'm totally with you. Far easier to program a micro than this!

Of course i could use and an FPGA but where would be all the soldering fun and the frustration that comes with it

[ChrisGreece52]

Why hand drawn schematic?

Its easier for me to draw the schematic by hand instead of making it digitally ... i love to write and erase stuff with a pencil.

[rstofer]

i like the old school approach.  I ran across my cut-strip-wrap gun the other day and was wondering if I would ever used it again.  Sure, the project could be done with a uC, CPLD or FPGA but old school is a much better learning opportunity.

Great project!

[EEVblog]

Curious, why was it done in discrete logic vs an embedded controller ?

Because it's way cooler 

[Zero999]

As for the decoupling caps i have none because I am not familiar with their placement in the circuit.
I mean i was planning on having a reasonably big cap between Vcc and Gnd but beyond that i have no idea how to couple discrete logic signals.

Decoupling capacitors are used because quite often the power supply has a high impedance to high frequencies. If the circuit suddenly draws a large current for a short time, the supply voltage will drop, then when the circuit suddenly stops drawing current, the supply voltage will increase, often to much more than the nominal voltage. A capacitor will discharge slightly, when the supply voltage starts to fall, therefore keeping the circuit powered and charge up more, when the supply voltage increases, thus absorbing excess energy.

The general rule of thumb for decoupling is one 100nF capacitor per IC, but if it's low speed then one capacitor across the supply will often suffice and if it's run off a battery with a low impedance and very short leads, you may be able to get away with none.

Capacitors are cheap though, so unless there's a reason not to have decoupling, then just do it.

[Ammar]

Looks like a lot of fun. A good exercise would be implementing the same thing with an FPGA. One of the first projects I did with an FPGA was implement an alarm clock using RTOS. Great learning experience.

[Pjotr]

Nice project! 

Why hand drawn schematic?

Its easier for me to draw the schematic by hand instead of making it digitally ... i love to write and erase stuff with a pencil.

That's not a fault of "digital" software but the clumsy counter intuitive implementation of it. With modern schematic entry software you are more or less enforced to draw a net list directly, not a decent schematic. And it's almost impossible, or at least cumbersome, to "sketch". And sketching is an important part of the process to evolute ideas into real working things.

Funny enough there is a schematic software package that do this almost right. It is 30 years old and did not change much over that time! It was almost right done the first time. It's called DesignWorks. There is still a active site about it: http://designworkssolutions.com/  It was originally written for the Mac, so maybe that's the cause not many EE's know about it. I myself use it still daily as a schematic entry front end for Altium PCB.

[ChrisGreece52]

As for the decoupling caps i have none because I am not familiar with their placement in the circuit.
I mean i was planning on having a reasonably big cap between Vcc and Gnd but beyond that i have no idea how to couple discrete logic signals.

Decoupling capacitors are used because quite often the power supply has a high impedance to high frequencies. If the circuit suddenly draws a large current for a short time, the supply voltage will drop, then when the circuit suddenly stops drawing current, the supply voltage will increase, often to much more than the nominal voltage. A capacitor will discharge slightly, when the supply voltage starts to fall, therefore keeping the circuit powered and charge up more, when the supply voltage increases, thus absorbing excess energy.

The general rule of thumb for decoupling is one 100nF capacitor per IC, but if it's low speed then one capacitor across the supply will often suffice and if it's run off a battery with a low impedance and very short leads, you may be able to get away with none.

Capacitors are cheap though, so unless there's a reason not to have decoupling, then just do it.

Thank you very much i did a bit of research on this and found some pdf files that i read and i get it now the use of a decoupling capacitor.