High Bandwidth Current Injector for Impedance measurements

[Jay_Diddy_B]

Hi,

I recently shared two projects on the Test Equipment section of the forum. Both are for performing measurements on power supplies.

The first one is a PSRR Injector that is used to measure a power supply's ripple rejection ratio.
This project can be found here:

https://www.eevblog.com/forum/testgear/psrr-injector/msg3025318/#msg3025318

I also shared some information on the correct way to use an injection transformer for measuring the closed loop response of a power supply in this thread:

https://www.eevblog.com/forum/testgear/injection-transformers-bode-plots-application/msg3021218/#msg3021218

This is a similar project. It is the construction of a high frequency current injection device that can be used to measure the impedance of capacitor or Power Distribution Networks.

There are commercial products like the PicoTest J2112A that are designed for this application.

This is a DIY solution that doesn't use any exotic parts.

The target specification is 50MHz of bandwidth (-3dB)

LTspice Simulation

Like many of my projects I started with LTspice.

Here is the model:




Circuit description

Q2 is a fixed current source.

Q1,Q2 and Q4 are a current sink that is modulated by the input signal.

Q5 is a transistor operated in common base. This is a speed up trick, reduces the collector base voltage variations on Q1, Q2 and Q4.

The modulated current flows through L1, C2 and R6 to the output. L1 is not a real component but included to represent the wiring inductance between the injector and the device been tested.

There is a monitor port that allows the current to be monitored. The scaling is around 1mV/1mA

Modelling in the Frequency Domain




The LTspice predicts a -3dB bandwidth of 70MHz.

Transient Response



The model is showing rise and fall times of around 10ns

To be continued …

Regards,
Jay_Diddy_B

[Jay_Diddy_B]

Hi,
Here is the real schematic:



Board Design





This is the other side of the board:



To be continued …

Jay_Diddy_B

[Jay_Diddy_B]

Hi,

Here are some pictures of a prototype.





Regards,
Jay_Diddy_B

[Jay_Diddy_B]

Hi,

Testing with an HP3325B

The rise and fall times of the HP3325B are around 10ns.

The Tektronix P6022 current probe has a published BW of 120MHz.

This is what the output of the current injector looks like when been driven by the HP3325A at 5MHz:



The input was 1V p-p the output is 80mA p-p

The HP3325A is not really fast enough to test this circuit.

Testing with HP8112A Pulse Generator


The HP8112A has 5ns rise and fall times.



This shows the current waveform measured with a Tektronix P6022 current probe with the input driven by the HP8112A pulse generator.

Rise Time





This is the rise time at 10ns /div

Fall time



The fall time at 10ns / div

The circuit is performing very well. It probably exceed the ability of the Tektronix P6022 current probe.

Regards,
Jay_Diddy_B

[Jay_Diddy_B]

Hi,
I continued working on the Current Injector.

The components in the attenuator for the monitor port were installed. This network gives a 30 resistance at the emitter of Q4 and output impedance of 50

The combined result is a monitor signal that is 1mV/mA

Testing Monitor Output



The upper trace is the monitor output. The lower trace is the output current measured with a Tektronix P6022 probe.

Application

I am going to share one application of the current injector.

The current injector input is connected to the source of a network analyzer.

Channel R is connected to the monitor output of the current injector.

The current output is connected to a 1 resistor with a very short twisted cable.

Channel A of the VNA is connected across the resistor with a 50 cable.



1 Ohm Resistor



A 1 Ohm resistor consisting of three 3 resistors connected in parallel is used as a standard.

The VNA configured to display channel A / Channel R

This is voltage / Current



This is the result. It is very flat but increases above about 50MHz.

This result is normalized on the VNA.

The VNA is now calibrated in dB

Measuring a capacitor



A capacitor is connected in a similar way to the resistor.

Here is the graph:



The marker is indicating -9.21dB at 100kHz

-9.21dB = 0.346

C= 1/(2 x Pi x F x Xc)

C= 4.6uF



At the minimum the impedance is -46dB

-46dB = 5m

This is the ESR of the capacitor



With cursor at 20MHz the impedance is -17.3dB

-17.3dB = 136m

L = Xl / 2 x Pi x F

L = 1.08nH

This illustrates how the current injector can be used to characterise a ceramic capacitor.

Regards,
Jay_Diddy_B

[Jay_Diddy_B]

Hi,
Here is another measurement that can be performed with the Current Injector.

I have added a Bias Injector to the setup:



Here is a picture of the Bias Injector:



Impedance Measurement

I measured the impedance at 0V bias and I measured -8.53dB at 100kHz

-8.53 dB at 100kHz = 4.24 uF

I set the Bias voltage to 40V, this is a 50V capacitor, I measured -0.8dB

-0.8dB at 100kHz = 1.74uF

The capacitance has been reduced by 59% by the bias voltage.



Notice how the self resonant frequency moves to a higher frequency and the inductance of the capacitor is unchanged by the bias voltage.

Regards,
Jay_Diddy_B

[schmitt trigger]

Very, very impressive project.

Thanks for sharing.

[16bitanalogue]

A couple of comments:

1. This is a good DIY solution to measure passives. +/-10% is good enough as I typically want to be in the ballpark (sanity check).
2. There are several bumps in the transient response - this would indicate low phase margin, but this behavior is not observed on the voltage waveform. Are we exceeding the capability of the current probe? This is me really asking for less of a 'ripply' response.
3. Can you provide some additional insight into the purpose of Q5 'speed up trick'?  Is the intent to keep Q1, Q2, Q4 to share equally?
4. Are you comfortable of sharing the LTSpice circuit and the KiCAD files? I need to start dipping my foot into KiCAD myself - transitioning from Eagle.

I can compile a BOM and ultimately compare costs to PicoTest.

[Kleinstein]

The combination of Q1-3 + Q5 is a normal cascode circuit, nothing so unusual. It lets the collectors of Q1-3 see a low impedance for high speed. Just the choice of Q5 is odd to me: the MJE182 does not look like especially fast. My choice would be more like BD135, 2N2219, 2N3019.

[Jay_Diddy_B]

A couple of comments:

1. This is a good DIY solution to measure passives. +/-10% is good enough as I typically want to be in the ballpark (sanity check).
2. There are several bumps in the transient response - this would indicate low phase margin, but this behavior is not observed on the voltage waveform. Are we exceeding the capability of the current probe? This is me really asking for less of a 'ripply' response.

Snip ...

In the transient response the ripple could be coming from the source. It is pretty hard to make a square wave pulse with 5ns rise and fall times.

The frequency response on the VNA is flat. This suggests that there aren't any resonances in the circuit.

A couple of comments:


I can compile a BOM and ultimately compare costs to PicoTest.

There are some major differences in performance:

1) The circuit presented here is AC coupled so the maximum output voltage depends on the coupling capacitor in the output.

2) Because it is AC coupled it can safely be used when testing LDOs because it can't cause over voltages.

3) It has a HF -3dB bandwidth beyond 50MHz. The PicoTest product is useable to 40MHz it is actually about -15dB at 40MHz

The combination of Q1-3 + Q5 is a normal cascode circuit, nothing so unusual. It lets the collectors of Q1-3 see a low impedance for high speed. Just the choice of Q5 is odd to me: the MJE182 does not look like especially fast. My choice would be more like BD135, 2N2219, 2N3019.

This is correct Q5 is operating in common base.

The datasheet specification of the FT for the MJE182 is 50MHz

In this application the current gain is unity, so the BW=FT

I can't find FT on the BD135 datasheets from ST and ON-Semi.
(I suspect that they are similar to the MJE182, if not the same transistors)

The 2N3866 might be a good choice, but I am reluctant to use it because of the large number of fakes.

It is hard enough confirming the performance at 50MHz ….

Regards,
Jay_Diddy_B

[Kleinstein]

In a Phillips datasheet for the BD135 they give 190 MHz as typical fT. The BD135 is also a little lower current than the MJE182, so likely not the same chip. If the power is not too high the 2n2219 (250 MHz fT) could also work well - I would not expect to many fakes there.

[Jay_Diddy_B]

Hi group,

I tried this BD135 in the circuit, it made very little difference.



I am not sure of the manufacturer.

Regards,
Jay_Diddy_B

[Jay_Diddy_B]

Hi,
I did get some improvement by shortening the leads and twisting better.

Before



After



Note that the frequency sweep has been extended to 200MHz

New Wiring



This is how the connection was made for the improved result.

LTspice Simulation



The wiring inductance was stepped from 5nH to 200nH



The limitation is the wiring inductance, not the transistors.



Regards,
Jay_Diddy_B

[Wolfgang]

Very true. The fastest transistors will only lead to oscillations, a pragmatic design with moderate top frequency but robust and stable is better.
If you must have ultra fast edges think of an RF design directly attached to the load and using RF design rules.

What are your trying to measure ?

[Jay_Diddy_B]

Snip ..

What are your trying to measure ?

Hi,

The use of current injectors has been proposed, (by people that sell them) for evaluating the closed loop performance of power supplies where the top of the divider is not accessible and the there is no other suitable injection point.

I am not sure about the usefulness of this application. The reason is that this test is the frequency domain version of a stepped load current test. If the power supply is well damped you can't tell too much about the loop from the transient load test except that it is stable. If the power supply has a small phase margin you might be able to tell more.

Example



If I set the LTspice to measure the output impedance of the power supply, which has a known crossover frequency of 80kHz and phase margin of 85 Degrees

I get this result



At 10 MHz, the power supply has no influence, we are measuring 0.5 which is the ESR of the output capacitor.

At lower frequencies the control loop is reducing the output impedance.

I can't see how you learn about the phase margin from the output impedance graph.

Parallel Decoupling Capacitors

Measuring the effectiveness of decoupling capacitors is a good application for this type of current injector.

We often see multiple values of decoupling capacitors in parallel and explained like this:



It is not quite as simple as this.

I tested a 4.7uF capacitor on its own:



and 4.7uF capacitor in parallel with a 470nF capacitor:



Theses are the measured results:



The bright trace is the 4.7uF capacitor.

The dim trace is the parallel combination.

Note: there is a range of frequencies around 5MHz, where the parallel combination has higher impedance.


At frequencies around 20MHz the impedance is half for the parallel combination.  There are two ESLs  (1nH each) in parallel.

This is a good application for the high frequency current injector.

Regards,
Jay_Diddy_B

[16bitanalogue]

Hello Jay_Diddy,

Back some years ago, I would access stability of linear amplifiers solely by the rate-of-closure method with the closed loop gain graph superimposed on the open-loop gain graph. This is fairly simple to do because the feedback node is available, most op-amps can be modeled as a linear second order system; e.g., one, low frequency dominant pole and a high frequency pole with a nice 20dB/dec role off.

For Power supplies, feedback node is not available. Some adjustable options may have an external divider, but that is still not the feedback node of the error amplifier.

Frankly, in my limited experience with DCDC converters, the closed loop method is predominantly used in industry. The gain-phase is closed loop and the load step/release in the time domain helps correlate or perhaps better stated as "back up" the frequency response in closed loop.

Picotest has an application note on using the output impedance and Q of the response over frequency. I believe the purpose when measuring output impedance over frequency, one wishes to find the Q of the response and this is related to phase margin. Picotest pushes this as non-invasive measurement technique and frankly would be very helpful with customer designs when trying to determine stability in a production prototype or released system. Who wants to cut traces, which one may not even have access to in a 10 layer board, when one can measure output impedance.

I am simple person so Bode and load transients are my tools. When I grow up, I will try the output impedance method and/or Nyquist.

[Jay_Diddy_B]

Hello Jay_Diddy,


Picotest has an application note on using the output impedance and Q of the response over frequency. I believe the purpose when measuring output impedance over frequency, one wishes to find the Q of the response and this is related to phase margin. Picotest pushes this as non-invasive measurement technique and frankly would be very helpful with customer designs when trying to determine stability in a production prototype or released system. Who wants to cut traces, which one may not even have access to in a 10 layer board, when one can measure output impedance.

I am simple person so Bode and load transients are my tools. When I grow up, I will try the output impedance method and/or Nyquist.

This is really my point. If you have a power supply that that has a very dominant single pole, it doesn't have a measurable Q so you can't determine very much about the stability.

If you have a two pole system, the smaller the phase margin, the higher the Q and easier it is to determine stability with the current injector. But that isn't a good design anyway.

I am interested in trying to measure the stability non-invasively. I will try one day …

Regards,
Jay_Diddy_B

[16bitanalogue]

Hello Jay_Diddy,


Picotest has an application note on using the output impedance and Q of the response over frequency. I believe the purpose when measuring output impedance over frequency, one wishes to find the Q of the response and this is related to phase margin. Picotest pushes this as non-invasive measurement technique and frankly would be very helpful with customer designs when trying to determine stability in a production prototype or released system. Who wants to cut traces, which one may not even have access to in a 10 layer board, when one can measure output impedance.

I am simple person so Bode and load transients are my tools. When I grow up, I will try the output impedance method and/or Nyquist.

This is really my point. If you have a power supply that that has a very dominant single pole, it doesn't have a measurable Q so you can't determine very much about the stability.

If you have a two pole system, the smaller the phase margin, the higher the Q and easier it is to determine stability with the current injector. But that isn't a good design anyway.

I am interested in trying to measure the stability non-invasively. I will try one day …

Regards,
Jay_Diddy_B

I'm speaking from ignorance, but most DCDC converters that I have seen (buck, boost topologies mostly) are more complex than your textbook 2nd order linear system. There are multiple poles and zeros in the type 2 and especially type 3 compensator. I don't believe these types of designs could be modeled by a single dominant pole. My guess is this is where the current injector shines with the non-invasive measurement.

I still have trouble with the Bode 100 - trying to find a suitable signal level that 1) does not overdrive the feedback network at 'HF', and 2) large enough to overcome noise.

[Wolfgang]

Hi,

two comments about this:

- the NISM method is, strictly mathematically speaking, *only* correct if you have a second-order system, i.e. *one* dominant pole.
  Picotests has mentioned this (not very prominently) in their product description. Complex multipole systems - watch out

- for a system with strong resonances, its very normal that a sweep with a constant power level drives your system into nonlinearities
  in the vicinities of the resonances. It makes sense to run a sweep with non-constant power levels of the frequency range. A lot of VNAs
  can do that, what I know the Bode100 too (ask Omicron). A smart trick for stubborn systems is to use a flat noise source and then
  measure the frequency response by an FFT.

[Jay_Diddy_B]

Hi,

Using information that I found here:

https://www.picotest.com/images/download/non-invasive-assessment-of-voltage-regulator-phase-margin.pdf

I constructed a small signal model of a typical current mode switching power supply.

Included in the model:

A transconductance to represent the output stage
A transconductance to represent the error amplifier
A delay to simulate that the switching supply control is a sampled at the switching frequency

The power supply is two poles

The output transconductance and the output capacitor is one pole.
The Error amplifier is the second pole.

There is a zero in the error amplifier to obtain stability.

The error amplifier is 'stepped' to generate power supplies with different phase margins.



This is the invasive model. The loop gain can be measured from the error amplifier input to the output voltage divider.



These are the familiar Bode plots showing the bandwidth and phase as the error amplifier is stepped.


NISM Model




The is the NISM model. The model is set to measure output impedance.
There are .meas statements to measure the phase margin according to the reference above.

There are two methods. One is based on a simplified curve fit. The other is more accurate.



These are the impedance curves.


Results



You can see the differences between the techniques.

There is reasonable accuracy for Q greater than 0.8

The more complex calculation should be used for Q<0.8 or phase margin greater than 60 degrees.

Note:

This is all theoretical, it doesn't consider the challenges of measuring small signals in a noisy environment.

I have attached the LTspice model.

Regards,

Jay_Diddy_B

[Jay_Diddy_B]

Hi,

Let us look at the same power supply with a transient load step:



The power supply is arranged to step through the same error amplifier settings in the time domain.

Results




Observation if the phase margin is less than 70 degrees to you can estimate the phase margin by looking at the transient response.

If the phase margin is greater than 70 degrees, all you can determine is that the phase margin is greater than 70 degrees.

Regards,
Jay_Diddy_B

[Wolfgang]

in a few words: NISM: No good pole, no phase margin. Too many close poles/zeros: guesswork.

[16bitanalogue]

Hi,

two comments about this:

- the NISM method is, strictly mathematically speaking, *only* correct if you have a second-order system, i.e. *one* dominant pole.
  Picotests has mentioned this (not very prominently) in their product description. Complex multipole systems - watch out

Can you point out where Picotest subtly suggests this? It has been a long time, but if someone were to ask me to describe a linear second order system - I would pull from my op-amp knowledge base. A single, low frequency dominant pole around 10-100Hz and a single high frequency pole (perhaps 2) that is located after unity gain cutoff. The response would be your nice 20dB/dec roll off in gain.

When I review error amp (compensator) design in DCDC converters, I always see multiple pole/zero pairs throughout the bandwidth. Can you elaborate?

[Wolfgang]

IIRC, the method works on Q(Tg), i.e. the stepness of phase change at a pole.
As long the poles are well apart, and steep enough, OK. If not - see above.

IIRC, Sandler said the method is exact for 2nd order systems (which is correct). In return, it is *not* exact for higher order.

For really low impedance stuff, time domain techniques could be useful. Make a steep current step and watch the response.
I am notoriously sceptical of linear approaches in multiloop regulators. If just one of the loops gets nonlinear or saturated,
the whole theory falls apart. From a step response you dont have this problem.

[Jay_Diddy_B]

Hi,
If I further simplify the model by:

1) Removing the load resistor

2) Removing the ESR in the output capacitor

This make the output transconductance amplifier a pure integrator.

3) Remove the delay in the switching circuit. The delay only cause phase shift, no change in amplitude.

4) remove the noise filter in the error amplifier.

There is now two poles and one zero left in the loop.




The result of doing this:



The two results now agree exactly.

This confirms the comment from Sandler, shared by Wolfgang:

IIRC, the method works on Q(Tg), i.e. the stepness of phase change at a pole.
As long the poles are well apart, and steep enough, OK. If not - see above.

IIRC, Sandler said the method is exact for 2nd order systems (which is correct). In return, it is *not* exact for higher order.

Regards,
Jay_Diddy_B