How many vias to connect a small ground zone under a small boost converter ?

[microvia]

Hi,

In order to minimize the EMI of a small boost converter, I put a small ground zone around its components.
The pcb is a 4-layer type, with the bottom layer grounded.
The input voltage is under 1V to 3V, the output is 3.0V . The components are the boost converter IC which operates at around 1MHz, two 0805 capacitors and one 0806 inductor.
Looking at the layout below, what do you think about the number of vias around the boost converter components ? Are they way too many ?
Any info appreciated. Thanks !

[mtwieg]

That's certainly enough vias, having more wouldn't really help.

The main cause of EMI/ripple in a boost converter is the path through the output bypass cap, the area of that path should be kept as small as possible. So you should move things such that output bypass cap connects directly to the GND and Vout pins of the boost chip (pins 1 and 3). Are you using a TPS61322? It's datasheet gives layout suggestions.

But what you have will probably work fine anyways.

[MT4S301]

Metalized vias must have Cu pad diameter approx 2x larger than its drill diameter for DFM/reliability reasons. Your current design might be rejected by most fabs.

[tszaboo]

Metalized vias must have Cu pad diameter approx 2x larger than its drill diameter for DFM/reliability reasons. Your current design might be rejected by most fabs.

I agree. The term is "annular ring".
You also typically also don't place a via into the thermal cutout, as it defeats the purpose. Or no thermal cutout is needed.
I would move the output cap 90 degrees, and place it below the converter to be closer to it's ground. And leave place for extra capacitors.

[fourfathom]

You might consider reorienting the capacitors.  This tightens up the ground-current path, reducing the loop area. In the image I used an 0802 inductor footprint -- I didn't have the 0806.  And I used skinny traces, they should be fatter.  The main point is to keep the ground currents confined to a small area.  It might make sense to have some groundplane gaps partially surrounding the ground feedthroughs to approach a single-point ground topology.

[microvia]

Thanks for your explanations.
The vias have a hole diameter of 0.2mm and an annular ring diameter of 0.3mm. I have always used this without trouble so far.
I rotated 180 degrees the capacitor which had its grounded pad upwards. This should reduce the path.
The only thing which I wonder is the risks of MLCC cracks with the two 0805 capacitors located near the border.
The pcb is 1mm thick to reduce the global height (2.5mm with all components) as much as possible, so that the pcb can fit in small devices with limited space / height.

[Manul]

Solid ground plane and a via close to the pad for every component which needs GND is a general rule. Basically you should imagine that you don't have any ground pour on the signal layer (even if you do) and connect everything to the ground plane with vias. Beyond that, I don't think that you will get significant improvent with more vias. The next step would be a shield can.

The pcb is a 4-layer type, with the bottom layer grounded.

Does that mean that bottom layer is your only solid ground plane? Having ground plane as the closest layer is best and could be a significant improvement (this makes via inductance way smaller, like perhaps an order of magnitude smaller).

[microvia]

Solid ground plane and a via close to the pad for every component which needs GND is a general rule. Basically you should imagine that you don't have any ground pour on the signal layer (even if you do) and connect everything to the ground plane with vias. Beyond that, I don't think that you will get significant improvent with more vias. The next step would be a shield can.

Or maybe move the boost converter components to the bottom layer (ground) ?

Does that mean that bottom layer is your only solid ground plane? Having ground plane as the closest layer is best and could be a significant improvement (this makes via inductance way smaller, like perhaps an order of magnitude smaller).

I know nothing about via inductance, so will look around.
The layer stack is Signal - Vcc - Signal - Gnd.
Pouring ground on the top layer would make the boost converter spread its noise all around. Instead, a better layer stack could be Signal - Gnd - Signal - Vcc. The second signal layer has less than ten tracks.

[Manul]

Or maybe move the boost converter components to the bottom layer (ground) ?

Solid, continuous ground plane is essential. Ideally it should be directly under (or above) signal layer, so via height is small. Common 4 layer stackups have 0.2 or even 0.1mm gap between top and first internal layer. That is way shorter distance than top to bottom (commonly 1.6mm). Small distance to ground plane also greatly reduces parasitic trace inductance, because it reduces vertical loop area. Smaller loops, planar and vertical (between layers) are always better.

Signal - gnd - gnd - signal (power is routed on signal layers) might be a great stackup too (depends on situation).

By the way, besides layout, boost converter EMI depends greatly on switching speed and I don't mean base frequency, I mean rise and fall times of gate driver and switching node dv/dt. So adding gate resistor will slow the edges and reduce EMI, especially in high frequency RF spectrum range (kills high harmonics). You will loose some efficiency though.

[Geoff-AU]

Solid, continuous ground plane is essential. Ideally it should be directly under (or above) signal layer, so via height is small. Common 4 layer stackups have 0.2 or even 0.1mm gap between top and first internal layer. That is way shorter distance than top to bottom (commonly 1.6mm). Small distance to ground plane also greatly reduces parasitic trace inductance, because it reduces vertical loop area. Smaller loops, planar and vertical (between layers) are always better.

Signal - gnd - gnd - signal (power is routed on signal layers) might be a great stackup too (depends on situation).

By the way, besides layout, boost converter EMI depends greatly on switching speed and I don't mean base frequency, I mean rise and fall times of gate driver and switching node dv/dt. So adding gate resistor will slow the edges and reduce EMI, especially in high frequency RF spectrum range (kills high harmonics). You will loose some efficiency though.

This is great advice on 4-layer stackup + rise times. 

[Smokey]

This is what makes 4Layer layouts hard.  If this is a personal project or a high value commercial project, maybe consider 6 layer when you run into this sort of thing.  The boards are going to be more expensive, but likely not drastically more expensive.  And you get "free" plugged vias with 6 layer at JLCPCB.  6Layer makes it much easier to keep a ground reference per signal/power layer and have enough routing layers.

[microvia]

I changed the stackup to Signal - Gnd + 4 tracks - Vcc - Signal (only 2 tracks).
The 4 tracks on the Gnd layer include one clock track (< 100KHz) so I chose to increase the Gnd zone clearance to 0.5mm.

[tszaboo]

This is what makes 4Layer layouts hard.  If this is a personal project or a high value commercial project, maybe consider 6 layer when you run into this sort of thing.  The boards are going to be more expensive, but likely not drastically more expensive.  And you get "free" plugged vias with 6 layer at JLCPCB.  6Layer makes it much easier to keep a ground reference per signal/power layer and have enough routing layers.

I don't really find them hard to do TBH. Though I've been doing S-G-P-S, with GND flooding on the top and bottom, stackups for a while now. Some people frown on it, but I've never really failed an EMC test because of the stackup. 6L would be easier, but it is higher cost. I think I'll have to do a 6L board again soonish because of isolation distance and size of the board, but not because of EMC.

[Manul]

I changed the stackup to Signal - Gnd + 4 tracks - Vcc - Signal (only 2 tracks).
The 4 tracks on the Gnd layer include one clock track (< 100KHz) so I chose to increase the Gnd zone clearance to 0.5mm.

That is a big mistake. GND plane should not have any tracks. Tracks on GND layer split the plane and it is no longer continuous. This may drastically increase ground return paths, because return current must go around the splits.

[microvia]

Thanks for your hints. I modified the layouts as shown below, and applied the following:
- Grounds moved to L2 (under to copper layer). Instead of one ground plane, I created a ground zone for each section (MCU, audio, boost converter), all connected to the central ground zone of the common LDO, and to which the upper left ground pad is connected.
- VCC lines arranged in a star network instead of a whole layer, as they were not many.

What I'm wondering is how I should connect the boost converter ground zone (down right).
I hope I'm (almost) done with the overall layout !

[Manul]

You certainly like to invent things. I don't even know what to say. To me it looks like a mess and I think it will perform worse than solid ground plane.

[tszaboo]

Thanks for your hints. I modified the layouts as shown below, and applied the following:
- Grounds moved to L2 (under to copper layer). Instead of one ground plane, I created a ground zone for each section (MCU, audio, boost converter), all connected to the central ground zone of the common LDO, and to which the upper left ground pad is connected.
- VCC lines arranged in a star network instead of a whole layer, as they were not many.

What I'm wondering is how I should connect the boost converter ground zone (down right).
I hope I'm (almost) done with the overall layout !

(Attachment Link)

I have one questions.
Why?

[microvia]

I'm not an expert in PCB layout, but thought I could reduce the noise spread by the MCU and eventually the boost converter when used, without going into expensive options.
For these reasons, I made individual ground zones so that the MCU, audio and boost converter grounds are connected to the central LDO ground, which itself is connected to the upper left via through the orange track.
Please explain why a plain ground zone is better. I'm happy to roll back to the previous design.
Same with the VCC lines in star network (yellow lines), which replaced a plain VCC zone.

[tszaboo]

I'm not an expert in PCB layout, but thought I could reduce the noise spread by the MCU and eventually the boost converter when used, without going into expensive options.
For these reasons, I made individual ground zones so that the MCU, audio and boost converter grounds are connected to the central LDO ground, which itself is connected to the upper left via through the orange track.
Please explain why a plain ground zone is better. I'm happy to roll back to the previous design.
Same with the VCC lines in star network (yellow lines), which replaced a plain VCC zone.

https://resources.altium.com/p/splitting-planes-good-bad-and-ugly

To make things easier, we can readily debunk all of the foregoing and say they are not true. But, perhaps one of the most important takeaways is that you should NEVER, EVER split ground planes. If you do, you will destroy the integrity of your PDS.

[microvia]

Thanks for this interesting link. Plane ground zone is put back in place.
I also improved the ground path around the boost converter IC.

[hugo]

I'm not an expert in PCB layout, but thought I could reduce the noise spread by the MCU and eventually the boost converter when used, without going into expensive options.
For these reasons, I made individual ground zones so that the MCU, audio and boost converter grounds are connected to the central LDO ground, which itself is connected to the upper left via through the orange track.
Please explain why a plain ground zone is better. I'm happy to roll back to the previous design.
Same with the VCC lines in star network (yellow lines), which replaced a plain VCC zone.

https://resources.altium.com/p/splitting-planes-good-bad-and-ugly

To make things easier, we can readily debunk all of the foregoing and say they are not true. But, perhaps one of the most important takeaways is that you should NEVER, EVER split ground planes. If you do, you will destroy the integrity of your PDS.

And another one:
How to Achieve Proper Grounding - Rick Hartley

[microvia]

VERY interesting indeed ! I'll have to watch this maybe two times. Right now the layer stack is Signal-GND-VCC(star)-Signal.
I saw in the video that the author likes GND-Signal-Signal-GND but I wonder how many vias you need to connect your smd components together with this method, unless you have vias-in-pads, which all PCBAs don't necessarily offer like JLC.
I'll eventually post a photo of my updated layout.

One last question: I never studied the use of metal cans for shielding. So many modules use them that I'm wondering if PCBAs have some tools to make custom cans at affordable prices for 250+ pcbs ordered.

[Manul]

You need to develop some intuition on what are good practices in PCB layout. Once you get that intuition, you can't undo it, it just stays with you.

You might find some useful, easily digestible information in these YouTube channels:

Hans Rosenberg
"Top 5 PCB Grounding Mistakes That Cost Me Thousands"
"Why Your Ground Design is WRONG — and How to Fix It. Flawless PCB design part 6"

Robert Feranec
"What Every PCB Designer Should Know - Return Current Path (with Eric Bogatin)"
"What Every PCB Designer Should Know - Crosstalk Explained (with Eric Bogatin)"

Anyway, if you are trying to achieve a low noise design, you shouldn't blindly add more vias, shielding cans, mu-metal shields and whatnot (aka over-engineer and pray). First of all, you must clearly understand the problem you are trying to solve. It might be, that there is no problem at all and you don't need these shielding cans. In case you actually see a problem, define your noise sources, what are their frequency spectrum, power. Define sensitive signal nodes. Is it capacitive coupling into high impedance nodes? Is it magnetic coupling? Is it perhaps PSRR related issue? Once you clearly characterize the problem, then look for a solution.

[Smokey]

You need to develop some intuition on what are good practices in PCB layout. Once you get that intuition, you can't undo it, it just stays with you.
You might find some useful, easily digestible information in these YouTube channels:
...

Or... spend about 5-10 years doing layouts at a company with senior pcb designers that can act as mentors. 

Seriously though, just make lots of boards.  Stay away from stuff like RF and HDMI and you will probably be fine, even with wacky unnecessary star ground layers.  When it doesn't work, make sure you learn something, fix it, and try again.  Boards are so cheap now it's easy to play.  I still have some of the terrible terrible layouts I made when I was starting out (hand etched and everything). 

About the specifics, you are overthinking all this.  No need for star grounds.  No need to worry about EMI at all.  You are never going to get FCC/CE tested and you won't have the test equipment to measure it, so don't sweat it.  Just select a part that has a recommended layout and copy that.  TI is really good about this (Yes I know everyone rips app notes and recommended layouts and such, but it's a significantly better starting point that this).

[Kokoriantz]

Just a side subject question.
I always apply 2 vias directly under the tab of 1206 smd capacitors.
I see this is avoided here, is it a bad idea?