EEVblog Electronics Community Forum
Electronics => Projects, Designs, and Technical Stuff => Topic started by: new299 on December 17, 2017, 06:53:39 am
-
Perhaps this should really be in the beginners section, if so, perhaps some kind mod would move it.
I'm interested in trying to design a basic multislope ADC. As a first pass, I'd like to understand if something like the attached design might work, or if there's anything I've woefully misunderstood.
The design would use a microcontroller to control a DG411 switch, this would switch in the positive/negative references. LT1013s are being used to buffer the reference, and as the integrator, comparator. Later the design could be expanded adding more slopes etc. At present, I'm just trying to understand if the basic architecture is sane.
Any comments are most welcome!
-
The inverter for the reference does not work this way - it should be obvious, unless this should really go the the beginners section.
The way the reference current is switched is not the best choice: the switched current is a rather dynamic load to the reference - this is especially a problem for the rather slow "buffers". When switched off, it takes a relatively long time to discharge the switch side of the resistor - thus short off times are not working well. There are other more suitable configurations, like having only one resistor for the positive and negative reference current and switch between those two.
The LT1013 is not working well as a comparator. Many µCs have a much better comparator inside.
The LT1013 OP might not be the best choice for the integrator: it has rather high noise and bias current and also is rather slow. So the ADC would not give a really low noise and work well only at low speed, with a relatively large integrating capacitor. The more normal choice for the integrator would be a JFET based OP, like TL071, LF411 or better (e.g. AD711).
Most simple integrating ADC use an additional switch to reset the ADC to a well defined start. There are ways to do without it, but this is the more difficult way.
-
Many thanks for your suggestions. I've modified the schematic as attached.
I assume reset would be implemented as a switch across the integrating capacitor?
Using a single resistor for both positive and negative references would imply a dual-slope configuration? I was planning to use a multislope run-up configuration, but also try dual slope (layout the circuit so I can use a single resistor for both references too).
Are there alternatives/switches schemes I am missing?
-
One would be limited to dual slop, if only one resistor is used for the signal and both signs of the reference level. Using one resistor for both signs of the reference still allows applying the input signal and reference. Using just one resistor would be having both switches connected before the resistor. The only case no longer allowed is having both references active at the same time. To avoid this problem (e.g. during transients) one might add separate small series resistors.
The other common switching scheme is using a SPDT switch connected at the integrator side on the resistor. Here the reference current is either send to the integrator or to ground. As the switch only sees low voltage, one can use a simple 74HC4053 for this: one for the input and one each for the two polarities. This scheme has the advantage that the current drawn from the reference is constant. Also the power dissipation in the reference path resistors is constant.
The true dual slope conversion uses the same resistor for the signal and the reference. So this would need a different circuit. I have seen such a combination: here the signal and reference signal are added in the input amplifier by using a switched capacitor for the reference. So as a side effect they also don't need an extra negative reference. So the signal applied is either just the input or input +/- reference.
For the reference part and maybe the input amplifier, it is still good to use the LT1013 OP. The AD711 is only a good choice for the integrator. So it usually takes different.
-
Use another analog switch before the input signal buffer so that the autozero cycle can remove its offset voltage as well. This is how fully integrated slope converters were able to achieve microvolt accuracy using low precision CMOS processes.
Study old designs like the Fairchild 3814 and Siliconix LD120/LD121A and LD111A/LD110. Siliconix used a run-up design which extends the range of the integrator for less non-linearity error due to dielectric absorption so it is potentially better than the more common ICL7104 implementations. By fixing the number of switching cycles, charge injection errors may be calibrated out; HP did this in their high resolution meters like the HP 3456A through HP 3458A.
https://xdevs.com/doc/HP_Agilent_Keysight/journals/1989-04_HP3458A.pdf
The simplest design I would attempt is to combine the run-up of the Siliconix parts (HP called this Multislope Runup) with the charge injection cancellation of the HP designs. If that did not yield 10 times better linearity than the 40,000 count ICL7104 design, then I would be disappointed.
-
how does charge cancellation of these switches work? I thought it was dependent on the voltage the switch is facing. At least the LTC1043 datasheet lead me to believe this.
I am interested in lockin amplifiers. I think the optical optimos devices have basically no injection.
-
how does charge cancellation of these switches work? I thought it was dependent on the voltage the switch is facing. At least the LTC1043 datasheet lead me to believe this.
I am interested in lockin amplifiers. I think the optical optimos devices have basically no injection.
This is different from minimizing the amount of charge. Instead during the run-up cycle of the integrating converter, there are a constant number of switch cycles whether they are needed or not so the injected charge is constant and calibrated out during the zero calibration. From the HP Journal that I linked:
An important requirement for any ADC is that it be linear. With the algorithm described above, multislope runup would not be linear. This is because each switch transition transfers an unpredictable amount of charge into the integrator during the rise and fall times. Fig. 6 shows two waveforms that should result in the same amount of charge transferred to the integrator, but because of the different number of switch transitions, do not.
This problem can be overcome if each switch is operated a constant number of times for each reading, regardless of the input signal. If this is done, the charge transferred during the transitions will result in an offset in all readings. Offsets can be easily removed by applying a zero input periodically and subtracting the result from all subsequent readings. The zero measurement must be repeated periodically because the rise and fall times of the switches drift with temperature and thus the offset will drift.
-
Thanks David and Kleinstein for your helpful comments.
I've moved to using a single resistor for both references in the attached schematic. If I can get this design working, I'm wondering about modifying it to create a multi-slope run-down design. In this configuration, I could use the 74HC4053 to switch in the resistor on the integrator side, or switch to ground is that correct? Could I also use a DG419 here, though not strictly required?
I've also added in a autozero switch, using a DG419. I've reverted to the LT1013 for the reference buffers. Is there a better part to use for the input output buffers (I've currently left these as AD711s). I feel I don't have a strong grasp of the required specifications, and will try and read more about this.
Thanks again for your help.
-
Is there a better part to use for the input output buffers (I've currently left these as AD711s). I feel I don't have a strong grasp of the required specifications, and will try and read more about this.
The input buffer is usually a low input bias current part to present a high input impedance to the source but the AD711 covers that. This is needed if a high input impedance attenuator is used and it also makes overload protection easier.
One thing I do not quite understand in these designs is that the common mode rejection of the input buffer should limit the linearity yet in the past, they got by with truly terrible integrated CMOS input buffers. The implication is that the input buffer should be a precision JFET or CMOS part with high common mode rejection like the currently available LT1793/LT1055/LT1056/LT1122/LT1022 or if you are adventuresome, the much higher precision LT1012 low input bias current *bipolar* part. The AD711 is not bad in this respect either. I seem to recall doing the calculations and concluding that integrated chipsets were limited to less than 4-1/2 digits of accuracy because of this and it might explain why some old multimeters bypassed the built in integrated CMOS input buffer and replaced it with a part like the AD542. Or maybe most of the error contributed by the common mode rejection shows up as gain error instead of non-linearity.
I am not sure why the output buffer would be needed. The integrator has a pretty low output impedance and should not have a problem driving the comparator. Maybe isolation is needed?
I would start off using a less expensive part in place of the AD711 or any of the others above like the TL051.
-
Thanks again! I maybe getting ahead of myself, but... for this kind of layout is there any reason to prefer through-hole parts over SMD (ICs)? I’ve read in reference circuits people sometimes worry about SMD parts being under additional mechanical tress, and this introducing error somehow? (I’ve seen this mentioned with respect to reference circuits mostly).
A normal ground fill would be acceptable? Are there any particular points I should take into consideration?
-
It should be Ok to use SMD parts. With a MUX at the input to do an automatic zero adjustment, there are no parts that are really critical with respect to DC performance. For very high accuracy THT parts may have a slight advantage of less leakage and less stress sensitivity for the resistors, but this is if you go for more than 7 digits. One advantage with THT parts is the option to have sockets and change the OPs later on. So one can first test with TL071 and later upgrade to something like OPA140 if needed. For a hand soldered board one can mix SMD and THT.
The integrator should be a good quality JFET OP. The AD711 is just one such OP, there are other's. I mentioned it because it is was used in some older DMMs. However there are other choices - likely better ones too. For a first test a TL071 or LF411 should also be OK. It helps to have a good BW and low noise both in the LF and MHz range.
For a precision circuit a ground fill is not a good idea. Usually the better way is having a dedicated ground star point. Also decoupling can be important, it should be made the right way. Another important point can be the choice of the integrating capacitor. It should be a low loss (DA) type, like PP film or a good quality NP0 ceramic.
For good linearity the TC of the resistor for the input signal is also important: self heating could otherwise cause nonlinearity. Also having a higher power rating can help. It is less important with the reference resistor(s), as here the current is constant.
Especially if a slower rundown slope is also used, it helps to have another amplifier following the integrator. Not just a buffer, but an amplifier with well defined saturation to help the comparator.
I don't think the last circuit diagram was updated. For the switching there are mainly two options:
1) 1 reference resistor and switching between +ref,-ref and maybe GND
2) 2 separate reference resistors (+ref and -ref) and switching at the integrator side with something like DG419 / 4053.
One should use the same type of switching for both the input and the reference. It also helps to have the same or at least similar resistance.
-
I don't think the last circuit diagram was updated. For the switching there are mainly two options:
1) 1 reference resistor and switching between +ref,-ref and maybe GND
2) 2 separate reference resistors (+ref and -ref) and switching at the integrator side with something like DG419 / 4053.
One should use the same type of switching for both the input and the reference. It also helps to have the same or at least similar resistance.
Thanks again, regarding the above. Does the attached schematic now correctly reflect option 1? Regarding "maybe GND", what would the purpose of grounding the reference resistor be. Would this be for use when reseting the integrator?
Thank you also for your layout suggestions. As suggested, it sounds like a good idea to use through-hole parts so I have the option of using socketed opamps and experimenting.
Regarding the output amplifier, I'm wondering what to do here. In particular I've been wondering if it might be interesting to try implementing the control logic with an FPGA at some point (or is this just wasted effort?). If I want to leave the FPGA option open, might having an onboard comparator simplify things? Otherwise I will likely use an AVR for the initial design, and assume its comparator is suitable.
-
Grounding the reference current not used would keep the current through the resistor constant. Otherwise one would get a modulation in temperature too. In addition there is parasitic capacitance that would also change charge. Usually the break before make time of the switch (e.g. 4053) is so short that the integrator / GND side of the resistors would not change voltage very much due to the parasitic capacitance.
It is a good idea to have a similar switch also in series with the resistor used for the signal current. So there should be an additional DG419 after the input buffer. The switch resistance usually has a high TC, but if balanced for signal and reference this would no have that much of an effect.
One can implement the control logic in an AVR µC However for getting exact, prdictable timing it might need ASM programming , but this is possible. The only really time critical part would be the rundown phase, to stop the coarse rundown.
Unless you need a very fast converter, there is little advantage of using an FPGA instead - it's just more expensive and difficult to program.
Using the µC internal comparator just makes the HW simpler, an external LM311 would be about as good, likely even lower noise. However with an extra amplifier stage comparator noise does not matter much. With the AVR one could even use the µC internal ADC for an additional fine step for the residual charge after rundown.
-
I would use sockets for the operational amplifiers just so that I could start out with cheap TL051s until everything works and then change them to the much more expensive precision types. It would be interesting to see how the accuracy is affected by different operational amplifiers.
-
Grounding the reference current not used would keep the current through the resistor constant. Otherwise one would get a modulation in temperature too. In addition there is parasitic capacitance that would also change charge. Usually the break before make time of the switch (e.g. 4053) is so short that the integrator / GND side of the resistors would not change voltage very much due to the parasitic capacitance.
It is a good idea to have a similar switch also in series with the resistor used for the signal current. So there should be an additional DG419 after the input buffer. The switch resistance usually has a high TC, but if balanced for signal and reference this would no have that much of an effect.
Thanks. If I've understood correctly the configuration I currently have is a multi-slope run up converter [1]? With a shared resistor for the positive and negative references. In this configuration, this resistor will therefore always have the same current flowing through it, is that correct? However if I were to move to a multi-slope run-down configuration [2], it would be valuable to switch the resistors to ground when not in use, to ensure that they are kept at the same temperature.
The purpose of the additional switch on the input signal is also for use in the multi-slope rundown configuration, and is used when removing the input signal current at the start of the run-down phase.
Perhaps the next stage is to modify the schematic so it represents a full multislope rundown configuration.
[1] https://upload.wikimedia.org/wikipedia/en/thumb/3/30/Multislope_runup.svg/500px-Multislope_runup.svg.png
[2] https://upload.wikimedia.org/wikipedia/en/thumb/f/f3/Multislope_rundown.svg/510px-Multislope_rundown.svg.png
-
The question of mulit-slope run-up is more a question of the software / control: it needs (there is a way around that too) separate resistors for the input and reference, so that input and reference can be active at the same time. Using some feedback already during the integration of the input signal is usually the more important improvement over the dual slope mode.
For a multi-slope rundown it can help to have the configuration with switches at the integrator, as the resistors can keep there constant current, when not active to the integrator. This also helps to avoid a highly dynamic load to the reference amplifiers.
Unless the rundown needs to be super fast there is not that much need to use many slower slopes for the rundown. Especially when done with the µC to control, there will be some delay on switching and thus only 1 slower slope is likely enough. A suitable offset to the comparator could compensate the delay. The slower slope also needs extra adjustment measurements - so having more makes thinks rather complicated at a rather small gain in speed. To get the slower rundown reference one could in theory use both the positive and negative reference together, if they are intentionally slightly (e.g. 2-10%) different.
The pictures from Wikipedia are still only the very basic concept, so they don't care about the details of how the switches are made.
The switch for the signal current is needed for the rundown phase, so that integration of the input stops. The other purpose of the switch is usually compensation of the switch resistance. As the switch resistance is rather temperature dependent, it really helps. to have the same type of switch for both the signal and reference currents. It also helps to have the same resistance for signal and reference currents, so that the contribution of the switch will be the same.
-
Thanks again!
In the attached schematic (multislope_r5), I've modified the configuration to match that shown in the 3458a document previously linked.
Practically, I might just want to use a single large resistor in the same configuration as +/-S1024 if I've understood your suggestion correctly? (as multislope_r5a).
In the path from the input signal, I have one switch. In the reference paths two. Should I have the same number of switches in the reference and signal paths?
-
It helps to have the same number of switches for the reference and the signal path. It would help to have a second switch for the signal two, even if this is just for compensation. It could be used to switching between the input and maybe 0. The scheme as drawn with 2 switches is unusual, but still possible and it has some advantage too. The simple (and common, e.g. 34401, 3458, K2000,K2002) solution is to use separate resistors for the + and - reference. It adds the need for two matched resistors, but there is a pair of resistors to make -ref anyway. So there is not that much added possible temperature drift. It helps if the switches are well matched.
The slower slope reference currents can use more switches as the resistance is higher anyway and they are used only for a small fraction. So this could be just one large resistor and than switching the voltage if needed (e.g. full and - 1/8 of the reference). The 3458 uses this scheme, even with just a 74HC14 as a switch (R2R like DAC ?). Due to the higher resistance self heating is not that important and the requited stability is also much lower.
-
Thanks, I have made changes based on your suggestions.
I'm trying to understand which resistors are critical now.
If I've understood correctly, in the 3458a all the slope resistors (and the input resistor?) are part of the same network (which is part of U180?). This means the TCR tracking of all these resistors is good? [1].
Obviously, I don't have the option of having all resistors in the same network. However it might be possible to try having some of the resistors in the same network. It seems useful for example to have the input resistor and the largest slope resistor as part of the same network (well essentially on the same substrate/in same package?). Same would go for the negative reference resistors perhaps?
The output amplifier seems less critical.
Regarding what kind of resistor, I was thinking of doing the layout such that I could optionally try using foil resistors. Do you think this could help, or is it likely that the TCR of other parts of the circuit would make this pointless. There seem to be some nice networks containing 2 47K foil resistors which I could potentially use for the input/largest slope resistors [2].
I'd be interested in hearing thoughts on this, and if I've seriously misunderstood anything.
[1] Vishay Advantages of Precision Resistance Networks for Use in Sensitive Applications Technical Note: http://www.vishaypg.com/docs/63512/VFR_TN109.pdf (http://www.vishaypg.com/docs/63512/VFR_TN109.pdf)
[2] https://www.ebay.com/itm/1x-300198-47K-4K7-4K7-47K-High-Precision-Custom-Networks-2-3-or-4-Resistors/121930640926 (https://www.ebay.com/itm/1x-300198-47K-4K7-4K7-47K-High-Precision-Custom-Networks-2-3-or-4-Resistors/121930640926)
-
The multi-slope converter does not have that many critical resistors. To keep it relatively simple I would definitely not use that many different slopes for the rundown as the 3458 does. The many steps are mainly for high speed - if you have enough time (e.g. another 50-100 µs) one slower slope should be all it takes. This is how the Keithley 2002 does it. Having only one fine slopes means there is only one resistor ratio to adjust or with a modern design to measure. The extra steps used in the 3458 allow for a faster conversion, but it is not helping with accuracy - more to the opposite.
Drift in the resistors has 3 effects:
1) a shift in the offset. This is not that critical, as one will most likely have a kind of auto-zero measurement anyway. Thus alternate signal and zero. There are other source of an DC offset (OPs, input amplifier) and 1/f noise is also reduced by the alternating measurements. So this kind of drift is easy to compensate for.
2) Drift can also cause the gain of the ADC to change. For long term, there usually is a direct path from the input to the raw (e.g. 7 V) reference to adjust the gain. This takes some time and adds noise and thus is usually not done that often. So compensation is possible, but good stability is an advantage.
3) If the ratio of the fine a coarse slope changes, this effects the linearity. Old meters like the 3456 used very stable ratios, adjusted to the exact numbers wanted to simplify math. Not sure about the ratios in the 3458 - they might be fixed and critical, but a self calibration of those rations is also possible, so that ratio drift can be compensated for. Especially with just one slow slope a periodic adjustment is possible, at least to get rid of long term drift. However this adjustment will take some time, though the adjustment for just a single fine slope might not be so bad.
The resistors at the reference amplifier (e.g. +-10 V) part will effect the gain and especially the zero drift. The gain usually scales a little slower than linear with the resistors. Depending on the circuit it takes 3 or 4 resistors.
If 2 separate resistors (as with switching at the integrator) are used for the + and - reference path, these two resistors also effect the zero drift, just like the inverter. So good TCR matching (like R1*R2 = R3*R4) of these 4 resistors might help. In a set of 4 one could try swapping two to get the better matching. The resistors also effects the gain. In theory the LT5400 network might be an option - but hard to solder and limited values. Also capacitive coupling might not be that much desirable.
If a single resistor and thus switching at the +-ref voltage side is used, the resistor is mainly for the gain and TCR matching to the input resistor would be good. The fine slope resistor (if a separate one is used) has only minor effect - more like effecting DNL, and not very much.
The resistor for the input path effects the gain. In addition this resistor can have an effect on INL due to self heating. So here a low TC / low voltage coefficient is also a good idea, not just TCR tracking.
The switches are in series to the resistors and thus there is a limited use in using extremely good resistors, if the switches are not coupled as well. AFAIK the switch resistance has an TCR of about 6000 ppm/K so with 100K in series to a 100 Ohms switch, there will be an effective TCR of about 6 ppm/K, though with reasonably good matching. However tracking of the switches will be less accurate if one is at +ref and one at -ref in the one ref resistor scheme.
There is no need to have the negative and positive ref at exactly the same magnitude. So there is no need for accurate value matching. In the scheme of switching at the integrator slightly (e.g. 5%) different voltages could even be an advantage, as they would also make up a fine slope (using both refs together). I would consider this a rather clever idea, as it comes at essentially no cost and there is no problem with having a higher impedance switch for the fine slope. At first using + and - reference together to get the small difference sounds like a bad idea, but this is only used for a very short time (e.g. 10 µs) and thus has little effect and the two sources are used anyway alternating, so the difference already matters.
For the 3458 the input and coarse slope resistors are part of the same network. Not sure about the very fine ones, but these are not critical and done with a reduced voltage anyway. The same network also contains the resistors for the reference scaling to go from 7 V to a +-12 V.
The TCR tracking will be very good. It also provides a large substrate for the input resistor to get low self heating to effect INL.
As one can relatively easy do adjustment measurements for the drift, I don't think one will need such super stable resistors for the first test. One could still get stable readings, if one uses not just a zero adjustment, but also a gain adjustment more often. It would just reduce the speed to maybe half. With same value / same batch resistors, there is still a chance to get reasonable matching, even if not on the same substrate.
Due to the higher demand on the input resistor, one might use a better one here, even if this means not having matching to the reference resistor(s). Having the option to change to a different form factor can be a good idea. My guess is the first board could start with something like 15 or 25 ppm/K (e.g. thin film) resistors - there are still chances the first layout might not work that well. The first version is likely also much about getting the software right and finding those nasty points that don't work as supposed.
For me the really unknown is the stability of the charge injection of the switches and also jitter caused by the switches. So hard to tell how suitable the DG419 or 74HC5043 are.
The amplifier behind the integrator is not that critical - so no special resistors needed there.
Another point to look at can be the integrator itself. Most better DMMs use a kind of compound amplifier made from 2 OPs for the integrator. This can help to have a more ideal behavior. However it can also be tricky to get stable without too much ringing. I think that today there should be better OP available as for the old days DMMs where we have schematics from. Some of the choices found in the old plans look odd from todays perspective. Chances are there are better alternatives today.
-
Thanks again for your detailed observations. I will work with thin film resistors at first, but try and do the layout such that I can try foil resistors/networks are the suggested points later if everything comes up correctly.
Based on your note regarding using multiple opamps in the integrator, I've been reviewing the Keithley 2000,2001 and 2002 schematics. As far as I can tell these all use off the shelf parts, and the design should be instructive. I've attached copies of the integrator sections of various (reverse engineered) schematics I've found online (thanks to TiN and others).
Based on the schematics, I've made note of the opamps used below. However, I don't fully understand how they are being combined, and what benefit this provides. Is there any good reference on this?
In the Keithley 2000, there's a OPA177 which provides some kind of offset, to the second opamp which is a AD711. But I'm not clear as to why. Any pointers you can give me would be most welcome.
Below are my notes on which parts are being used in the integrators, as I understand it:
Keithley 2000
Integrator opamps: OPA177GS AD711JR
Gain opamp: NE5534D
Integrator cap: 222...
Switches: VN0605T SD5400
Keithley 2001
Integrator opamps: OPA177GS OPA602AP
Gain opamp: NE5534D
Integrator cap: 10nF Polypropylene 10%
Switches: ??
Keithley 2002
Integrator opamps: OP177G AD711JR AD744JR
Gain opamp: ?
Integrator cap: 100nF? 2.2nF np0?
Switches: SD5400C
-
I also though about building an integrating ADC and thus had looked at some points before.
In my understanding, using 2 OPs for the integrator serves 2 purposes:
For sufficient BW without excessive input bias and current noise one essentially needs a FET based amplifier for the Integrator. However the DC 7 low frequency specs of those OPs are usually not that good. The 2 OP circuit can kind of split the low frequency and high frequency part. With something like the OP177 for the low frequency / DC part and an AD711 for the fast part.
The 2nd effect of the 2nd OP is that the input voltage is low even if a small capacitor is used. Otherwise one has a input voltage of about 1/ GBW / C_int. In a first approximation this isn't even that bad, as it is still linear, but GBW is not that stable and there can be second order effects. To reduce the input voltage it is a good idea to have the low frequency OP to be reasonably fast too. However for stability reasons the additional OP for the DC offset should not be faster than the 1st. OP. From the frequency response, I like the combination used by HP in the 34401: an AD711 as the fast part and an OP27 with a divider at the output for the "slow" part. The divider effectively reduces the GBW of the OP and in addition reduces the higher frequency noise contribution - though it won't be a big deal with the OP27, but it can be worth it for the OP177 or similar. However the OP27 has too much input current noise to be considered a good choice.
My personal favorite would be a combination with two OPA141 or similar OPs. These modern JFET OPs are in the higher frequency part better than the AD711. The low frequency noise is surprisingly good - not much higher voltage noise than the OPA177 and essentially no current noise. A lower cost alternative would be an OPA134. There is a higher DC drift, but for good DC precision one would use a kind of AZ mode anyway. A divider at the output of the additional OP (e.g. 1:10) should set a reasonable speed ratio with two equal OPs to get a stable and fast response.
The extra Gain stage before the comparator seems to be OK with the NE5534 used in many versions: It's low noise, fast and low cost.
Anyway the OP's usually use the same pinout. So one can change this later if needed.
-
I replaced OP177 with ADA4077-1 (0.25 ?V p-p noise, lower input bias current) in my KEI2010. It helped to reduce the ADC noise. Reading Kleinstein's post I am now curious whether OPA140 (or cheaper OPA141) would be even better choice. It also has 0.25uV p-p noise, but lower bias current and its noise.
I am looking for better solution instead of AD744 too (used as the integrator). I am thinking about ADA4627-1. It has three times less p-p noise (typ.) than AD744. If the integrator can't benefit from high slew rate of ADA4627-1 then again OPA140 may be a better option.
This brings me to DMM7510. Why? I think it uses a very similar configuration as Kleinstein suggested, i.e. 2xOPA140 (see attached picture).
-
The ADA4077 looks really good from the datasheet. In most aspects a step forward from the OP177/OPA177. The 2nd OP in the integrator is mainly important for the low frequency noise. I would expect especially the 1 Hz-25 Hz range to be important - lower frequencies are likely handled by the AZ mode and input switching anyway. With BJT based OPs the current noise is especially a problem, as the 1/f cross over for the current noise is usually relatively high - thus the noise matching impedance (voltage noise / current noise) gets lower at low frequencies. So a 0.2-0.3 pA /Sqrt(Hz) at 10 Hz is really good for the ADA4077 (compared to about 1 pA/Sqrt(Hz) for the OP177). Changing the OP to a faster type might also cause trouble, as too fast an OP here could make the compound integrator unstable. When comparing the voltage and current noise, the usual circuit should have an effective source impedance of the signal and 1 reference resistor in parallel. So with something like 50 K each a 0.2 pA noise would correspond to about 5 nV and thus less than the voltage noise. So I would not expect a big difference with the OPA140.
For the integrator OP, the important noise should be higher frequency noise, like the 1 MHz range. Low frequency errors would be compensated by the 2nd OP. A higher speed is only of limited use. As the OP is operated in it's linear range only, the slew rate parameter is usually not important, it is more like the GBW that matters. Even with a small integrator cap, the slew rate would normally be still rather low, more like in the 1V/µs range. The advantage of a faster OP at the integrator would be faster settling and thus the possibility to use a faster modulation scheme and thus a smaller capacitor. This could be an advantage if high resolution is wanted at high speed. However a higher GBW would not help much if the modulation and cap stay the same. Keep in mind that the AD744 uses external compensation - this might be different from unity gain compensation. So it is hard to tell how fast the AD744 is actually in that circuit.
Both OPA141 and ADA4627 would give a significant improvement in higher frequency noise over an AD744.
For the higher frequency noise it is the combination of the integrator and the following gain stage (slope amplifier) that matters. The often used NE5534 is still not that bad and changing that OP might influence the timing. A lower noise might help with the noise, if limited by the rundown phase. However the resolution might be limited by the timing resolution or similar. So the advantage of a lower noise OP in an existing circuit might be limited. The effect would be most visible at short integration times (e.g. 1 ms).
Interesting note on the DMM7510. I already was quite sure the ADC is not under the second box - that is most likely the input amplifier.
-
@Kleinstein, thank you for your inputs.
I will probably stay with ADA4077 as further improvement wouldn't be that big to justify risk of damaging the PCB during repeated desoldering.
I am still tempted to replace AD744 though. I need to perform new search since I overrated significance of slew rate parameter as you confirmed. Maybe ADA4625 would be even better than ADA4627...
As concerns the slope amplifier (NE5534), I tried to replace it with LT1037, but it was little bit worse then, so I put NE5534 back.
I agree it is probably the input amplifier instead of the ADC under the grey shield in DMM7510. The same approach is used in KEI2182 and KEI2010 (where the input buffer and MUX are shielded too).
-
The ADA4625 is a really low noise OP - but also take quite some current. To make full use of it one should also change the NE5534, as for the high frequency part these two work together. The LT1037 was a poor choice, because it's not unitiy gain stable. An OPA209 might work (if the input impedance is low enough) - it may need an extra cap to reduce the speed. Changing only the post amplification does not help, as the AD744 is much higher noise. In the ADC circuit, it depends also on other factors if lower high frequency noise really results in much lower overall noise.
-
Yes, ADA4625 is rather hungry if we are talking about supply current (Iq~4.0 mA), but AD744 takes 3.5 mA already. Still better than ADA4627 (Iq~7.0 mA!)
I know LT1037 is stable with gains of 5 or greater. In the slope amplifier, its gain is set to 6 in vicinity of zero-crossing (gain resistors 49k9 and 10k). I ran a simple simulation, didn't see any issue at first glance, so I tried it. As I said, the result was not a disaster, just slightly worse (~20%) than with NE5534.
Maybe LT1037 was too fast? NE5534 uses 47p compensation capacitor, which should give ~4V/us slew rate. I admit I don't get why high slew rate is an issue in this case...I should study some theory :)
I would remark I am quite happy with modifications I have already made. I managed to reduce noise from 0.55 uV rms to 0.31 uV rms (@ 10V range, 0V input, 10NPLC, 1024 samples).
-
Getting 310 nV_RMS at 10 PLC is already quite good, something around 100 nV/Sqrt(Hz) for 1 single conversion or 140 nV/sqrt(Hz) with AZ mode.
The expected noise from the ADA4077 would be about 0.3 pA/sqrt(Hz) times about 50 kOhm (depends on the ADC circuit) and twice the OPs noise at about 2-5 Hz, thus 2 times maybe 15 nV/sqrt(Hz). This would be total of maybe 35 nV/sqrt(Hz) and thus only a small fraction of the residual noise.
There are also other noise sources. One that is hard to avoid is the input resistors. Effectively one has the input and a reference path resistor in series. Thus possibly some 40-60nV/sqrt(Hz) from the resistors alone, thus about 1/4 the observed noise.
The effect of the higher frequency noise of the integrator and slope amplifier and thus likely the AD744 would depend on the integration time: it limits the accuracy the residual charge can be determined. It somewhat depends on the exact mode, but the more usual way would be that this noise contribution goes down with one over integration time. So it would be most important at high sampling rates. Chances are it would not matter very much at 10 PLC - especially if the 10 PLC are real single conversions and not averaging over shorter conversions. So comparing the noise at different PLC settings could give some clues on the noise sources.
For using the LT1037 it could be ringing that can be higher than with a well compensated NE5534. The noise of this OP is still small compared to the noise of the AD744. It is well possible the NE5534 will set the bandwidth for the comparator path - a faster OP would result in a higher BW and thus more noise seen by the comparator. The compensation not only sets the slew rate but also the bandwidth for the OP. If the ADC uses a slow rundown slope, I would not expect the slew rate to be relevant. I don't have an accurate way to calculate the noise from the higher frequency part of the integrator, but I would expect something like OP_s higher frequency noise for the integrator and post amplifier combined times the square root of the bandwidth (e.g. post amplification) and the time constant of the integrator (cap time resistor at the input path) to be the main factors. Replacing the AD744 with something lower noise might bring down that noise component by a factor of maybe 3. Reducing the BW is tricky as this might require longer delays and thus a slower rundown phase.
When building your own ADC, reducing the BW might be one option.
-
I looked at the specs of the Keithley 2010. They show the noise at 0.1 PLC nearly 8 times higher than with 1 PLC. This kind of suggests the noise from the rundown phase is a major contribution at 0.1 PLC, and already present with 1 PLC. However there is still a chance this is more like quantization noise and not the AD744.
The specs also suggest that the longest integration time directly supported might be 5 PLC and thus 10 PLC would be 2 readings at 5 PLC averaged. This makes sense since at some point the 1/f noise contribution (e.g. current noise from the OP177) would dominate over the noise from the rundown phase.
-
The most likely KEI2010 supports true (not averaged) 10 NPLC. It can be set only via GPIB/RS232 though. Supported range of values is 0.01-10.00. You can set e.g. 9.63 NPLC. I wonder why they chose slow rate to be 5 NPLC. I would prefer 10 NPLC as it is in KEI2000/2015 (they use the same ASIC to control A/D conversion).
I found an OPA140, which left after an old project. Couldn't resist and replaced AD744 with it :) The result? The noise was further reduced to 0.28 uV rms (it is the average from ten runs, 1024 samples taken in each run, conditions same as above). Next step is clear, I will try to upgrade the slope amplifier too. OPA209 suggested by Kleinstein (thanks!) looks really good...
-
Upgrading the slope amplifier would not give such a big advantage. A first and easier step could be changing the 47 K / 10 k resistors at the slope amplifier to maybe half (e.g. add another pair in parallel). A little extra capacitance in parallel to the higher resistor might help to bring back the BW to the correct value.
The 10 K resistor produces more noise than the NE5534 and OPA140 together. The OPA209 would only be better with reduced resistance, otherwise current noise would cause more noise. Anyway the NE5534 is already lower in noise than the OPA140 - so no real need to change the NE5534.
I won't expect a large effect of the fast OP on the noise at 10 PLC. The effect should be more pronounced for the shorter integration times. So it would be interesting to look at something like 1PLC and 0.1 PLC noise, before changing the resistors.
p.s.:
A remark on the integration times. There are two noise sources that change with the integration time: one is the 1/f noise of the "slow" OP (the OP177 in the original circuit) this noise gets higher for long integration in one piece. The second is the residual charge measurement (e.g. due to the integrator, slope amp, ..) - this gets higher at short integration. With long integration times one usually used the AZ mode, thus alternating between the signal and a zero. There is a point at which it is lower noise to use several conversions and average instead of a single long conversion. There is a good chance this point of the optimum integration time could be in the range of 1-5 PLC - this is especially true for modern DMMs with a focus on fast conversions.
-
One more thought on the resistor noise: making the 10K/47 K feedback circuit much lower impedance is limited, as more current will flow and this could lead to more "noise"/crap on the supply. One possible solution to avoid a much higher current and much of the resistor noise could be using 2 depletion mode FETs (e.g. JFETs) with a resistor in between in a kind of current limiting circuit - near zero crossing this can be low resistance (e.g. 1 K range). It is nonlinear, but this is not a problem, more like adding to the nonlinear function of the limiting diodes.
Attached is the suggested circuit for the inverting slope amp case, the non inverting is analog. The choice of JFETs also sets the resistor. A type with low threshold is likely preferred.
p.s.: The red curve shown the input current. Full scale is +-2.4 mA.
-
Happy New Year to everyone! :)
Interesting idea about feedback resistors and JFETs. I would rather not to change topology of the ADC circuitry in KEI2010 (prefer 1:1 replacement). Definitely inspiring for new designs though.
I performed more tests with various NPLC settings with my modified KEI2010:
NPLC test result specs
0.01 63 uV 135 uV
0.1 11 uV 11 uV
1 0.66 uV 1.4 uV
5 0.38 uV 1.2 uV
10 0.28 uV N/A
I am surprised there is no improvement at 0.1 NPLC at all. Otherwise I am pretty satisfied with results. It is worth to note I have made more modifications than I mentioned here. (I don't want to spam in this thread. I will rather enter a new post once I am finished with performance tests.)
I also tried to find out what slope amplifier is used in DMM7510. I would bet it is AD847J - as it can be seen (with some imagination :)) in attached picture stolen from Dave's teardown video. So, they used 2xOPA140 as a composite integrator, AD847J as a slope amplifier (with 49K9, 10K gain resistors) and LT1116 as a comparator. The last two are used in KEI2002 too, so not such surprise.
-
It is really odd to see not improvement in the 0.1 PLC case. Maybe one could look at a time series or histogram plot, to see if there is something special happening, like a special point of hitting a kind of idle tone and this way a point with poor DNL.
After changing something at the ADC it would be a good idea to at least do some DNL tests with histograms. The histogram might also show if there is even a chance to get better or if quantization limit might already be reached.
The improvement at 0.01 PLC with about a factor of 2 over the specs looks quite good. This is actually a little more than I would expect from changing from an 16 nV/Sqrt(Hz) OP to a 6 nV/Sqrt(Hz) OP with still the 10 K resistor (and thus 13 nV/sqrt(Hz) of noise). There is some extra noise gain due the input capacitance to ground, that might explain why the integrator OP is slightly more important than the slope amplifier and resistor. This noise gain might also explain why they can get away with an OP that is not unity gain stable. Also the specs are likely a bit conservative.
One might still change the 10K/47 K resistor pair to some lower value, but keep in mind it might also have negative effects due to more stress on the decoupling. The JFETs part was an idea to get a low impedance for low noise and still not so much more current it's not really changing the topology - it's just a nonlinear "resistor" replacement (or in parallel) for the 10 K. I can fully understand if you keep it this way.
Usually the better way to test such things would be a really self made ADC. I thought about an ADC design even before this thread. This kind of explains why I had some points at hand so fast. My concept is a little in between the 34401 and K2000 ADC, with an µC (AVR) for control. This could be good at intermediate integration times (e.g. 1 PLC), but with some limitations at the very short integration times. Limitations at long times are not an issue, as averaging is a real alternative - so I see no real need for a true 10 or 100 PLC mode, if resolution at 1 PLC is already high enough.
-
One might still change the 10K/47 K resistor pair to some lower value, but keep in mind it might also have negative effects due to more stress on the decoupling.
Excessive load on the output of an integrated operational amplifier will cause offset shifts and other problems due to self heating from the output transistors. This is what ultimately limits open loop gain and settling time and why higher noise OP-07 type amplifiers and lower power parts can achieve better precision than OP-27 type amplifiers and higher power parts which require a much lower impedance feedback network to take advantage of their lower noise. Using an external buffer to unload the amplifier output from its own feedback network and other loads largely if not completely solves this.
Precision operational amplifiers use a mirrored layout of the input differential pair (actually four transistors), the output transistors, and other functions to reduce thermal feedback but this only goes so far. George Erdi came up with this designing the uA725 at Fairchild in 1969 and then moved to PMI where he used the same design ideas for the OP-07 and its predecessors.
-
The Keithley 2010 uses a non inverting slope amplifier. So the extra current would come from the slope amplifier (NE5534), that is running rather hot anyway. The problem is more that the current would also flow through ground and this way could cause some trouble.
Somewhat sorry for confusing with showing the inverting version for a slope amplifier - in this case the current would actually come from the integrator, and loading the integrator could be a problem. I would not worry so much about thermal effects (as there is a second OP that takes care of the DC part anyway). However loading could change the open loop gain and add to AC supply currents.
Anyway for experiments around an multi slope ADC a own design would be much more suitable than a precious DMM. Especially with the Keithley meter there is also the somewhat odd way they do the AZ calculation that add low frequency noise - this can also make the interpretation of the readings more difficult.
-
Hi All,
Happy new year, and thank you for your many notes. I'm slowly understanding things better. In the attached schematic I've added a second opamp to the integrator which could be used to compensate for low frequency noise as suggested. All opamps are labelled as AD711s, but I would plan to try the various combinations suggested.
I've replaced the analog switches (DG4xxs) with JFETs. The Keithley 2001 appears to use JFETs driven by a LM339, and I've used the same scheme here. An example of the driver circuit is shown in the bottom left. Will this scheme work here? Which JFETs might be appropriate here?
Thanks again for all your help.
-
I personly don't like switching with JFETs very much. It's quite an effort needed to drive the gates. Fast switching and protection against excess gate current are kind of difficult to bring together. Switching at the negative side would also need a voltage lower than the negative ref. voltage, witch kind of limits the useful voltage range. The choice of p-channel JFETs is very limited. JFETs also tend to have quite a spread in properties.
I would not consider the ADC in the K2001 a good solution - OK to learn from, but not to copy. They still use MOSFETs for the fast switching for the main feedback.
Switching at the very input is odd - the FET towards ground should be behind the other one - otherwise it would shorten the input and leave to OPs input open. There usually is no need for the same magnitude slow slope both positive and negative.
The switch for the zero phase might show too much leakage - so it usually take 2 or even 3 switches combined and a series resistor. If the zero comes from behind the post amplifier, it will also correct for offset drift of that OP.
It is also odd to have switching for the reference current at both ends - the more usual way is using switches only at one side of the resistor. So either one reference resistor and switching at the +- Ref side or using 2 separate resistors for + and - Ref and use switches at the integrator. Switching at the integrator is kind of a little easier, as the level is near ground. It is also a good idea to have some balance in the switch resistance, which is easier, when switching is at the integrator side. However switching at the +- Ref side can be lower resistance, but this is usually with MOSFETs instead of JFETs.
-
Thanks for your comments Kleinstein. In the attached schematic, I've reverted back to the DG419.
Based on your preiovus notes, I feel I have a better understanding of opamp selection here. But the switching is less clear to me. I would guess the on resistance isn't very critical, as this can be corrected for with the zero compensation. Various keithley instruments use the SD5400, this doesn't appear to be generally available but the datasheet quotes "Low Interelectrode Capacitance and Leakage", and I'm assuming the capacitance of the device is important?
-
Keithley used the SD5400 for switching. These are 4 MOSFETs with separate substrate connection, which makes them somewhat similar to half a CMOS switch. AFAIK these chips tend to get obsolete. In addition they need the extra gate to control the 2 MOSFETs. Ready made SPDT CMOS switches are relatively similar and easier to use, though in theory the N-Channel FET only version might have a slight advantage of less controlling capacitance. Still I would consider the DG419 a reasonable replacement, as the ready made chips also include the gate drivers and make the circuit more compact. These switches also provide a reasonable break before make timing.
Though I am not so sure the DG419 is the best choice, as this is a rather high voltage version with thus more charge injection and internal capacitive coupling - there might be other alternatives with better parameters (e.g. max4053, ADG633). Even the 74HC4053 seem to work in the 34401. The on resistance can be important, but so does the change injection or more specific the fluctuations of the charge injection. One has to find a kind of balance between on resistance and charge injection. The on resistance is in series with the current setting resistors and can add quite a bit to the temperature coefficient. However most of that resistance can be balanced to compensate (in the 34401 they have a non operated switch in series just for compensation). This makes it attractive to have the 3 important switches in one chip and also use the same resistance for the reference and signal channels (R2=R3=R4). As the switch is keeping the input side at low voltage, there is no need for the switches to be made for a high operating voltage. Switches for lower voltage (e.g. 5 V or 12 V) often are better with charge injection.
There is no need for both polarities for the fine slope, one is enough. Having less switches at the integrator is attractive, as this reduces leakage and capacitance. I even think one can get away without an dedicated extra switch for the slow slope, if the two reference voltage are slightly different (e.g. +10 V and -11 V). When turning on both at the same time, this corresponds to a -1 V reference and thus a slower slope. For the coarse steps the relevant reference is the difference of the two ref voltages. Due to tolerances one can not rely on the two reference currents to be absolutely equal anyway and thus needs to consider different values anyway - which is easy as it only adds a small offset.
P.S.: one more point: when doing the switching at the integrator side, most of the meters have a ferrite bead or similar between switches and the integrator. This is likely to reduce the effect of charge spikes from charge injection. The exact function is still not clear to me, but it kind of makes sense.
-
Thanks Kleinstein,
I've made a first crack at a layout attached. The second fine slope is present, but I will remove it in a future revision. I've used DG419s and a DG417 for the integrator switch. Analog do a low on resistance version of the DG419 (2Ohms on resistance, ADG1419) in the same package. I'm wondering if this is worth trying out.
As you can probably see, I'm still a bit confused about the grounding. I've tried using star grounding for all the grounds, but I'm less clear on what should happen with opamps. I've therefore pulled all the negative opamp rails back to the same point too. But this is perhaps not necessary?
I still need to think about the integrator capacitor selection, it's laid out for something like a SMD NP0, but I should probably modify the layout so a through hole PP could be used too.
-
Grounding and similar layout parts are really a difficult part of the design, but it is likely important to get really good performance. I would not be so much concerned about DC shifts, as there will be an offset to zeroed out anyway. Howver anything that changes can be tricky and also those nasty switching spikes can be difficult. So good decoupling is likely needed, especially for the switches, but also for the OPs.
The OPs would rund for most of the part on a +-15 V or similar supply. So the first line of decoupling would be from the +15 to the -15 V at the OPs. For the critical parts (sensitive points, but also noisy ones) one might consider extra isolating impedance (small resistors or ferrites) towards the global power. However there also needs to be a coupling from the supply (usually the negative side) to ground.
I don't think very low resistance switches like the ADG1419 are a good idea. A low resistance comes at the price of more leakage, more charge injection (or at least fluctuations if there is good compensation) and also stronger supply spikes on switching. Quite often the low resistance parts are also slower. Leakage and change injection are a little less critical when switching at the reference side - so at that position lower resistance part might be acceptable. For switching at the integrator, it is more like looking for lower voltage parts like ADG633. There are also different requirements for the different switches - the fine slope and zero switch don't have to be low resistance at all.
Already the DG419 has quite some capacitance, which could be a problem with several of those switches.
-
Here is my suggestion for a rather simple multislope converter controlled by an µC (AVR Mega 8 or similar). The circuit is simplified by leaving out a few more obvious parts, like the supply and decoupling. A clean supply and good decoupling is likely very important though. The circuit is to a large part inspired by the HP34401 ADC and the more classical multi-slope ADCs like in the Keitley 2000, with rundown phase with fast and slow slope. In addition the µC internal ADC (e.g. 10 Bit) can be used to measure the residual voltage.
The part on the left is an amplifer for the reference voltages. Noted as +-12 V though the right value would be more like +11 V and -12 V, thus two intentionally slightly different values.
IC1 A and IC1 B are the two OPs for the integrator. The 4 inductors at the switches (74HC4053) are ferrite beads inspired by the 34401 design. Not sure they are actually needed of might want parallel resistors in the KOhms range. This would be a part to check with real hardware. There is no extra slow slope, but combining the two slightly different slopes should work as a slow slope as well. The three resistors (shown as 50 K) at the 4053 should be the main critical resistors in the ADC circuit. Using 3 resistors of same value should give reasonable good compensation for the on resistance in the 4053.
IC4 is working as a slope amplifier in inverting configuration. Using the JFETs Q1/Q2 is optional if rather low resistors are used for super low noise - not sure this is really woth it unless one would go for 8 digits. A first test could use just a resistor here. The inverting slope amplifier has the advantage that the output voltage range is limited to about +- 0.7 V around the ground / reference level. In addition there is little load to the ground / reference level. Here the reference level is set to about 1 V above ground by a divider. This allows to use the µC internal comparator to detect the crossing of the reference level.
As a kind of second amplification stage there is the OP IC6B as an inverting amplifier with an adjustable reference level. This level should be rather close (or identical) to the 1 V level used for IC4. This amplifier is supposed to be powered from 5 V just like the µC and amplifies the residual charge signal for the µC internal ADC. In addition the inversion is needed to get a hardware zero phase.
Q3 and Q4 (small N-MOS FETs - maybe other types, preferably small ones) are used as a switch for the zero signal. The two fets might be needed for good isolation for good precision. Depending on the mode of operation one might even get away without this HW zero path. R61 is used to add a little bit of negative voltage, to compensate for the shifted reference level used. The zero level would be at about 1/10 (set by R60/R61) of the -12 V reference and thus about 1.2 V (for the ADC) with the resistor values given.
Feedback during the runup phase will be via an extra comparator IC2. Comparison is towards a fraction of the input signal (at LSP1). The combination is also used in the 34401 and many other HP meters, though with using an inverted input signal added to the integrator output. Comparing to the input signal gives kind of a preview to the future integrator state. Due to this kind of preview, the speed of the comparator used for the feedback should not be that important - so chances are one can get away with the lower power 393 instead of the faster, but higher power LM311. Accuracy of FB during runup is not that critical anyway.
AFAIK the AVR µC does not use an internal PLL for it's clock. So I hope to get away without extra synchronization flipflops for the control signal. Depending on the µC used these might be a good idea (for the 2 reference signals). The control is separate to allow for using both refs at the same time.
The one point I am still not sure about is the shifted level for the slope amplifer. One drawback I get, is that the ground of the ADC is somewhat coupled to the µC ground for the µC internal ADC. It also needs quite a lot of extra resistors to shift levels. Maybe there is a better way ? I don't really like the idea of using something like a +-2.5 V supply for the µC, though it might be an option.
From the software side the AVR is fast enough to control the FB during runup. This is with SW in assembler and using the run time for the timing, which is kind of OK as the AVR has a predictable timing (no cache) and the software is not that complicated. Here it is more the integrator HW that sets the speed limit. I would prefer a rate slower than in the 34401, more like the K2000. It looks like the 34401 could use it's high frequency FB only at the price of a reduced input range and long neutral phases - however this adds quite some noise.
For the rundown phase the control by software (instead of dedicated HW) causes some extra delay on the order of 300 ns and thus similar to the delay due to the comparator. I don't think a slightly slower rundown phase should be a problem for a first test. When using the ADC for residual voltage, one might not even need the slow slope (except for super high resolution) and the hardware zero phase.
-
Thanks Kleinstein, the design looks really interesting! It will take me some time to understand it all.
Do you plan to do a layout of this too?
-
I have a layout ready for a first test board - just need to find time to make the board. It is just for a test and thus has a few air wires to be added.
I also did some minor changes in the circuit.
For the way of operation I am not really sure. I see 2 promising modes of operation. One in the a feedback with reading the comparator at a fixed time to choose between two feedback PWM patterns (like 5% pos and 95% negative, and the other way around). This is about what the 34401 seems to do. This system is the easier one and will be thus my first test.
The other option would be looking also at the time when the comparator changes level and this way get a finer control with many more PWM levels. The second option might give better FB, but it is also computational more demanding and thus can not run that fast.
The HW is rather similar the the 34401: SPDT switches at the integrator. The main differences are:
1) also controlling the signal channel, which is only used for compensation at the 34401.
So the ADC will be more classical multislope with a separate rundown phase.
2) using the combination of the both refs to get a fine slope. It is a little higher noise, but not significant, as the fine slope is used only for a short time. It is a rather simple idea so I am surprised I have not found this in the plans of commercial DMMs.
3) using the ADC to measure the voltage after rundown (instead of in the fly in the 34401) - this should give extra resolution and low noise. The µC has the ADC anyway and compared to the comparator the ADC has lower BW, which is good for low noise.
-
A short update:
I decided to go with a first test on a breadboard (the µC and UART interface is reusing an existing board) version first, with a slightly more simplified version. It uses no external comparator and thus the µC internal comparator for feed-back in the run-up phase too. I know this will lead to some INL/DNL errors due to DA of the integrating cap. However I see not reason an external comparator for a better run-up should not work - this one is not critcal for the final noise.
Anyway the ADC works reasonably, as far as I can tell so far. Despite of using only a µC clocked at 8 MHz the rundown can be quite fast: about 60 µs - even with some room for improvements. Currently it seem to be limited by mains hum - so hard to tell how much real noise. So far it's something like 1-5 ppm with a 18 ms integration in a multi-slope mode and something like a little better than 0.1 % in a dual slope more with 20 µs integration and 60 µs (+ another 40 µs for the µC internal ADC) rundown.
I still need to write some of the GND based part (PC) software and the test measurements to bring the different scales together so it is a little hard to tell how high the noise really is.
Edit:
Attached is a scope picture of the integrator waveform at 20µs/div (500 mV/div ?). The initial sharp rise is the fast "rund-down", followed by an overshoot with fast rundown in the other direction and than a slow rundown (going up) and the horizontal phase (reference off) for the ADC to sample. After that comes the beginning of the next multi-slop run-up that starts as a 100 kHz triangle in this case. So there is quite some overshoot due to delay of the comparator (and µC program), but still the rundown can be quite fast.
-
Hi Kleinstein,
Wow! Sounds like great progress! How do you plan to reduce the mains hum? Would you try integrating over a complete power cycle as a way to attack this?
I would love to see pictures of your build/layout.
Do you plan on eventually making the gerbers available?
-
The steps to reduce mains hum will be integrating over a full cycle (20 ms) and adding some extra shielding. I had a software bug that made it around 18 ms instead of 20 ms.
Sill better shielding is needed, as to understand the noise it also helps to do measurements with much shorter integration time - up to the point of dual slope mode with very short integration time. With the 1 nF integration cap I could go down to 20 µs integration - though at limited resolution.
Besides better shielding, the next step would be the special modes to measure the reference ratios. Currently I only get raw data, like number of run-up steps, µs of positive and negative reference and the ADC steps. So it takes three more steps to bring these 4 numbers together.
The step from run-up steps to µs of pos and neg reference is relatively easy, as this is a fixed integer number that can be determined from the software simulation. The next is getting the ratio of positive to negative reference from a special operation of the ADC - I have the code ready, just have to test it. For the ADC it might be enough to look at the noise, but for a faster and better value of the scale factor it would also need a special mode of operation.
I will make the layout available - but the current tests might give some changes to the circuit and the board might include something like an input amplifier.
So far the first point to change is that I have hardly a need for the hardware zero mode.
Attached is a picture of the circuit on the breadboard. Form right to left the Chips are:
OP07 to do inversion of the reference voltage (currently 5 V supply or the green LED)
74HC4053 to do the switching
OPA2134 (low noise audio JFET OP, 8 MHz GBW) for both OPs of the integrator
the integration cap is the small sytroflex one near the scope probe
OP27 used for slope amplification (slight overkill)
MCP6002 as final amplification for ADC (2. nd OP unused)
The white wire at the left is the output to the µCs ADC. The ribbon cable in the center top is the connection to a µC board with Mega48 µC.
The circuit is running at +-8 V and +5 V, as this are the supply I have at the breadboard.
-
A short note on progress:
The cal measurement to check the ratio of the positive and negative reference seems to work well and fast. So no need for long time stable resistors for the reference amplifier.
The Measurement for the µC internal ADC needs still a few tweaks - it runs through but the numbers still need to make sense.
Noise in the dual slope more is now down very much - good for about 14 bit resolution now. It looks like some DA effect is visible, but just a little barely at the noise level. It would take a modified SW to get a longer soak time to keep the cap charged for more than about 50 µs. So the polystyrene cap seems to be good enough.
For the board design I still have a few open points. One is the reference:
I guess I should include a reference on the ADC board. The LM399 is kind of simple, but it is more like long time stable and not really low noise. For the ADC test I would more prefer low noise but no need for long time stability. The long time value and the absolute scale would be due to measuring a reference through the normal input path anyway. My current idea would be something like 3 LM329 refs (essentially similar to LM399 but without the heater and a cheap plastic case and thus not long time stable). Having 3 refs in series and thus 21 V nominal voltage would reduce the number of critical resistors in the reference amplifiers a little, as there would be little amplification towards the about 25 V difference between the positive and negative reference.
Is there a simple way to to a compensation for the possibly large TC of the LM329 ? I am afraid that buying a few more looking for the 3 refs to compensate is not that practical - chances are a batch from one source would be all one way.
I am currently using normal slow onto-couplers for the UART and thus 9600 baud. This is just fast enough to send out the data from 20 ms integration in real time. Is there a value in faster transfer, e.g. for 1 ms integration time ? Even when doing the calculation in the µC it would be about 3-4 ms to send out 24 or 32 Bits.
-
Another update:
I got a first real test in dual slope (no FB during integrate) with putting together the 3 result parts (fast rundown, slow rundown and adc for the residual charge. For a first test I measured the discharge of a capacitor. The plot only shows the last end of the discharge, starting at -300. The y scale is in a kind of arbitray units (around 10 mV at the capacitor), the x scale is just the number of reading (about 15 ms apart). The right graph is a magnified version at the end.
The residual scattering still looks like it contains a kind of dominant frequency, so it is not only noise, but likely still some hum left.
-
Another update:
I got the multislope mode running - the main problem was a software error, that added noise noise during runup.
Considering the rather low reference voltage (around 3.5 V) and the not so perfect layout (breadboard) I am kind of surprised on how low the noise can get. Currently the standard deviation for a simulated AZ mode (taking the difference of 2 consecutive readings and thus the Allan variation for 1 time step) is around 2.4 µV with a full scale range of around 3 V. So it is good for 6 digits resolution. The direct readings don't show much extra LF noise and drift.
Chances are it gets better with a larger reference voltage: the resistor noise should go down with the square root of the increase in voltage, the noise contribution (relative to the range) of the OP would even go down linear.
I think it is now really time to make a board. The breadboard experiment still let to a slight change in the circuit (slope amplifier relative to GND and level shifting only after that).
Any idea for test that should be done with the breadboard version, before making a board ?
I am still unsure about the reference: I tend towards having a separate low noise reference with the ADC. For the long term there might be a second reference later (e.g. LM399) that would be used for the scale adjustment. However I am not so sure about what reference to use:
The LM399 is rather noisy (thus the idea of an extra reference).
An LTZ1000 is kind of expensive.
3 or 4 LM329 in series (the higher voltage makes 1 resistor less relevant) might be an option, but they could have a significant TC.
For the compensated zeners like 1N821 the noise data are kind of confusing me.
Any other good ideas for the reference ?
-
Yet another update:
With a small change in circuit and maybe a contribution from SW (better adjustment of the internal ADC scale) I could reduce the noise even further, now at slightly below 1 µV for the difference of two consecutive conversions (to eliminate the 1/f noise, just like an AZ mode would do it).
The possible effect of the SW change make me think about a possible noise contribution: The ADC is kind of free running in a sense that the conversion start with a slightly different charge in the integrator ( the range covered by the µC internal ADC). This could be seen as a kind of natural dithering, when averaging more conversions for longer integration time. If there would be significant DNL errors, especially intervals too small this dithering effect would cause extra noise. So using the argument the other way around, the relatively low noise - much of it can be accounted for - would also indicate that there should be no large DNL errors, at least not at the small range tested by the dithering.
Another result came from comparing two speeds of modulation during the run-up phase: There was very little difference in the noise. This means the switches (74HC4053) seem to contribute little to the noise - at least more frequent switching does not increase the noise. So chances are good one can get away with the 4053 switch (no need for ADG633 or max4053 - which seem to get hard to get anyway). Also jitter seem to be not a serious problem with the AVR. So chances are that is could work without the extra flipflops for synchronization.
For the board it is now the question if low costs, low power, linearity or low noise would be more important ?
For the OPs I kind of have the problem that for testing a DIP form factor would be nice, but the good OP options for the most critical OP (OPA141 and ADA4077) are not available in DIP (at least not easy).
-
Yet another update:
For the board it is now the question if low costs, low power, linearity or low noise would be more important ?
For the OPs I kind of have the problem that for testing a DIP form factor would be nice, but the good OP options for the most critical OP (OPA141 and ADA4077) are not available in DIP (at least not easy).
This is the least of the problems listed, really its a non-problem. Simply order smt parts in soic packages and use dip adapter boards if you want to have a proto socket. They are not hard to solder. People should move to surface mount as it isn't that hard outside of BGA and WCLSP.
Soic to dip:https://www.ebay.ca/itm/20PCS-SOP8-SO8-SOIC8-TO-DIP8-Interposer-board-pcb-Board-Adapter-Plate/310575279861?hash=item484fbaaef5:g:0XkAAOSwtfhYqoh0 (https://www.ebay.ca/itm/20PCS-SOP8-SO8-SOIC8-TO-DIP8-Interposer-board-pcb-Board-Adapter-Plate/310575279861?hash=item484fbaaef5:g:0XkAAOSwtfhYqoh0)
I vote for optimizing performance (linearity first then noise) other optimization can come after. Avidly watching your progress. cheers.
-
I did a test to see how much DA in the integration cap would influence the INL. As far as I understood it, one possible effect of DA would be an INL error, depending on how the run-up phase is working. So see the effect I had the idea of comparing two slightly different runup version with the same HW in an alternativ fashion. So there is one conversion with a slow rundup (24 µs modulation period) and one conversion with a faster run-up modulation (8.2 µs). Ideally those two versions would give the same result - however due to a slightly different integration time the scales are off a little, but not much. The idea is to compare the two methods. To get a better scaling I used he difference of the readings as a function of the reading of the "slow" mode. The idea behind this is that I expected INL errors due to DA to have a different dependence on the voltage for the two modulation methods.
To get a stronger effect, I also tried this measurement with a higher DA polyseter cap instead of the polystyrene cap used for the other tests.
On the scope some fast DA effect is visible (however hard to trigger - so no photo).
For a large part the measured curve looks really smooth. However there is a small wiggle in the curve just at the point when the slow mode passed 50% PWM - thus showing the worst DA effect. The worst case error is a little more than 0.5 units of the ADC, which corresponds to about 12 µV. With a range of about +-3 V this would be a +- 4 ppm local INL error. This would be a good number for a using a poor quality cap.
However now comes the odd thing: when doing the test with the much better PS type cap, the errors seems to be a nearly perfect copy, despite of a much lower expected (and observed one the scope) DA. So the error seems to come from something else than DA in the integration cap. Now these 4 ppm error are kind of a bad thing - though only very local, just a 1 mV range. A more normal DNL test might miss this. It is nor just an external disturbance - the data are from three runs passing the critical range.
The other result from these runs is that the noise seems to be not much worse with the faster modulation. So the switch is not yet critical for the noise. There seem to be some drift between the two modes of measurement. As they use the same HW, this is likely due to a drift in the charge injection, that is about 3 times more important in the fast mode.
Attached are curve for the difference in measured voltage in 2 modulation modes. Units are cycles of positive ref. which correspond to about 22 µV each. The curves a taken with a PS and PET integration cap.
-
I'm not sure at what voltage the kink in the ramp occurs or the present schematic, the parts and such but what came to my mind is cross-over distortion. Some op-amps have low output-stage bias current, almost Class B. Maybe try add a pullup or pulldown resistor to the op-amp's output, to force it more into Class A; only a few mA at most for low self-heating.
Most MCU's have a bit of clock-noise on their I/O pins, so I add 50-100R series resistors to roll off. Just don't want MHz getting into the analog section. The 4053 ABC control lines I would see as one path and add resistors there. I find ferrite beads only work if the impedances are similar i.e. 600Z ferrite bead does almost nothing into an op-amp's high-Z input, or a circuit section with high, say >10k impedance.
Audio Precision finding polystrene capacitors having less DA than mica parts. That surprised me, but that was at ppm levels.
-
Audio Precision finding polystrene capacitors having less DA than mica parts. That surprised me, but that was at ppm levels.
I thought mica didn't have particularly good DA, but I haven't tested one. Teflon is an order of magnitude better than any other capacitor I've tested, polystyrene, polypropylene or NP0 ceramic - and I've looked - to replace the integration capacitor in my HP 3455A. Some Russian teflon capacitors have been the best so far, but to get 80nF, they are _huge_.
One is best off designing the AtoD converter to maintain an average voltage of 0V on the integration capacitor - unlike the 3455A where you can get a 2 to 3 count error due to DA (particularly noticeable with auto-cal on).
-
I will likely use a polystyrene cap, as I have enough old ones to use. These caps are a few of the old parts that may actually be useful. Polystyrene caps are supposed to very good with DA, nearly as good as PTFE. Mica is not good for DA, more like similar to mylar / PET film caps. The good thing about mica is the long term stability, but this is not an issue here. There is a small effect of the capacitance value (because of the ADC used for residual charge), but something like 1% drift is not a problem and it can be adjusted internally. Anyway the test with the FKS type (PET) capacitor shows the ADC seems to be not that sensitive to DA. I had expected a much larger effect with some more ripples in the curve using the PET cap - but I could not see any extra errors. I can see the DA effect on the scope - right after the rundown, there is extra relaxation and it takes a few more 10's of µs for the voltage to settle. So maybe I did not see the DA effect as the waiting time before reading the value was long enough. The used SW version was not tuned for a fast rundown. So the good thing is that DA does not seem to be an issue, at least not from the rundown patterns. There might still be a longer time scale effect when switching between voltage levels.
Edit: The test confirmed the capacitive coupling: it got worse with more wire at the sensitive nodes and got better (though not much) with some improvised shielding.
I think I have a good idea where that trouble might be coming from: There is likely some parasitic coupling from the output of the slope amplifier to the reference inputs to the 4053. If the zero crossings of the integrator get in sync with switching the reference (this is possible at the point where the wiggle is) the errors can add up over nearly 1000 switching events. A test for this effect will be the next point.
I don't think the output stage of the OP is a problem. The OPA134 is an audio OP with a relatively high current consumption and likely an output stage with low corss-over distortion. In addition it is only the average current to cross zero, due to the modulation the current will be more like a square wave.
-
Today I tried a classical INL test with using a floating reference. As a don't have a good stable reference, I tried it with 2 new alkaline cells. Not to load the cells too much I added an OP07 as an input buffer. For the larger voltage range 2 green LED are use as a reference, and a slightly larger resistor for the signal input (around15 K for the input and 12.8 K for reference). So full scale is around 4.5 V for the slow modulation mode and around 4 V for the fast modulation mode.
It kind of worked, but there is quite a lot of drift, likely from the batteries. So the result is not really useful showing less than about 50 ppm INL in the 1.6 V + 1.6 V vs. 3.2 V test. There is a chance the switch did some transient shorts to the batteries - like no reliable break before make :-- .
However there where side result:
1) The green LEDs are a low noise reference: noise on a short is around 1 µV eff, and with the 3.x V batteries around 1.3 µV. So the LEDs are at least low noise :-+, though quite some TC.
2) with a larger voltage there is some DA effect visible from the average voltage in the integration cap. So the MKT cap did not work anymore - it left the working range of the µC internal ADC. Even with the PS cap there is some relaxation after rundown visible, about proportional to the voltage, and smaller (about half the size) with the faster modulation.
3) with the stationary voltage the slow an fast modulation mode produce slightly different results: the fast mode gives about 12 ppm lower reading. Not sure if this is INL or just a slightly off scale factor. Ideally the scale factor should be the same as the integration time is now identical. Chances are DA is causing this and much of the effect could be linear.
The test on the breadboard uses just one zero crossing comparator and thus a larger DA effect is expected compared to the final version using FB with a look ahead contribution from the signal, like many HP DMMs use.
The noise in the fast modulation mode is significant (about 2.5 times) higher than with the slower modulation. In the initial tests I did not notice the difference, but this was with a slightly slower version and more background. The much higher noise is kind off odd, as much of the noise in the slow more is expected to be due to the OP and thus only a small part due to switching. With the 3 times faster modulation (123 kHz compared to 41 kHz) I have expected a little higher noise, but only a factor of 3 (or square root of 3) for only the small part related to switching. So maybe some pulses get to short for the breadboard version.
-
Why not skipping the breadboard and doing some free wiring on a copper clad board? This way you can avoid the parasitics and learn about the critical points within the circuit. Thus you learn what to look for when laying out a printed circuit board.
-branadic-
-
I wonder if an extra low input bias current integrator would allow using a length of Teflon coaxial cable as an integration capacitor. RG-178 is 29 picofarads per foot so probably not less expensive than an actual Teflon capacitor.
-
One might use a coax cable as a capacitor, but depending on the design of the integrator the needed cap is in the 0.5 to maybe 2 nF range. Thus this would be 5 to 20 meters. So I don't think it is worth it.
As far as I can see the DA of the capacitor is not such a big problem. PTFE caps are supposed to be not that much better with DA than PS caps. Polystyrene caps are a little difficult to get, but not that much - at least in Germany one can still order them at something like 40 cents. One problem with DA is that good specs are rare and DA is more than just one number, it also has a time dependence. There are also options to reduce the DA effect with a better feedback during run-up. Currently I have the very simple version with just the zero crossing comparator, which is known to be not that good. I had paned at least to use a second comparator with a mixture of the input signal - this would especially reduce the slow DA effect due to the average voltage during run-up. The next better step would be using a kind of fast, low resolution ADC to get a little more info for a better runup - accuracy would not be critical already 2 or 3 comparators could give better zero finding.
The other way to fight DA is using a fast modulation - however this makes coupling (see below) more critical.
The more tricky part so far is more like (capacitive and via supply) coupling from the slope amplifier, comparator and digital control lines to the integrator and reference current sources. With a little shielding it is visible on the breadboard, but not that bad anymore. I would expect only that one point with a 50% PWM during run-up to be really critical - that would be a rather narrow known range (around 0.1% of the range). A few other points are just visible for the breadboard version, but I doubt is would be with a reasonable layout.
Currently I am surprised how good the slower mode works, the faster modulation mode still has some odd points, like working most of the times, but something like one out of 10 readings (not a constant frequency) is off by about 2 ppm in addition to the normal noise. Without those out-layers the noise looks similar. So chances are the switches and digital jitter is not a problem.
-
PTFE was definitely better in my tests. I posted the graphs I got from Bob Pease's DA test circuit here:
https://www.eevblog.com/forum/testgear/hp-3455a-last-digit-jitter-in-hi-res-auto-cal-mode/msg967855/#msg967855 (https://www.eevblog.com/forum/testgear/hp-3455a-last-digit-jitter-in-hi-res-auto-cal-mode/msg967855/#msg967855)
And from later in that thread (my/original capacitor refer to the integration capacitor from my 3455A):
Now, as far as absorption is concerned, my capacitor is about the same as a good regular polypropylene capacitor. I did't post the picture, but a pair of WIMA MKP 4 capacitors (33 and 47nF in parallel, http://www.wima.com/EN/mkp4.htm (http://www.wima.com/EN/mkp4.htm)) gave a similar curve to the original capacitor and an 80nF polystyrene capacitor was a little worse.
The MKP capacitor datasheet claimed low DA.
I was running my test with Pease's circuit running with a frequency and duty cycle similar to what the 3455A AtoD converter uses, so it's possible that the teflon cap isn't so much better at a different frequency/duty cycle.
-
I always found that qualifying capacitors yielded quite a variation in dielectric absorption and leakage between different types naturally but also between lots of the same capacitor. I never had Teflon capacitors to test though.
Polystyrene has an annoyingly low maximum temperature.
-
Especially at the low end DA can vary between caps. One factor might be humidity inside the cap. So far I am quite happy with the PS cap. I can see a slight effect of DA even with the low DA PS capacitor, but so far it is more like a small effect and I don't see a really viable option for a lower DA cap than the PS ones. If I really look fine at the data one can see some "drift" / relaxation after the rundown phase, that is slightly different depending on the runup phase (likely the last pattern) - but so far this is in the 10 ppb range. So this would be something to correct if more than 8 digits are called for.
For the ADC it is more about keeping the charge small, so that less DA can build up. Worst case I would consider numerical correction of the effect of the last pattern.
-
Have you tried compensating dieelctric absorption as shown in "Understand capacitor soakage to optimize analog systems" (http://www.datasheetarchive.com/files/national/htm/nsc03883.htm)
(http://www.datasheetarchive.com/files/national/image/nsc01029.gif)
-branadic-
-
I have not tried the DA compensation and will likely not use analog compensation anyway. So far DA is visible, but it is not clear if it will really cause severe INL problems. Chances are that most of the effect of DA will be a slightly modified scale factor and thus not a real issue. As far as I see there are three parts of DA effecting the ADC: one is kind of the slow part that comes from the average voltage during one conversion. This to a large part would give a scale error and maybe some after effect when changing between voltages. Here the first step is to make this voltage small, by using a second comparator for the run-up. I am not so sure how good it works, but this should give a pretty good reduction.
The second part would be the change in average charge with feedback pattern. Depending on the voltage the average charge will change a little. Here it helps to make the feedback faster and maybe use a better feedback algorithm, e.g. by using more than one comparator or maybe even an ADC during run-up. I might try 2 comparators later as a kind of 1.5 bit flash ADC. I did a crude initial test for this effect by comparing the two run-up modes (see earlier post). To my surprise the difference was pretty constant over most of the range, even with a mylar cap. I would expect this DA contribution to change with feedback mode and thus should show up in the difference between the two modes.
The faster mode still shows some odd extra noise (those 10% of points that are off), that i don't understand. This kind of makes the comparison more difficult. In addition there is some drift between the two mode - likely due to charge injection changing with temperature or supply voltage. So I may have to repeat the comparison with two intentionally slower modes - so less background and more DA effects expected.
Finally there is an effect from the very last part of the feedback pattern. It looks like that the very last part of the run-up phase has a minute effect. I read the residual charge after rundown twice with some 100 µs in between and for this time a change in voltage by about 1-4 ADC steps or about 20-80 µV for the capacitor is visible, depending on the run-up pattern, likely from a change in the last part, as i only saw like 2 cases. As the 100 µs waiting time is already more than the runup step size, I would not expect much more change with longer waiting. These 1-4 ADC steps are not very much (still well below noise for the 20 ms conversion) and may be better corrected numerical than in analog HW.
I guess I should somehow record the last part the the feedback for debugging.
DA might be one of the effects limiting the linearity. So it is kind of important. The best choice of modulation frequency depends on the DA and this way it effects the speed needed for the integrator and µC. The current tests are still a bit slower than the HP34401 design.. The 34401 design for some reason uses a very fast modulation and limits the useful range - likely to make this work with the slow integrator. I am not sure the high modulation frequency is because of DA, it could also be because of the ADC used to measure the residual charge without a rundown.
So despite the possibly fast integrator (higher BW OPs) I would not go for such a fast modulation, unless there really is a problem with DA. I would more like hope to improve on the feedback mode to keep the charge small. As I don't care very much about the fast conversion modes like < 1 ms, I also don't care very much about the slightly faster rundown that is possible with less charge to start with. For a 20 ms conversion I think some 120 µs for the rundown (without the second ADC conversion currently used) should be fast enough, and some of this is avoidable by reducing the comparator overshoot and a faster µC clock.
-
Any news on your topic?
-branadic-
-
I am still at the project. I had a layout nearly ready - only to find out that I ignored a type of capacitive coupling and had about the worst possible layout for that. To reduce it I had to redo the layout more or less from start.
I am still little unsure about the reference - will use 3 LM329 (in series) for a first test. I know the LM329 is not that great with TC and not the very lowest noise. It is still possible to use low noise zeners (e.g. 1N825) in the same layout.
With a little luck I get a board ready this week.
-
@Kleinstein: any new results with your design?
-
Hi,
I've restarted work on my design. I have my board working in a basic dual slope configuration currently, and am slowly working my way through various issues. You can find my notes here:
http://41j.com/blog/2018/12/multislope-adc-bring-up-dual-slope/ (http://41j.com/blog/2018/12/multislope-adc-bring-up-dual-slope/)
I'm currently trying to understand why I'm seeing such a big difference between the positive and negative slope speed. Thoughts and suggestions on how I should proceed in testing/evaluating issues are most welcome.
-
The board looks nice - my design is still on the breadboard and using a low supply.
For the circuit I am surprised not to see diodes in the output amplifier to limit the output amplitude. The AVR usually does not like a full +-10 V signal at the comparator. The normal way is to have 2 antiparallel diodes parallel to the feedback resistor. This works even better of the amplifier at the output is inverting.
For the different gains in positive an negative direction I have no good idea. However I am a little surprised with the code. With ARUDINO C++ / C code it would be difficult to get an accurate timing. At least there are chances that delay may change a little if the compiler version changes, as the same C code not always gives the same machine code output. So it might help to at least have the conversion part in ASM. However this can not explain the rather large difference positive to negative. The separate codes for positive and negative direction cause some discontinuity at zero, just near the zero readings from an AZ mode.
For high resolution it is normally a good idea to do the final integration from one direction only. This avoids different scale factors and an delay / offset of the comparator and slope amplifier would only add an offset.
The way I do it is the following: first always integrate up (at least 1-2µs, until the right sign is reached), than down til zero crossing and than slow up. So it is always the same sequence, just different times. One no longer needs a slow down unless one wants an additional very slow down as a last step.
Of cause one would still need to solve the different slope problem - not sure if this is more like a hardware problem or a software one. One could check the timing in the simulator.
To get the exact ratio of the up and down slope it could be a good idea to use the ADC circuit to also measure the ratio (e.g. in a special test mode).
-
For the circuit I am surprised not to see diodes in the output amplifier to limit the output amplitude. The AVR usually does not like a full +-10 V signal at the comparator.
No, it doesn't like it. I have a couple of dead Arduinos now. :) I'm currently using fractional gain on the output amplifier. I think I might want to move to a bipolar external ADC at some point. It might be useful for debugging if nothing else.
However I am a little surprised with the code. With ARUDINO C++ / C code it would be difficult to get an accurate timing. At least there are chances that delay may change a little if the compiler version changes, as the same C code not always gives the same machine code output. So it might help to at least have the conversion part in ASM.
I agree. From previously experience, the overhead of even digitalWrite's is reasonably high, so the timing will not be accurate (but should be consistent I think). I will need to rewrite this.
However this can not explain the rather large difference positive to negative. The separate codes for positive and negative direction cause some discontinuity at zero, just near the zero readings from an AZ mode.
I cleaned the board in an ultrasonic cleaner, and then sat it in IPA for 30mins under agitation. This seems to have almost completed cleared up the slope differences. The flux I like (AMTECH NC-559-V2-TF) seems relatively low resistance. I previously had issues on this board with residual flux under the switches throwing measurements off as well. I wonder if I quit using this flux on these kinds of boards...
Anyway the current measurements as attached (and I've updated the blog post).
-
For the signal send to the comparator one can relatively easy limit the signal in an inverting amplifier: just have two additional diodes back to back in in the feedback. This way the output is between some -0.8 and +0.8 V, still with a steep slope around the zero crossing. With a simple divider towards 5 V (e.g. 5 K and 22 K) the signal would be in a range suitable for the arduino internal comparator. This is the way I use it. An alternative would be using an external comparator (e.g. LM311).
For debugging I prefer the scope over reading with the µC. Though reading with the µC internal ADC can also help. Here a divider can help to bring the signal in the right range and avoid damaging the µC.
Even under the arduino environment one can directly write to the IO ports to avoid the extra delay from digitalWrite. For the beginning it is not that bad, as it only adds a fixed time delay - though at least consistent with the same program. The extra delay makes the use of the slow slope a little more difficult, as the added delay means there would be quite some time for the slow slope to make up the delay. So the slow slope should not be that much slower (maybe around a factor of 10). Still if there are some 5 µs lost in the reaction time this would be some 50 µs lost to make it up at -1/10 the slope.
For the program the possibly tricky part can be that "IF (x ==0)" and "IF (x > 0)" may take a different time. Also for 16 bit numbers some operations may take a different time depending on the value. Getting code with a well defined run time is one of the few cases where assembler programming has a real advantage - in C one would at least need lots of testing (e.g. in the simulator) on the actual timing. For a first low speed, less accurate version it may still work in C.
If possible I would such an conductive flux for sensitive parts.
-
Small update. I attempted to rebuild the board using all ADG1419s. This did not work well. After reset the integration capacitor had a tendency to swing negative. Before (very slowly over 60s as before) drifting back to a positive value. I put this down to higher charge injection, does this seem correct?
The ADG1419 datasheet does not list charge injection. Can this be calculated from other parameters? The Vishay, and Maxim DG419s do, as do some other Analog parts. This leads me to believe that charge injection may not be well controlled in the ADG1419, and it might not be an ideal part for my application.
I'm thinking about building a board, just for measuring charge injection to test various parts and improve my understanding.
-
For switching at the integrator the CMOS switches should not be very low resistance. So the ADG1419 are not a good choice. Usually charge injection goes up about like 1/R at a given voltage rating. So a high charge injection is very likely. The charge injection depends on the voltage level at the switch and the value near ground is close to optimum.
I use just simple 74HC4053 - except for missing tight the leakage specs they are quite suitable. They are reasonable fast and thus suggest good jitter specs and 3 switches in a case is very convenient to the 3 main paths trough 1 chip. I consider the on resistance about the right value.
For leakage one might need to check before use and maybe select a good one - the typical specs are OK, it is just that they don't test them very much for such a cheap part. I get a net charge injection for an ON/OF cycle of about 1 pC.
AFAIK the Fluke 8846 DMM also use HC4053.
-
PF2019!
I've been trying to understand how the multislope works. Because of lack of parts I've done a simple simulation for the run-up phase. My understanding so far is following (an Example only):
1. I created 1000 chunks, 20us each, such it fits into 20ms
2. after resetting the integration Cap the logic is switching the VrefP and VrefN based on the comparator's output such it tracks the integrator around the zero (at 20us comp_output sampling period)
3. The binary counter (the top pane green indicator) shows the number of crossings through zero.
With 0V input I get something like 470 counts (runup zero crossings), With +10V and -10V I get ~250counts. The counts to input voltage dependency is V shaped therefore. Is that something I may expect or I miss something fundamental here?
-
The simulation is about what one should expect - at least at the very basic level. To get better accuracy there should be extra provisions to keep the number of switching events constant.
In a simple (though good) case the ref switches follow a sequence where the reference is
1) fixed positive
2) positive or negative depending on 1 comparator reading
3) fixed negative
4) positive or negative depending on 1 comparator reading
The relevant number is not counting zero crossings, but the time the references are active (e.g. counting positive phased for step 2 and 4 in the example above).
-
::)
By replacing a piece of wire I've been now counting the positive charge. My chunk of charge is 20us*I_ref and the total number of chunks is 1000 (=20ms).
With
10V inp I get 250
0V inp I get 501
-10V inp I get 749Looks much better :)
Thanks!
-
..To get better accuracy there should be extra provisions to keep the number of switching events constant..
I think this scheme (a pwm like modulation) would be something you refer to.
The Vcomp transition from 1 to 0 - that is something I cope with. When compared to zero I get usually problems - Vintegr moves somewhere off for reasonable Ri,p,n, Tx and C values and when sweeping from -10 to 10V Vinp.
-
There are different possible schemes to get a constant number of switching events. The picture seems to have used a continuous PWM like sequence. It looks like 1 transition is simply by time. The other maybe from the zero crossing of the integrator with some delay.
How, and how accurate this is done during the run-up is not important, as the errors don't add up. A more crude or noisy control would only increase the excursions of the integrator a little. This can effect the average voltage of the integrator and thus the effect of dielectric absorption. However normally the modulation frequency is high enough (e.g. > 10 kHz) to not make his an issue even with a simple control scheme.
During run-up it's important to sum up the correct times for the references - so the reference switches should be in sync with a clock and not directly driven from the comparator.
The VCOMP signal is not the comparator, so not sure about this signal source or use.
The scheme I had described is a little different, with no fixed transitions, but fixed states. Each Cycle has only 4 possible sequences, 1 dominant positive one dominant negative and 2 mixed, half and half. This corresponds to 2 readings taken from the comparator.
The continuous PWM way can have a slight advantage, but is more difficult to implement. The for step case is more like simple.
-
..The scheme I had described is a little different, with no fixed transitions, but fixed states. Each Cycle has only 4 possible sequences, 1 dominant positive one dominant negative and 2 mixed, half and half. This corresponds to 2 readings taken from the comparator..
Could you point us to a simple picture with the cycle, plz?
-
The modulation scheme I described is from the US5200752 patent.
In short form this a 4 step cycle:
1. fixed reference at positive for a short time (e.g. 2 µs) and read the comparator at the integrator output
2. depending on the comparator reading before chose positive or negative reference for a fixed time (e.g. 20 µs)
3. like step 1, but with negative reference
4. like step 2
The reference setting is changing from pos to neg either between steps 1 and 2 or between 2 and 3 .
The reference setting is changing from neg to pos either between steps 3 and 4 or between 4 and 1 .
Attached is a simulated (spread sheet) curve. The blocks mark the beginning of the steps mentioned above. The rundown phase has the steps in short sequence.
-
Your scheme solves the issue with none-constant number of P and N switching. But the number of constant duration P and N phases is discrete and rather low, therefore the "runup resolution" is low (you count the number of those discrete phases).
My scheme above with "continuous pwm" during the runup has constant number of switching, and, the P/N is none-discrete in each sample period.
When the P or N "on" time will gate a 50MHz oscillator (an example) and will count its clock I may get for example 450000/450000 counts with Vin=0V and with 50us sampling period in the 20ms integration time frame (and maybe 50000/850000 with 10V, etc.)..
-
I know that the run-up resolution is limited. However in my view resolution is not the important point for the run-up phase. The first important point is the worst case charge at the end of run-up, which influences the length of the rundown phase. A second, related point is the needed integration capacitance which corresponds to the worst case charge in between. A smaller capacitance might lead to less noise for short integration times. For short integration times the noise is often limited by higher frequency noise of the integrator and amplifier behind, and this gets better with a smaller capacitor.
However to longer integration times the integrated low frequency noise takes over. So there is a limited use in reducing the capacitance very much. Depending on the details of the integrator and rest of the circuit something like < 1-10 nF for the cap would be nice to have the cross over at less than 20 ms. A smaller cap could still help with very fast conversions, but it also needs a faster amplifier in the integrator.
The continuous PWM type feedback can give a lower charge if the control is well made. Something like a factor of about 2 for the maximum charge and a little more (with a BW limited input signal) for the final charge. However the simple feedback directly from the comparator and a fixed time for the other transition (this is similar to the Adcmt 6581 DMM) is not really better than the simple 4 phase system. I think the 2 methods are about equal quality and similar effort. It would need a more advanced PWM feedback (e.g. using a fast ADC or the comparator timing) to get the slight advantage.
There is absolutely no need to use a very fast clock during run-up. It not about fine steps, but knowing the steps well. So 10 µs steps are fine as long as the length is accurate (e.g. to some 0.1-1 ns). It only adds about 1 time step to the rundown time, that usually is more in the 100-500 µs range anyway. The main resolution comes from rundown. Here higher clock can help - though there are limits to how fast the comparator is or should be.
-
The "continuous pwm" in my picture is intended for runup only. The worst case residual charge for run-down will be -10 or +10V.
The run-down will be the next process and a business as usual.
Imagine a simple DIY ADC with following spec:
1. run-up phase duration 20ms (50Hz suppression)
2. number of fixed steps in the run-up is 1000, each step is 20us
3. each runup step starts with VrefP (P) "on" and it is "PWM", where P/N ratio varies inside the step (in my picture the step is the period between T1 and T2 for example)
4. the number of P and N switchings in the runup is constant
5. total runup charge measurement: when the Vref P or N is active ("on"), it gates a "P" or "N" 20bits long binary counter, and the counter counts a 50MHz clock -> that way it measures the total runup P and N duration (the charge) with a 20ns resolution (1 million total counts in 20ms)
6. after the 20ms runup finishes the run-down phase starts, with whatever strategy you want (ie 16-20bit fast SAR as a "residue ADC", multislope, or other known approaches)
7. the run-down phase duration max 19ms
8. max ADC measurements per second: 25
With Ri, Rp, Rn around 20-50k and the integration cap=3n3-6n8 you may fit inside the 20us runup steps.
The resolution of runup: 16+ bits
The resolution of rundown: 14+ bits.
:phew:
-
For the run-up resolution the counter clock is not relevant. The step size to set the resolution is the time it needs to get the worst case residual charge. So if the runup is using time intervals of 10 µs to set the references, the step size is usually this time. So the resolution is more like 20 ms / 10 µs = 2000 steps or some 11 Bits.
For the rundown the resolution depends on the method used. In the simple case of a single speed rundown with a comparator the resolution could be something like 10 µs (the step size from the run-up) divided by the timing resolution (e.g. 50 ns with a 20 MHz clock). So the simple rundown would than have some 10 µs / 50 ns = 200 Steps (near 8 bit). So in total it would be near 19 Bits (plus sign).
Here it is not really relevant what accuracy the run-up has - the total resolution til after the fast rundown is integration time (minus fixed part) divided by the timing resolution for the rundown. So something like 20 ms / 50 ns = 400,000 steps. A different value for the run-up steps only moves resolution between the 2 phases. Longer Integration would give higher resolution. The timing resolution is limited by the comparator, not just the clock.
A way to higher resolution in a slower slope to get a higher resolution without a super fast and thus high bandwidth and thus higher noise comparator. A 2 nd slope lower by a factor of 16 could add another 4 bits. A 50 ns timing resolution is already quite optimistic for the fast slope and even more for the slower slope(s). The BW and thus timing resolution may need to be a compromise between a short rundown and low noise. So the gain in actual resolution from the slower slope(s) can be lower, as the slower slopes may need a reduced BW.
If a residue ADC is used, its useful resolution is limited, as the scale factor depends on the integrating capacitor and absolute value of the resistors. So the gain uncertainty can limit the useful resolution, depending on how and when the scale factor is calibrated.
The time for the rundown phase in the typical better DMMs is more like 100 µs - 2 ms, usually no need for more time. This time also includes a zero phase to discharge the integrator. So with 20 ms integration there can be something like 48-49 readings per second or with an auto zero mode some 24 readings per second. Many DMMs also need more than 20 ms for there full resolution, though it can help against 1/f noise to only use 20 ms. So the resolution at 20 ms can be a relevant target, even though the full resolution might still need averaging of several of those short readings.
-
Thus do you say that knowing the charge budget coming from references during the run-up phase with, say, 100x better resolution, plays no role?
-
One still has to know the charge budget during run-up very accurate, but one does not need a fine resolution setting the charge. So10 µs quantization is good enough, if those steps are know to something like 0.1 ns.
A coarse quantization only effects the time needed for the rundown phase and indirectly the required size of the integration capacitor.
-
Assuming "ideal" components (switches, references, comparator, integrator) and ideal precision/accuracy with any timings in runup (talking here runup only), and having two results from runup (in both cases the runup is 20ms long and all components are identical):
A. Pcharge/Ncharge = 674/326
B. Pcharge/Ncharge = 67443/32557
From what you wrote above the B has none benefit (compared to A) for the final result?
-
Just the higher resolution of the numbers has no direct benefit, as it is not about resolution, but accuracy of the actual time.
A finer quantization during run-up can have a slight advantage in getting a slightly lower final charge, if the feedback algorithm is good. But it's more about the algorithm not the quantization. A lower charge would allow a slightly faster rundown.
If done in a good way the continuous feedback could have an advantage that it could get away with a slower (AFAIK up to factor of 2) modulation. So I am still open to a better feedback alternative.
Maybe I have a look at the continuous feedback option again - not for more resolution, but to avoid coincidence of zero crossing and reference switching. My standing here so far is that the simple fixed time + comparator (like ADCMT6581) way is likely not better than the simple step way and the better feedback I have in mind is a little slow and needs scary complicated ASM software.
-
Here is a complete simulation of a Run-Up phase of a simple DIY Multislope integrating ADC built from junkbox parts. Intended for people who want to play with something more complex than blinking an LED and who want to learn.
The Runup is 20ms long, with 1000 fixed steps @20us.
The integrator is composite one, with slope amplifier and fast comparator.
There are also 3 counters - for VrefP, VrefN and Runup_Clk events.
In the below example the input voltage is a sine wave 4Vpp, at 4V DC.
The simulation itself runs till 20ms, exactly.
You may measure the residual voltage at the end of Runup phase therefore.
The sequences and timings are provided by various voltage sources and by a simple CMOS logic. Timing is considered precise.
The ADC strategy is to sample the comparator output @20us periods, and to switch the VrefP and VrefN references as required. The number of VrefP and VrefN switchings is not constant, but 1000 in total.
This is not a continuous pwm Runup, nor any high-end related stuff, but rather a wiki-like one example intended for hobby experimenters.
With the below ready example you should get VrefP=321 and VrefN=679 at the runup end. With Vinput=4V with no added sine wave you should get the same (as the 500Hz sine wave cancels out during integration).
With a -10V Vinput you may get VrefP=955 and VrefN=45, and vice versa with 10V at its input.
With Vinput=0V (input shorted) you should get VrefP=504 and VrefN=496.
The 3 voltages in the upper pane do represent the event counters, at the end of the simulation you may go with the cursors to the very end of the timescale and read out the counters and residual voltage values.
Enclosed is the .asc source and .plt file.
Worked with LTspice latest, and the Bordodynov library for some parts used. The parts were chosen as an example only. You may experiment with better parts when models are available.
Note:
1. Before you start to mess with different parts, R/C values and timings, try to run the stuff to get familiar with it.
2. Not all models of op-amps and switches work fine. Feel free to experiment.
3. The V1 schematics is rather complex, the simulation speed is about 30us/sec with a mainstream 2 core notebook. So take a nap.
4. You will get around 750MB of data (waveforms) with the example.
Provided as-is.
-
It's an interesting way of simulating more digital stuff. The simulation looks valid.
However a constant number of reference switching events is kind of a requirement to get good accuracy:
I get something like 2 pC of charge injection from a pos/neg/pos cycle for the reference switches. With a reference current of some 300 µA the 2 pC correspond to an equivalent timing error of some 6 ns or some 0.3 ppm of error for a difference of 1 switching cycle. The DG419 are relatively low resistance and may thus have even more charge injection.
So I don't think the suggested feedback method would really work.
If one does not want to program in ASM one could still use an µC to control the feedback and use 2 (+1 for the input) external flipflops to synchronize the reference switching to a constant clock (e.g. 200 kHz from the µCs timer). This way slight timing errors in from the program would not matter.
-
And here is a Basic version, with minimum parts. It cannot be done simpler, afaik.
The simulation speed is about twice the above version.
Btw, I've seen an ADC in hardware (in situ), in this Basic configuration (better parts used) which claims 6.5digits.. Simple rundown phase used.
-
Nice topic :) ;)
-
And here is a Basic version, with minimum parts. It cannot be done simpler, afaik.
The simulation speed is about twice the above version.
Btw, I've seen an ADC in hardware (in situ), in this Basic configuration (better parts used) which claims 6.5digits.. Simple rundown phase used.
The implementation looks simple for a discrete parts solution or in the spice simulation. There are a few possible simplifications: e.g. using a single chip with 3 SPDT shwitches (e.g. 74HC4053). The logic part could also be done by a CPLD or µC. So the HW side could use less chips.
My current favorite is using a µC - a little similar to the early MS-ADCs, but with a modern faster µC in a single chip instead of a slow CPU plus support.
One can get high resolution even with a simple rundown, if the integration time is long enough. If an AZ OP is used in the integrator the useful integration time is no longer limited by 1/f noise. As an extreme the Solartron 7081 goes up to 8 digits without a slow slope, though only after some 50 seconds. The circuit is not a classical MS ADC, but more like a continuous integrating ADC. However a classical MS ADC build in a similar way could perform similar.
Still I don't think using an AZ OP and very long integration is the modern way to go, as they are relatively noisy and with computer readout there is also value in good resolution at shorter times (e.g. 1-10 PLC).
-
.. There are a few possible simplifications: e.g. using a single chip with 3 SPDT shwitches (e.g. 74HC4053). The logic part could also be done by a CPLD or µC. So the HW side could use less chips.
My current favorite is using a µC - a little similar to the early MS-ADCs, but with a modern faster µC in a single chip instead of a slow CPU plus support..
The max voltage with 74HC4053 is +/-5V, afaik. That limits the part a bit.
I think nobody will mess with uC in the inguard logic today. A complete logic with counters and serial output (opto isolated) fits into a smallest fpga or mid cpld (iCE40, or similar). The verilog exercise is a weekend project for most today's talented builders with 6++ digits ambitions.. :)
-
If used to switch at the integrator input the +-5 supply limit of the HC4053 is not a problem. The signal switched is essentially at ground level (+- maybe 50 mV from transients) and even during turn on or errors the worst case current from a higher voltage is limited to some 0.2 - 0.5 mA.
There are some DMMs that use the HC4053: the HP34401 and the Fluke8845/6.
I know that modern designs seem to prefer CPLD or FPGA over µC. However from the noise problems a single chip µC should not be that much different from a FPGA. It kind of depends on the experience whether one prefers Verilog over hard core ASM. I personally prefer ASM -though I know it gets tricky if a 8 bit µC is no longer enough, as the faster ones tend to be not that predictable in the timing.
-
I made this multislope runup (+simple rundown) integrating ADC. It has full scale range +-14V, with resolution up to tens of microvolts. Least significant digit is rather stable.
Inguard control logic is in single EPM240 CPLD, configuration written in Verilog. CPLD also contains UART for sending the output results via single wire. On the second picture you can see complete setup, taking measurement of CPLD power rail. Power supply is the big block with metallic standoffs providing floating supply for ADC and blue digital board, containing optocoupler for galvanic separation from ADC and PIC18F47K40 to convert ADC counts into voltage values.
This is just feasibility study; I'm working on more refined voltmeter project at the moment.
-
Here is a RunUp simulation of the Basic ADC which could fit above Jaromir's POC design well (concept with typical R/C/timing values, not the identical parts and detailed schematics).
It works nice with perfect runup results (see the comments in the schematics).
The OPA134 model does not work well, therefore I've been using the LT1022A instead.
Also I have replaced my Version1/2 DG419 switches with the MAX4659 models I found in my LTspice junkbox.
The simulation speed is now 10x of the previous one.
Fyi - the ADC's Vinput=5V DC with 2Vpp 500Hz sine on it returns 150 counts :).
-
It's only a small detail and may not effect the simulation: the switch for the input signal should be wired like the reference channels.
@jaromir:
The board looks nice. I find it a little odd to have the resistor for the input to the integrator at 200 K. This is rather high impedance and twice the resistance at the references. With equal resistors one would have a smaller input range, but also better compensation of the switch resistance.
-
It's only a small detail and may not effect the simulation: the switch for the input signal should be wired like the reference channels.
Ok, thanks, fixed. Same results.
Vinput[V] VrefP Vresidual[mV]
-----------------------------------------
14 60 -84.724598
10.001 100 -111.18542
10 100 -65.6633
9.999 100 -20.195641
5 150 -41.385211 5VDC+2Vpp_500Hz
5 150 -41.934181
1 190 -22.446172
0.1 199 -18.161997
0.01 200 -457.83404
0.001 200 -49.337398
0 200 -1.#INDV (-580.12284µV closest)
-0.001 200 28.80118
-0.01 200 437.25276
-0.1 201 -2.7407967 << simul slow down
-1 210 2.2517985
-5 250 22.25494
-5 250 22.35401 5VDC+2Vpp_500Hz
-9.999 300 2.6997826
-10 300 48.327059
-10.001 300 93.820557
-14 340 69.571078Values taken from the plot.
VrefP + VrefN = 400
-
@Jaromir: While reading the metrology section it seems to me even the vacuum filled caps are crap when used in the integrating ADC. Did you try with different types/materials in your prototype design?
-
A good point of the multi-slope run-up it that it reduces the effect of the capacitor quality. The usual candidates for good caps are PP (polypropylene), PS caps and NP0/C0G ceramic. With sufficient fast modulation during the run-up, these caps should be well good enough. There is a thread about the ADCMT6581 DMM. Even for 8.5 digits it gets away with a PP capacitor and only some 5 kHz of modulation and thus a 20 nF integration cap. I would consider this about the limit where you have to start worry about DA.
In my test setup I also tried polyester caps: it still kind of worked with some limitations. The effect of dielectric absorption gets clearly visible on the scope as quite some drift after the run-down. However the tolerance in my case could be in part due to the special way of operation, that is more tolerant to DA than the normal run-down. This was for test purpose to get an idea how the DA caused error would look like.
So I see no real need to look for better caps. In the < 20 nF range all 3 types of good capacitors are readily available.
DA would be a problem only if very slow modulation (e.g. < 5 kHz) is aimed for. Even than there would be the option to use an accurate feedback algorithm to keep the average voltage about constant. This should suppress much of the DA effect (at least the slow part). Anyway a large integration cap has a disadvantage when it comes to noise and is thus not that attractive.
-
I was curious about DA, so I made simple DA checker, or perhaps more DA experimenting tool.
It consists of two low leakage JFET switches, amplifier with low leakage opamp, plus MCU to switch the JFETs on and off; in order to charge the capacitor to 10V, then briefly discharge it to zero and then leave floating. Opamp amplifier allows observing the capacitor voltage during all phases, especially at the floating one. I abused MAX232 as JFET gate driver.
Attached are pictures of my setup, along with two measurement scope screenshots - one is grey PP capacitor, another one is soviet teflon type. Yellow trace is voltage on capacitor, blue trace is the same, with 10x amplification (plus notice different vertical scale). The voltage rise after discharge is effect of DA, very obvious on PP type, not much significant on PTFE type.
The differences are quite obvious; I tried a few more capacitors, the best were (in this order) teflon, polyester, polypropylene, polyphenylene-sulphide, NP0 ceramic. Worst were electrolytic, high capacitance ceramic were not much better.
Also, I tried different capacitors in my ADC setup. Capacitors with worse DA appeared to provide worse INL; but I have to recheck this again after I finish second version of my ADC.
-
Very similar results on capacitor DA to those I got and posted here:
https://www.eevblog.com/forum/testgear/hp-3455a-last-digit-jitter-in-hi-res-auto-cal-mode/msg967855/#msg967855 (https://www.eevblog.com/forum/testgear/hp-3455a-last-digit-jitter-in-hi-res-auto-cal-mode/msg967855/#msg967855)
-
Hi all,
In order to improve my understanding I've been reading over the Keithley 2002 ADC schematics (originally from TiN). I've written up my notes here:
http://41j.com/blog/2019/01/notes-on-the-keithley-2002-adc (http://41j.com/blog/2019/01/notes-on-the-keithley-2002-adc)
Most grateful for any further insights, or corrections. From what I can tell the 2002 uses current sources of ~+/- 450uA derived from the 7V reference. These are switched through the SD5400 into the integrator. This appears to be a dual slope ADC (rather than multislope).
The SD5400 in the 2002 seems to be driven by TTL input (5V). This limits it's range somewhat, but I guess this doesn't matter with 450uA and what I assume presents as a relatively low impedance load?
-
The Keithley 2002 uses current source, but it still it a multi-slope ADC. The current sources instead of simple resistors are just an attempt to reduce errors from not so ideal switches and the integrator input voltage. The second advantage is that the the switch resistance has little to no effect.
In addition to the 450 µA current sources there is another smaller current source of some 5 µA. It is always active, but can still be used as a single slower slope for the rundown and only adds a small offset for the rest of the time. In this respect the ADC is rather similar to the K2000, that also uses a single fixed current.
So the ADC is multislope, though only with a single rather slow slope. So it is not that fast.
The switches are at the integrator input and thus only see a small voltage, e.g. from non ideal transient behavior of the integrator.
As the on Resistance does not matter with current sources, there is no need to use a higher gate voltage.
-
In addition to the 450 µA current sources there is another smaller current source of some 5 µA. It is always active, but can still be used as a single slower slope for the rundown and only adds a small offset for the rest of the time.
Thank you for the clarification! I guess this is U815/Q807 I hadn't previously understood the purpose of this. Makes a lot more sense to me now!
-
Follow-up to my post from january 13th:
I made some more progress - respin the ADC PCBs, designed input amplifier (for now just follower/signal buffer, with autozero capability), digital board with MSP430 MCU, display/keyboard with MC9S08 MCU*, power supply with a few floating rails to achieve full isolation between "earthed" logic portion** and floating ADC/input amp. Floating part is enclosed in separate metal box.
It is designed as six and half digit DVM, though it displays seven and half digits just to see how stable it is. I'll truncate it to six and half digits later.
The wiring is still quite messy, it's work in progress. I need to perform proper calibration and characterization.
* I deliberately chose MSP430 and MC9S08, because I never made any real projects with those. It was fun to discover peculiarities of those.
** There is USB and RS232 connection options, plus bluetooth module - it is not used by now, not sure if it was good idea, after all.
-
What is that metal can in the input amp?
Isn't cutting off last few digits a difficult task? :)
-
The metal can part is just 78M05 to generate local 5V for VL pin of CMOS switch.
Normal 78L05 or million of other ways of creating 5V bias would do the job too, but I have a lot of 78M05 in TO39.
Cutting of last digit can be done in may ways. In case software solution isn't available or desirable, strategically placed piece of duct tape will do the job just fine.
-
Ah, Metrology grade 78M05 :P
I've been using the duct tape too, currently covered last 5 digits on my DMM..
-
I finally got a board made for the ADC already shown in response #48 (breadboard version). The circuit has not changes that much - slightly different OPs are used (not all better) and an oscillator instead of just a crystal. So the hardware is a little similar to the 34401, with HC4053 switches, the normal 2 OP integrator and using the µC internal ADC for the residual charge instead of a reset. The main differences to the 34401 are that I added a rundown phase, the µC internal ADC is used with the integrator in hold mode and the references are a little asymmetric. The control is via the µC and thus no ASIC (2 OPs instead).
The board also includes a MUX and buffer (place on the board, but currently still external with 4 wires going there) for the input to get zero and reference readings to compensate for zero-point and gain drift.
The board is a slightly odd mixture of THT and SMD parts, and some optional / alternative parts not used.
Some of the bodged in parts (the high value resistors and the large yellow cap) at the bottom are for measuring the average integrator voltage to check for DA contributions to INL - so not part of the normal ADC. With suitable caps there is not much DA effect visible. At least for this circuit I see no need very very special caps: just PS or the NP0 caps I tested were well good enough.
The software is working so far (for most parts). For some reason the PCB version is still a little more noisy than the bread board version was. This could be in part due to a not that optimal OP (TLE2021) that sets the integrator noise, but I suspect some switching related noise too.
Due to a changed software most of the earlier linearity problems are gone.
-
@ Jaromir and Kleinstein: Hopefully you will soon share your experience, results and designs such we may help with improvements.
"6 digits ADC for everyone" could be an interesting and feasible project :)
-
I will share the design soon.
Currently I still have a few minor problems (trouble with the UART, noise that is 2-3 times higher than it should be and some dependence on the load to the 5 V). Currently the noise is at about 1.5 µV RMS for the auto zero measurement - so already not that bad.
-
I found out that not all HC4053 behave the same. The 74HC4053 (2 samples) from ST I initially used caused higher noise than CD74HC4053 from TI and an old HEF4053. Nominally specs are very close for the HC4053 parts - so it may need some testing there. My guess is things like the break before make time or charge injection could be different. However I am not sure other batches will behave similar.
With the CD74HC4053 the noise is now down to a little below 1 µV RMS.
-
Have you tested MAX4053 for comparison?
-branadic-
-
I have so far only tested 74HC4053 (2 units) from ST, CD74HC4053 from Ti (1x, the one I used ) and HEF4053 from Phillips. I will probably also order an max4053 and 74LVC4053. However I am not sure which parameter is really important. The main advantage of the max4053 is the better leakage specs - however leakage likely is not an important parameter. The lower speed (still faster than HEF4053) could be more important than lower leakage. It is more like charge injection and the supply current peaks I am worried about. The HEF4053 / CD4053 might be a little on the slow and high on resistance side this could effect jitter and the gain stability.
For some reason HP in the 34401 schematics has a ferrite bead at the VSS pin (negative supply). To me this looks odd as the voltage at this pin should not go much higher than some 200 mV even in peaks. I have tried this in combination with a capacitor to the VDD pin but it did not have much effect. The next try would be without the capacitor.
The noise is still a little higher with the faster modulation. So there is a chance things can get better with an even slower modulation (needs a larger integration cap). However I would prefer to understand and solve the root cause.
-
According to AoEv3 HP uses the NXP version of the 74HC4053 in the 34401A. It may or may not perform any better than the other manufacturer's versions but it would be a good starting point. It's possible that the ferrite beads in the 34401A may be matched specifically to the NXP HC4053's characteristics.
Any idea why HP included the 42.2K R440 to pull down the 100K Vin signal just before the switches but didn't bother with the 30K +/- reference signals? The 100K/42.2K node is at virtual ground when the switch is operated so the only impact of R440 would be due to the input offset voltage of the integrator, but I would have thought that would be negligable?
(https://www.eevblog.com/forum/projects/multislope-design/?action=dlattach;attach=741483)
-
100 K in parallel with 42.2k gives 30 K impedance. It helps to have the same resistance at the inputs to the 4053 as in this case the TC of the external resistance plus the switch resistance is matched. The same resistance is also important for the effect of residual input voltage at the integrator. This is not only the offset, but there is also a dynamic component. Some of the errors only contribute if the impedance changes with reference setting. So resistance matching can help with linearity.
They could have started with 30 K and a smaller (e.g. 3.5 V) range - possibly the design started with this. The 34401 was designed to follow the 3457. It is just the time when going from 3 V full scale to 10 V fulls scale. In my opinion using this combination at the input is one of the weaker points and adds to the noise.
The way the 34401 ADC works with continuous integration and no rundown it needs a rather high resolution from the run-up
and thus the fast modulation (essentially the same as in the 3458). However due to the slower integrator settling it requires relatively long fixed phases and thus a reduced voltage range.
Using 100 K for the signal input helps to keep the self heating low and thus helps with linearity.
A looked the datasheets for the switches and found that there seem to be quite some internal capacitance inside the HC4053 - the power dissipation capacitance is quite high (some 38 pF). This suggests quite some current peak on switching. In this respect the 74LV4053 looks quite promising (only 5.3 pF). Though not in the specs I found, changes are charge injection and supply spikes could be quite good. Anyway my idea is to get the needed extra resolution from an extra rundown phase so that I can use a considerably slower (e.g. a factor of about 10) modulation, so that the switches should be less critical.
I think L401 and L402 are there to reduce charge injection by getting a higher impedance at the 4053. They also keep the very sharp peak from the integrator and ground.
L403 is a little odd: it's at the negative supply. Normally one would prefer a well decoupled supply for a chip. The extra impedance at the negative supply pin could effect the charge injection and switching speed. I would expect a slightly slower switching and possibly less charge injection.
-
Have you tested MAX4053 for comparison?
Hello,
I would use the MAX4053A (lower leakage current).
Besides this the MAX4053A showed lowest INL against CD4051 and 74HC4051 in a 32 Bit resolution PWM-Divider.
With best regards
Andreas
-
100 K in parallel with 42.2k gives 30 K impedance. It helps to have the same resistance at the inputs to the 4053 as in this case the TC of the external resistance plus the switch resistance is matched.
The 42.2K is grounded at both ends when the switch is closed. If the integrator is perfect, there will be no offset, static or dynamic, so no current will flow in the 42.2K thus its TC and resistance will be irrelevant.
A good spot that the 100K//42.2K is 30K - which surely is to match the switching time of all three switches - since they will all have nearly identical capacitance (and inductance).
The same resistance is also important for the effect of residual input voltage at the integrator. This is not only the offset, but there is also a dynamic component. Some of the errors only contribute if the impedance changes with reference setting. So resistance matching can help with linearity.
Sorry don't get why the source impedance seen by the integrator is relevant so long as the integrator is operating within its limits. I agree that any offset voltage, so long as it remains constant, will cause an offset to the output which will be calibrated out. As far as I am aware, the 3458A ADC integrator doesn't see constant input resistance during its operation.
They could have started with 30 K and a smaller (e.g. 3.5 V) range - possibly the design started with this. The 34401 was designed to follow the 3457. It is just the time when going from 3 V full scale to 10 V fulls scale. In my opinion using this combination at the input is one of the weaker points and adds to the noise.
Noiser because of the higher thermal noise of the 100k resistor compared to 30k? It's an interesting thought that they simply scaled the 3457 design; it would be interesting to understand how the ratio of the reference currents to the Vin current affects the linearity.
The way the 34401 ADC works with continuous integration and no rundown it needs a rather high resolution from the run-up and thus the fast modulation (essentially the same as in the 3458). However due to the slower integrator settling it requires relatively long fixed phases and thus a reduced voltage range.
It doesn't have a rundown because it uses an ADC to measure the residual integrator charge, getting approx 3 digits from the run up (@ 1 NPLC) and 3 digits from the residual. From the service manual page 101:
Each analog-to-digital conversion begins when the multimeter is
triggered. The ADC starts by clearing the integrator slope count in U501.
At the end of the integration period, the slope count is latched.
The slope count provides the most significant bits of the input voltage
conversion. The least significant bits are converted by the on chip ADC
of CPU U500.
Anyway my idea is to get the needed extra resolution from an extra rundown phase so that I can use a considerably slower (e.g. a factor of about 10) modulation, so that the switches should be less critical.
A rundown will be slower than using an ADC to get the residual, but the linearity may be slightly better as the linearity of the integrator capacitor's voltage/residual charge relationship may be affected by dielectric absorbtion. Always returning the charge to zero should largely eliminate DA errors.
-
The same impedance for all 3 inputs is importance mainly because of the switch resistance (some 70 Ohms for the HC4053) and the related high TC. So this is essentially the reason for the 42 K.
The 3458 uses different switches for the signal and references and thus could use different resistors for the input and the reference. The way it is used there (40 K for the references and 50 K for the input) is still not a solution I like - using also 50 K for the references and 25% higher reference level would have given lower noise.
The other point is the same resistance for the positive and negative reference. This helps that an non ideal zero voltage at the input of the integrator will produce the same offset. An non ideal input can come from the integrator offset (less critical as constant), but also from the settling after the references change. A simple 1 OP integrator would have some kind of square wave of a few mV (depending on the OPs GBW and the integration cap). With the 2 OP integrator like used in the 34401 and most modern designs, reference switching causes a peak (some 10 mV range) that recovers to near zero after some 0.2 to 2 µS (depending on the speed of the OPs). The problem is if these peaks have a slower contribution (that may not be visible on the scope) that extends to possibly the next phase. The peaks are OK if the integrator is at always the same impedance at the input. The constant impedance is only important in the run-up phase - the rundown phase has relatively few transitions in a fixed sequence (but variable timing) is thus less critical.
I don't think the 34401 ADC is more like an upscaled 3457. It is quite different in many points - the 3457 ADC actually works with 10 V full scale and the amplifier adds gain. It only looks a little like they may had a 3 V full scale range in mind. Changing the 100 K at the input to 30 K would make the ADC from the 34401 a perfectly good ADC for a 3 V full scale range, like it was common in the old days.
Using 100 K to a 10 V full scale range and 42 K to me looks like an after-though to make the ADC work with 10 V full scale, at the price of more noise. The resistors can actually be a major noise source for a good ADC. For the integrator with it's current input it may help to look at it as current noise. In this view the 42 K does not contribute to the signal but adds current noise. The 30 K resistors from the reference also add quite some current noise.
Using the auxiliary ADC to measure the voltage at the integrator output is fast, but it also has a limited resolution. The scale of the ADC depends on the integrator resistors and the capacitor. Especially the capacitor tends to be not that stable, so that a frequent check of the scale would be needed. So getting 3 digits from the residual charge is already on the optimistic side - it's more like 4 digits from the run-up and 2.5 digits from the µC internal ADC. The resolution from the run-up part is limited by the speed of the modulation. The very fast modulation of the 34401 has 2 negative consequences:
1) the fixed phases in the run-up patterns reduce the input range. In the 34401 only some +-3.5 V (if they would use 30 K from the input) of the +-10 V reference range are actually used. Slower modulation (like in the 3457, K2000) could have allowed some +-8 V or so.
2) It needs a fast integrator. For the 34401 they choose the OP27 for the precision OP in the integrator, probably for speed reasons. For the noise performance the OP27 is a poor choice here, because of the current noise. Other older precision OPs (e.g. LT1001, OP177) are likely too slow.
A rundown phase needs some time, but not necessarily that much. The 3457 needs some 150 µs, my solution currently uses some 200 µs (120 µs with a single ADC conversion), with a possible speed up to the 50 µs range. So for a 20 ms conversion the time lost is not that relevant. For best precision one would likely anyway alternate between a zero and a signal reading anyway. So some time is anyway lost for the input switching and the continuous integrating version needs extra settling to start with.
The rundown, especially in the classical form does not help much with DA. It avoids possible nonlinearity of the capacitor - however most capacitors tend to be very linear (e.g. better than many resistors). The DA of the capacitors usually has 2 contributions: a fast one from dipole orientation, that happens on the 1-10µs scale and a slow one more from internal surface charges on the 1-10 seconds scale. The fast DA part can be a slight problem with the classical rundown with a comparator to stop the slope. However already a slower slope phase would reduce the fast effect as the last 10 µs before stop don't vary that much. An additional waiting time (some 10 µs) can further reduce this fast effect.
The slow DA mainly hides some charge proportional to the average integrator voltage and gives it back later. This effect does not depend much on the details of the ADC. It can be effected by the way the references a controlled during run-up, as this effects the average voltage. The nice point is that the expected DA related error would follow that average voltage curve, so one has a clear signature to look for. Attached is a curve for the average integrator voltage measured for an input voltage range around the center (horizontal units about 42 µV).
A fast modulation and thus less charge stored in the capacitor is very effective suppressing DA. With a reasonable good capacitor DA should not be an issue for a modulation faster than about 20 kHz. The ADT6581 DMM (8 digits) even gets away with only 5 kHz and not very good feedback during run-up.
-
I think L401 and L402 are there to reduce charge injection by getting a higher impedance at the 4053. They also keep the very sharp peak from the integrator and ground.
L403 is a little odd: it's at the negative supply. Normally one would prefer a well decoupled supply for a chip.
The ferrite beads - sometimes it is enough to place a ferrite bead (or a small ferrite bar) close to a pcb track and watch the signal on the oscope's screen. You may see the noise or peaks lowers. Then you may insert the bead into the track in the final design.
-
I think L401 and L402 are there to reduce charge injection by getting a higher impedance at the 4053. They also keep the very sharp peak from the integrator and ground.
L403 is a little odd: it's at the negative supply. Normally one would prefer a well decoupled supply for a chip.
The ferrite beads - sometimes it is enough to place a ferrite bead (or a small ferrite bar) close to a pcb track and watch the signal on the oscope's screen. You may see the noise or peaks lowers. Then you may insert the bead into the track in the final design.
The spikes the ferrite beads are working on are still quite small. In addition they a superimposed by the "normal" charge injection and integrator input settling. So there is quite some normal background and and a little very fast bit (e.g. the rising edge) the ferrite beads are likely supposed to improve on. At least with my analog scope I see no chance to watch the effect live. If at all it would need a good DSO and averaging over many cycles (high resolution, box integration mode) in a special test mode of the circuit (for a stable signal). So far for me the ferrites are something like trying different version on pure chance and compare the outcome.
As the circuit is not very fast, I don't think just a ferrite on a trace would have enough effect. Anyway, there is not much trace to work on anyway.
My current problem are odd (likely high frequency) signals that cause odd EMI like effects. E.g. the reading changes quite a bit with a wire attached to the 5 V supply of the µC or ground at different points of the circuit. The problem is that the RF junk is likely to small to see on the scope. Likely the xx4053 emits some RF spikes that cause funny effects from resonances somewhere in the circuit or attached wires. I think the 4053 is the source, as the effects get much better with the slower HEF4053 version. I have some new xx4053, ferrites and better OPs ordered.
-
Order a small ferrite toroid (ie smallest dia amidon 43 material), wind 10 windings for the oscope probe, cut the trace and go with a piece of wire through the toroid.
-
The 74LV4053 works really well: considerably less EMI problems - this supports my suspicion the 4053 was the source, as the LV version has much smaller supply current peaks and is still a little faster. The noise also went down a little compared to the HC4053 or HEF4053 versions. It's now at some 750 nV RMS and no longer much higher than what I know noise sources for (some 600 - 650 nV) with the current OPs in the circuit.
After changing the critical OP I will likely also test the max4053, but I think the LV4053 has the advantage of not having the extra level shift stage,as it has no extra negative supply pin and using lower voltage FETs.
@IMO I may try the current probe suggesting in a few days. It looks a plausible way to check for current peaks, when one is anyway using bodge wires or THT ferrites for the supply. However the ferrite does have some effect. So chances are, I would not use a scope probe, but more like 50 Ohms termination at the scope.
-
Sure the secondary winding feeding a coax w/ 50ohm termination is the right way to do it. It transforms the 50ohm down to a fraction of an ohm of the bodge wire.
I've acquired today 3 various 4053 versions, ordered another 2 incl Maxim. A pity it is a mix of PDIPs, SOICs and TSSOPs.
While reading 4053 DSs - the 74LV.. versions usually work with 0-5V only..
Nexperia LV:
..the analog inputs/outputs (nY0, nY1 and nZ) can swing between VCC as a positive limit and VEE as a negative limit. VCC-VEE may not exceed 6 V. For operation as a digital multiplexer/demultiplexer, VEE is connected to GND (typically ground). VEE and VSS are the supply voltage connections for the switch..
The only versions with >10V working area are the CD/HEF/MAX4053 and 74HC4053 afaik..
-
..
While reading 4053 DSs - the 74LV.. versions usually work with 0-5V only..
I know the LV version is for 0 and up to 5 V only. The 74HC and HEF4053 were also only powered from 0 and 5 V. I tried some -0.7 V, but it did not really help, though from some typical curves the charge injection could be lower.
Die switches in the 34401 and my ADC are used in a kind of current steering way near zero voltage. So the actual voltage at the switches is about in the +-50 mV range - this is OK with a 0 and 5 V supply. If really needed I could shift the voltage to some +100 mV, but it would make things a little more complicated.
The main difference between the LV and HC version is that there is no separate negative supply, that could go up to some -5 V, and thus no internal level shifter circuit. This and the likely smaller structure FETs for only some 6 V allows for less (about 1/7 ) current consumption and thus less current at the supply.
-
I think it is not about powering the chip's logic (all are 0-5V Vcc except the old CDs) but the voltage at the switches. The voltages at the switches with LV have to stay within 0..Vcc, with the others they could go from say -7V to +7V (while their logic is powered 0..5Vcc only).
-
I think it is not about powering the chip's logic (all are 0-5V Vcc except the old CDs) but the voltage at the switches. The voltages at the switches with LV have to stay within 0..Vcc, with the others they could go from say -7V to +7V (while their logic is powered 0..5Vcc only).
The voltage at the switches has to stay within about -200 mV to Vcc+200 mV. A little more than the supply is allowed, more would cause extra leakage. Only with a large current (some 100 mA for the LV) beyond some 600 mV could cause real trouble (e.g. latch up). So the maybe -50 mV in peaks are not a problem to cause significant leakage. The worst case current is limited to some 300 µA and thus also safe.
The 74HC4053 in the 34401 is also only powered from 0 and 5 V, even with a ferrite at pin7 and thus possible positive peaks of some 50 mV there, so that the input can be even more negative relative to pin7. The HC4053 can tolerate a negative voltage only to a little below the level at pin 7. With pin 7 tied to ground the limits are about the same as with the LV version.
-
The only versions with >10V working area are the CD/HEF/MAX4053 and 74HC4053 afaik..
And the MAX4053A is the only one with integrated level shifters.
On the other devices you have to add external ones if working outside +/-5V in a 5V logic system.
with best regards
Andreas
-
I changes the "low frequency" OP in the integrator from the not so good TLE2021 to an OPA1641. It did some improvement in the noise and the settling of the integrator also got faster as expected from a faster OP.
Noise went down to the 700 nV RMS range for the simple difference of 2 readings (simple RMS). Still a little high than hoped for and the noise source I know off would cause, but I consider this good enough for the time being.
The MAX4053 did not give an improvement, at least not with an extra ferrite at pin 7. It even looks like charge injection seen as the difference between the slow and fast modulation mode is a little higher. For the current circuit the I got the best results from the 74LV4053 Next best was the CD74HC4053 from Ti, HEF4053, max4053 and 74HC4053 from ST with a ferrite were about same level and the worst HC4053 (ST) without a ferrite was worst. As the LV4053 works good - I see no need for a further search.
It still looks like the fast modulation gives more noise, so I might test a slower modulation. The downsides of slow modulation are a stronger DA effect (should be OK down to some 20 kHz), a little longer rundown and more noise from reading the residual charge due to the larger integration cap - this would lead to more noise for short integration (e.g. < 5 ms). So one might have to find a compromise between good performance at >= 20 ms integration and 0.1-1 ms integration, which would be about the lower limit.
After noise, now comes the tricky part in building a high resolution ADC: that is linearity. My earlier version had a DNL problem just in the middle of the range, but I found a solution for this. So far it looks like the DNL is good. My crude test is looking at a slow discharge/charging of a large capacitor. Even if not a perfect exponential it should give a smooth curve and the deviation from a local fit is a first indication for local linearity.
A funny side note: The 5 V regulator use is an ET7805 (ESTEK)- it looks like this regulator is surprising low noise, but rather poor TC. So its a nice test source for a slowly drifting voltage :-DD.
Attached is a plot of the 5 V supply drifting. RMS noise is about 2 µV RMS for the difference to a straight line (about 0.01 to 25 Hz). This includes noise of the LM329 reference of the ADC circuit.
-
@Jaromir: While comparing recent posts w/ DIY designs the way you have done it - MCU+CPLD/FPGA - is the way..
I've been thinking on an MCU embedded into the FPGA (ie. my iCE40UP5k with embedded Forth+SDADC), but using a cheapo popular 32bitter - like the BPill's stm32f103, and a small CPLD/FPGA (where the bitstream could be stored in the MCU's memory) is something I would highly consider.
For example stm32f103 (or a clone) + iCE40LP384, the combo for <$4.
Except the low cost and much higher performance (than atmegaxx or msp430) the important point is the C and Verilog are easy to read and write (unlike the Forth or ASM) by a vast majority of DIY community.. And for the above combo there are open source dev tools available as well.
The analog part - I've been pretty curious about which solution from the recent DIY postings (Jaromir vs. Kleinstein) gives a better results at the lowest digits..
PS: I've thrown your verilog as-is into the IceCube2 and with iCE40LP384 32pin qfn $2 FPGA:
Final Design Statistics
Number of LUTs : 283
Number of DFFs : 151
Number of DFFs packed to IO : 0
Number of Carrys : 66
Number of RAMs : 0
Number of ROMs : 0
Number of IOs : 11
Number of GBIOs : 1
Number of GBs : 3
Number of WarmBoot : 0
Device Utilization Summary
LogicCells : 301/384
PLBs : 48/48
BRAMs : 0/0
IOs and GBIOs : 12/21
#####################################################################
Clock Summary
=====================================================================
Number of clocks: 1
Clock: adc_3|mclk | Frequency: 84.81 MHz | Target: 83.13 MHz
=====================================================================
The iCE40LP384 bitstream is 8kB large, and it fits as a C source into the 128kB stm32f103 memory easily, thus you do not need the hw bitstream flash memory. Moreover, you may reprogram the FPGA logic "on the fly" off the MCU. MCU+FPGA on the inguard pcb.
And as a bonus - you do not need an FPGA programmer hw (as you do not need a hw programmer for the stm32 provided you run an usb bootloader) :)
-
Yes, my hardware could be optimized in many ways. I realize MSP430 isn't the most popular choice among hobbyists, after all, it isn't even the most popular choice of my own. I've chosen it just for higher fun factor (what was the point of the project).
Should I rework the kit for mass appeal, I'd probably end up with STM32, plus the ICE40 looks like sensible choice for programmable logic - I think we agree on this.
Also, your mention of inguard MCU along with PLD is really reasonable. During the design and development I had to make a few compromises because of not having a lot of "intelligence" in inguard part. Not much of power or fancy features needed, low power 8-bit MCU would be more than enough here.
I wonder if choosing low-end 8-bitter over slowly clocked ARM would make sense here, especially from EMC standpoint.
Thank you for recompiling the Verilog implementation. For EPM240 it takes a bit over 200 of 240 available logic cells. I didn't expect as much as 301 cells on ICE40.
-
@Jaromir - your design is great and I wish I could order a kit from you for 99Euro :P
Instead of my regular afternoon nap I took your verilog and replaced the uart output with reading the 32bit result reg via spi (sclk, miso, ss). It builds with 50LUTs less (251). A simple flag is needed to tell mcu (ie rising edge interrupt) the result is valid, so add 1LUT.
PS: it took me 10minutes inclusive compile time - to demonstrate the flexibility of your verilog.
I think 20-50MHz crystal clocked stm32 together with a small fpga (ie the LP384) in the inguard can easily be used, the 8bitter is not cheaper, and you get a pretty higher flexibility and performance. And you get a decent 12bit ADC for measuring the residuals and 20kB of ram for some simple DSP or faster measurements. As you have seen the FLUKE 8588A is using a Blackfin on the inguard board as well :)
PS: and the stm32f103 is arduino compatible..
-
...
The analog part - I've been pretty curious about which solution from the recent DIY postings (Jaromir vs. Kleinstein) gives a better results at the lowest digits..
...
Jaromir's design in the current form likely has a slight advantage with gain stability, but it has definitely higher noise. The comparison is a little difficult though because of the slightly different ranges (+-14 V versus +-11 V). For the linearity it is hard to tell, as the measurement is not that easy - I see a slight problem with a variable current through the resistors that set the reference current. So it really needs the tight thermal coupling of the LT5400.
For the design, I would not care too much which languish is more common. The bigger hurdle is more like having the knowledge about the parts (µC or CPLD) and the required tools. It tends to be easier to go from C to ASM on an AVR than to change to something like STM32 in C. With FPGAs the ability to solder the case (especially BGA type) can also be a deal breaker for DIY. My design can work with DIP only parts, even on a bread board - my first tests were with only the µC and UART on an Aruduino like board and the rest on a bread-board.
I agree that CPLD + µC could make things easier, but it needs 2 environments / development tools. So it is attractive to get away with just a CPLD or µC.
PS. A faster µC could help with faster conversion rates and possibly doing digital RMS. Even a 12 Bit ADC of good speed could give a reasonable solution for digital RMS (e.g. comparable to the analog AD637 or like solution in many respects).
-
My current understanding of the problems around the Multislope Precision ADC DIY design and its feasibility is as follows:
1. the real know-how and expertise is in the analog part and in the processes of handling the analog part such you will get the best results
2. the digital part - inguard and outguard - is the simple part. Any modern cheapo 32bitter can do, any cheapo CPLD/FPGA can do, it does not matter. I would be happy to have an MCU with good built in ADC (ie with an external Vref).
The other stuff like display, buttons, power source, usb/232/wifi/ethernet is just a business as usual.
I worked with 8080 asm, Z80 asm, 8051 asm, 68k asm, atmel's asm, pic's asm, but the acceptance of an asm based firmware is pretty low today. Not talking manageability of such a source. People do not work with asm today.
With FPGA/Verilog you do not care on how what asm instruction work, and how many clocks it is long, and how many nops you have to insert to compensate a loop, or how to shift a 24bit word 7bits left, or how to set the portB pin3 and 6.
DIY hw community is C/C++ positive, with more and more emphasis towards programmable logic (because most the tools are free, easy to handle and the small chips are cheap). Verilog/VHDL - ok, that is something people discuss from time to time. Thus the languages are pretty clear.
I would be happy to have a chance to buy a 10x10cm large ADC inguard board, for say XXEuro, with 6.5+digits capability +/-20V input ADC on it, with >1G input impedance, with the 399 on it, with a 10pin connector for +/-25V +/-15V and +5V external floating power sources, a 4pin connector which communicates via opto-isolated UART with "something".
I can flash the board through a 3pin SWD connector (both MCU and FPGA) with a $2 dongle, where the FPGA and MCU there are "standard" C/C++/Verilog supported things. In addition a small I2C flash for calibration params wired to the MCU would be handy on the board.
The FPGA/CPLD bitstream bianary could be put into a C const array easily, and flashed together with the FW into the MCU. Upon reset the MCU loads the FPGA and that's it.
You may have several bitstreams stored in the MCU's memory and you may reconfigure the entire FPGA on the fly within a few milliseconds.
With that $4 combo you may measure every even ADC sample with Jaromir's algorithm, and every odd ADC sample with Kleinstein's algorithm, 25 samples per second (provided the analog part supports such an switch :) ).
You may put a simple CLI in the MCU, and talk to the board via set of "commands".
That all is easy today. People play with it every day. People run FreeRtos with CLI on the $2 BluePill.
What is not easy is the analog part and the processes around it, imho..
-
Jaromir's design in the current form likely has a slight advantage with gain stability, but it has definitely higher noise.
You are right with the noise. Your measurements indeed show lower noise than what I achieved. I tried to decrease the noise level, but it was fruitless.
At first I had OPA134 in integrator, changing it to OPA140 did bring just tiny bit of an improvement.
I thought that noise may be contributed by voltage approaching comparator switchover point too slow, so I tried to include slope amplifier after the integrator, in noninverting configuration with gain 10, but I didn't see much of a change. Opamp in amplifier was LT1115 because that was what I had on hand.
Perhaps you may point me to other possible sources of noise.
-
It makes sense to look at the noise source. One way to look at noise is to separate the frequency ranges. It is mainly to ranges that really matter: one is the rather low frequency noise (e.g. some 10-100 Hz), that 'happens' during run-up. This is acting kind of as an error in the charge going into the integrator.
The other part is measuring the noise in the integrator, which is done during rundown or with the auxiliary ADC. This is more higher frequency noise (e.g. > 10 kHz up to maybe the MHz range with the comparator). There is not much noise from the intermediate frequency range, as this has to little BW to matter for the charge measuring and is averages out by the integrator to matter for the actual charge.
So it is mainly these 2 noise types: low frequency for the run-up and high frequency for the rundown. These can be looked at quite separate. The shorter the integration time gets, the more important high frequency noise gets. Quite often (if no big mistake / weakness) at a few PLC and more the high frequency noise is not the main problem - this gets important for something like 5 ms integration and faster. A main way to fight the higher frequency noise is using a smaller integration cap and faster modulation. So for now I look at the low frequency part first:
With the common relatively high resistor values (e.g. 50 K or 100 K) to avoid self heating problems the resistors are a major noise source. The reference paths are essentially current sources, so high resistance here is good: so a higher reference voltage and larger resistors have some advantage, as it's a lower noise current source. So using some +-14 V for the references is already good compared to the often only 10-12 V in meters like the 34401 or 3458.
For the switches it is kind of natural to have the same resistance for the input and the reference paths, as it allows for some compensation. So this is my reference case. In this case the noise from the resistor at the input and the reference paths is the same size. So for the noise, one gets the noise, as if one would have twice the resistance as voltage noise source. If the resistors at the reference are chosen smaller (e.g. half) than the input side, the current noise goes up. At half the resistor values the noise referred back to the input is as if the resistor from the input goes up by the ratio. So the 200K in and 100K reference case already gives the noise of some 200 K + 400K = 600K. This is some 100 nV/sqrt(Hz) to start with. So to get really low noise, one may have to start with a smaller resistor at the input.
The twice higher resistor at the input also gives a noise gain of 3 to the voltage noise of the integrator. For the equal resistor case the noise gain is only at 2. Still with the OPA140 and a short integration (e.g. 1-5 PLC) the voltage noise is not that high. Going much slower will add 1/f noise of the OPs.
Another noise source is noise from the reference inverter this adds with a gain of 2 or 1 with the 2:1 or 1:1 resistor case.
Another, odd noise source is higher frequency (around the modulation frequency) noise from the reference, that is demodulated by the run-up modulation. This noise might contribute a little, but it should be easy to filter - at the very low noise level the RC filter at the LM399 makes some sense, even of only effecting > 1 kHz noise.
For the higher frequency noise, one may have to find a good balance of speed and noise bandwidth for the integrator. A faster integrator has more BW and thus more noise. So ideally one may have to accept that the last fine slope step is limited by the comparator / slope amplifier speed and may not give the full timing resolution. It can be difficult to find a good balance here (I avoid this problem by using the relatively low BW ADC). A fast comparator is not always better. A slope amplifier may have lower noise - though noise specs for comparators are rare, so hard to tell how good they are. A smaller integrator cap and thus more run-up steps also help with the high frequency noise. However the DG211 switches may not be suitable for really fast switching, as they have quite some charge injection. Also switching the voltage from 0 to Uref can additionally add some "charge" from parasitic capacitance - switching the unused references to ground has some advantages. The switches also tend to produce quite some higher frequency glitches, that could lead to noise or linearity errors - though slow these can be a problem with the DG211. I had to really care about supply spikes / glitches - just massive decoupling at the chips was not working well. It was more like adding ferrites / resistors in the supply, at both the sensitive parts and the possible trouble sources.
The simple rundown with only one slow slope, that is not that slow likely has a limited resolution and thus some quantization noise. More resolution (e.g. smaller slow slope) could avoid the quantization noise. The ratio of 1:6 is more suitable for very fast conversions. It could well make sense to have a lower reference level like 1:16 or 1:30 - it still does not take that long.
From the experimental side one could check the higher frequency noise from very short conversions, like a run_up without feedback (e.g. some 10-100 µs). Here the higher frequency noise would be measurable on it's own - not much integrated low frequency noise at this speed. Another point is comparing 2 speeds of the modulation: this gives a hint if the extra noise is switching related or not. Switching related sources could be something like jitter or supply voltage noise, that effects the charge injection. Also some DNL problems may look like noise.
@jaromir: What are the integration times and modulation frequency during run-up ?
-
Thank you much for detailed and valuable analysis. Your responses are goldmine of information.
In my case integration time is 20ms, with 200 runup cycles, ie. 100us per integration cycle.
DG211B is specified to have 1pC of charge injection by Visahy datasheet. I tried to select switches with charge injection as low as possible while withstanding +-15V on open switch.
I can try to experiment with both runup modulation speed as well as rundown speed. Slower rundown slope is not a major problem for me, as I'm not aiming at very fast acquisition, rather than slower and more precise measurement.
Also, I can easily try to filter the reference noise to some degree. There is even footprint for RC lowpass filter on the PCB, though the resistor is currently zero ohm link, but capacitor is fitted.
I guess the R17-C20 network in your design is added to cut down switching spikes from '4053. Is that correct? What kind of problem did the ADC exhibit without it?
Another thing I find intriguing is composite opamp in integrators of some ADCs, for example your design. This kind of composite circuit is not often used. What was your approach for selecting opamps (OPA1641/TLE2071) and resistor divider in between those?
-
R17 and C20 are kind of part of the compensation of the composite integrator. There is little need for these if a single OP integrator is used. Without these two the input voltage to the integrator and output of the OPA1641 showed quite some ringing. This required the short (fixed) phases in the modulation to be longer.
The idea of the compound integrator is to keep the input voltage to the integrator close to zero. With just a single OP, there would be some rectangular form residual voltage somewhere in the mV range, due to the limited GBW of the OP. If the resistors for the reference paths are not perfectly matched this can give a contribution to nonlinearity - by it's own the voltage is not a real problem.
The second OP reduces the residual voltage to some peak that decays after some 0.2-1 µs, depending on the speed used. The divider between the OPs is needed to adjust the stability / compensation. The 5:1 ratio is about right for same speed OPs. The choice of TLE2071 and OPA1641 is in part to the parts available at the time. When starting I used only a single OP integrator with a TLE2071 - at that time I had ordered parts from TME.eu and the TLE2071 was one they had at a reasonable price. In the compound integrator (and especially in my case with the ADC) the noise of the "fast" OP is not that critical - it is mainly speed. In the classical form the OP's noise may be more critical, as the comparator also reacts to higher frequency noise.
The OPA1641 is not that different from the OPA140 - just cheaper and slightly higher bias and offset. My other option here is an OPA145, the slower brother of the OPA140. For the test chose the fast OPA1641 to get a little more signal at the test point at the OPs ouput.
The 2 OP integrator is used in the HP34401, 34411, Keithley 2000, 2010, 2182, 2001 (some versions) - so it is not that exotic. the Keithley 2002 and 3458 even use 3 OPs - today one should get away with 2 OPs as the OPA140 is fast and precise. Besides the residual input voltage, the lack of high precision JFET OPs could have been a reason for the compound integrator. So just a single OPA140 may not be such a bad solution, if the resistors are well matched. The compound integrator is more like a thing for lower INL - it may even add some noise in the classical form.
With the charge injection the DG211 in deed does look good. One has to be a little careful with the front page numbers, as the charge injection depends on the voltage level. Another point is that the circuit impedance also effects the charge injection. In the circuit with just single switches the capacitance of the loose end of the resistors acts as an additional charge pulse. This extra charge pulse could upset the integrator quite a bit. It also take some time to get back to a stable off state (e.g. some 10 pF *100 K) - this could give an effect with very short off phases.
The reference noise is more like a small contribution. AFAIK some 100 nV/Sqrt(Hz) for the LM399 at some 10 KHz. So not that much filtering needed to reduce the 10 kHz by something like a factor of 5. It's a small noise contribution but avoidable.
Initially I also used the 4 phase modulation (to variable phases) during run-up. However for some reason the 2 sides/ positions in the cycle were not exactly equal and this can lead to quite some INL error just in the center of the range. This is because there is a chance from pos / neg / pos / neg to neg / pos / neg /pos over a very small range with changing many times between the 2 sub-phases nearly at once.
A simple test for the effect of higher frequency noise would be just doubling the integrator capacitor. This cuts the voltage at the comparator in halve and about doubles the effect of higher frequency noise. So one could see if the higher frequency noise is that relevant at 1 PLC. It helps to know which type of noise to fight.
Besides reducing the integration cap (which needs faster modulation) one could also increase the integration to 2 PLC. This reduces the effect of higher frequency noise by a factor of 2, and at 2 PLC the 1/f noise of the OPA140 is still very low. With older classical MS ADCs the optimum may very well be at more than 1 PLC - possibly even 10 PLC.
-
Here is a simulation of the Kleinstein's DIY MS ADC, the analog part.
You may use different opamps (with some models the simulation speed is low).
Timing is just a simple runup toggling, different from original.
Update: re-indexed relevant parts
-
R17 and C20 are kind of part of the compensation of the composite integrator.
I hope this isn't a stupid question. Did you mean R20 and C17 ? Enjoying your commentary, some of the aspects are counter-intuitive to me.
-
R17 and C20 are kind of part of the compensation of the composite integrator.
I hope this isn't a stupid question. Did you mean R20 and C17 ? Enjoying your commentary, some of the aspects are counter-intuitive to me.
Of cause it is R20 and C17.
For the OPs choice the second OP (with the capacitor in feedback) mainly needs to be fast. If at all higher frequency noise matters. The 1st OP in the compound integrator (with divider at the output) does not need to be so fast (though more than 1/5 the GBW of the other OP would be nice - faster OPs are effectively slowed down by the divider) and here low frequency noise and DC precision matters. Old Keithley meters used something like OPA177 (a little on the slow side) as a precision OP and AD711 for the fast part.
For the very fast switching spikes from the 4053 the HP34401 (and quite some other meters) and my ADC circuit use ferrite beads. I don't know exactly how they help, but they do improve the noise and settling of the integrator a little. The high speed of the HC4053 is a 2 sided thing: it keeps jitter low, but can also causes EMI issues from RF components not visible on the scope. However for the supply lines I more turned away from ferrites towards just resistors - they are just more predictable to me.
-
With ferrite beads (smd 75ohm). Found a MCP600x which works.
-
I'm guessing you probably chose the LT1028A just for the purpose of the simulation, but for a real implementation the input current noise, 4.7pA @ 10Hz, is much too high for this application - the noise due to the current noise exceeds the voltage noise for source impedance > approx 200 ohms. And you have 2 of them so the current noise will be 1.4X
The 40nA input bias current will cause a fair bit of offset, but so long as it stays constant, autozeroing will take care of that.
The 34401A op amp choice is a bit surprising (to me at least). The OP27 was a goto precison amp at the time so probably a reasonable choice, apart from the relatively high current noise. But why use an AD711? Its slower (4MHz GBW) and much noisier (2uVpp 0.1 to 10Hz) compared to the OP27 (8MHz, 90nVpp). Its a JFET so the bias current and current noise are much lower than the OP27 but that is pretty much irrelevant given they are already using an OP27. So why not use another OP27 or a faster non-precision, low noise amp? The AD711's full power bandwidth is only 200kHz; it does have a much higher slew rate of 20V/us compared to 2.8V/us for the OP27, but even that should be enough for the 34401A with a max dVc/dt of around 1V/us.
Of course it works well enough so perhaps it was a cost question - except that as a precision JFET I doubt it would have been particularly cheap either.
-
The OP choice in the 34401 surprises me too. The current noise of the OP27 can be a real problem at 10 PLC. The 2 nd OP may not need to be so low noise, but higher GBW would have definitely been an advantage. The µC internal ADC used in the 34401 is not that fast, and thus does not react to the very high frequency noise. At problem at the time could have well been that there where not many fast precision OPs.
The is another reason a don't like a BJT based OP at the integrator and thus prefer something like OPA140 and similar: the input can see small spike from switching that may exceed some 25 mV and at this point there can be additional input current for a BJT based input stage. At least one leaves the linear range.
The 34401 has another oddity with the resistors at the input, using an additional resistor to ground to effectively divide down the signal at the input. The ASIC they build for it was probably the reason HP used it so much.
@IMO The MCP600x I use in my version before the µC internal ADC is not critical - its used with quite some delay. The MCP600x are just simple and common 5 V rail to rail OPs. To speed up the simulation one can use the universal OP model from LTspice for non critical OPs.
-
Yes, the opamps in the above simulation are the "placeholders" only. With some opamps the simulation is slow or even not converging (ie OPA140).
Yes, it could be interesting to use the LTSpice "universal opamp" model and specify those several parameters it offers.
See below the LTspice model levels (from the LTspice library):
-
Could we somehow summarize what type of opapms are shortlisted for the specific ADC stages?
Input buffer:
---------------
1. OPA140
2. OPA145
3. OPA189
Integrator:
---------------
1. OPA140
2. OPA1641+TLE2071
Slope amplifier:
--------------------
1. NE5534
LM399 buffer/inverter:
--------------------------
1. OP07
2. AD8676
3. TL072
Comparator:
---------------
1. LT1116
2. LT1016
3. LM311
??
-
The OPA189 or similar makes sense for the input buffer, only if one needs low drift without auto zero. Normally the OPA140 should be still lower drift than the integrator. Here it could be about the accuracy: The
OPA140 OPA1641 has very high gain, but linearity may be limited by the still good CMRR. The OPA1641 OPA140has better CMRR, but less gain. Bootstrapping the OPA145 improves on the CMRR, but in the current form is a bit on the slow side.
For the Integrator OPA1641+TLE2071 is what I currently have, but other combinations are possible too. I don't even consider the TLE2071 a very good choice. Chances are OPA145+OPA1641 may work slightly better, as the OPA1641 has lower output impedance.
Just the single OPA140 may be good too. It can have some advantage in faster settling than the compound integrator, but would like very well matched resistors for the references. So it depends on the rest of the circuit.
The slope amplifier is relatively uncritical. It should be fast and low noise (e.g. less than the integrator), so the NE5534 is often kind of good enough and cheap. If a very fast comparator response is needed something like OPA209 (20 MHz GBW) could be an upgrade.
For the reference amplification it depends: in my form the amplification and load is static, so the OP07 is good enough. It contributes a little to the noise and drift, but not much. The AD8676 can be better and this may be needed for a rather dynamic loading to the reference.
In my circuit I use the µC internal comparator. With a slope amplifier the comparator noise should be no longer that critical and often the slope amplifier also sets the effective bandwidth. So the LM311 can be good enough in quite a few cases.
Quite often the OPs are not the really critical parts. The switches and the resistors can contribute quite a bit: quite some offset drift is due to a change in the ratio of positive to negative reference due to resistor drift. For this reason AZ OPs are of limited use there.
Quite often there is also a good enough: e.g. the OP07 are usually better than the LM399 reference when it comes to drift and noise. With only 20 ms (and up to some 100ms) integration the OPA140 or OPA145 for the integrator are lower noise than the usual 50-100 K resistors at the integrator: so there is limited use of even lower noise OPs here.
The integrator speed determines how fast the modulation can be. A very fast modulation is mainly needed to allow a very small integration cap and this way reduce the higher frequency noise, that is relevant for very short integration (e.g. 1 ms). As charge injection may also contribute, a very fast modulation is not good per se. Some 10-20 kHz should be fast enough to avoid DA related errors (at least the slow part), even without super fancy caps.
-
While reading the service manual of the 3478A (the Mutlislope detailed description chapters) I find myself asking why the meter is just 5.5digits, when Jaromir's and Kleinstein's meters are attacking 7digits with ease.
The 3478A's MS algorithm and the hw around (ok, the opamps are rather oldish and the switches inside the hybrids have unknown parameters) is much more complex than the 2 designs above.
For example more complex phases, variable rundown currents, 6bit DAC for integrator's offset compensation, etc.
Does the additional 78's DMM circuitry limit the "achievable" resolution (like dividers, etc) while the MS ADC itself can do more?
How would the 78's MS ADC perform with modern parts?
-
The ADC inside the 3478 is more like a reduced version of the 3457 (near 7 digit performance). AFAIK it uses slower control buy a CPU but possibly the same hybrid (though possibly lower grade ones). The 3478 is also one of the better 5.5. digit ones.
The old Multi-slope II ADC still has a few weak points: The modulation is relatively slow and the integration cap relatively large this results in some noise contribution from the comparator / slope amplifier. This is especially important for relatively short integration.
The integrator has one reference path always connected and is only switching one side - this increases the noise gain for the integrator OP and adds extra noise from the resistors. Using the difference of positive and negative current also adds to drift / uncertainty.
With relatively slow control the theoretical resolution is also limited. The CPU used is considerably slower than the modern single chip µC or FPGA.
The 3457 with an ASIC for faster control is considerably better resolution.
I don't think the ADC solution is especially good, as it is quite some effort. But this was about the state of the art by that time.
My design is more like an improvement from the HP34401 on. It is also made with a simple circuit in mind, making it even simpler than the ADC in the 34401, despite of better performance. It also uses quite a few function inside the µC (ADC and comparator). With parts from the 1980s the circuit would not be that simple either. Better OPs also help as there is no more need for analog offset compensation.
-
Though Kleinstein gave his answer, here are my two cents:
While reading the service manual of the 3478A (the Mutlislope detailed description chapters) I find myself asking why the meter is just 5.5digits, when Jaromir's and Kleinstein's meters are attacking 7digits with ease.
I'm aiming at 6,5 digits with my design. My design is simpler than comparable designs from 30-40 years ago because:
1, I keep feet on the ground: I do not shoot for high acquisition rates and have realistic 6,5 digit resolution in mind. Having high throughput of meaningful data is difficult and I'm not doing it.
2, New analog components. With better analog components, one can sometimes do less compromises, omit compensations, corrective circuits, cherry-picked components. That makes overall circuit much simpler and less laborious to build and setup.
3, FPGA/CPLD - this is expansion of point 2: in older TE there is often quite bit of circuitry to workaround that they didn't want to roll new ASIC for each meter. With FPGA and CPLD for a few bucks I can make he digital circuitry as needed and save five+ digit USD stash for ASIC. Alternatively - as Kleinstein demonstrated - MCU with appropriate peripheral set can do great job for fast digital circuitry, unthinkable in i8049 era.
4, Standing on shoulders of giants. I can take inspiration from patents, repair manuals and technical notes written by a lot of clever folks, sharing their hard earned knowledge.
All those points are doing the ADC design much simpler, less time consuming and therefore cheaper; available within reach of average hobbyist within limited time frame during lunch hours or evenings when kids are sleeping.
-
It seems most of the current multislope designs in the wold can trade resolution off for aquisition rate, could either of your designs do the same, or is there some fundamental limit that would prevent say 50x the sample rate but only resolving to 3.5 digits (and similar steps in between)
-
The ability to trade in resolution for speed is a general feature of the multi-slope ADC (and also the sigma delta ADC).
There are several effects that limit the range and how a shorter conversion effects the resolution/noise:
Towards very short conversions the resolution goes down proportional to the integration time. It depends on the design wether this limit is more due to the theoretical resolution (e.g. time steps for the last rundown) or from the higher frequency noise that can limit the useful resolution for the final charge reading. So there is a practical limit on how good a timing resolution helps.
Towards very short conversions there is also the time lost for the rundown, that limits the useful maximum sampling rate. It does not make much sense to have integration much shorter than the rundown time.
The other effect that can limit the effective resolution is low frequency noise. This noise (if not dominated by 1/f noise) goes down with the square root of the integration time only. So it takes 4 times the integration time to reduce this noise by a factor of 2. In the 1/f noise dominated range longer integration does not help any more. This extra 1/f noise limit can often be circumvented by using averaging of shorter integrations.
Often the real integration is only up to some 10 PLC and slower conversions are averaging with a zero reading in between.
So there are usually 2 ranges: resolution (theoretical resolution and noise) going up proportional to integration time T at short times. At long times the resolution (noise limited) goes up with the square root only. This also applies to averaging of shorter conversions to circumvent the 1/f noise.
Where the cross over between the two ranges is depends on the design - older designs with not so high timing resolution or relatively slow modulation tend to have the proportional to T regime up to some 10 PLC or so. For a good design it helps if the cross over to low frequency limitation is well below the 1/f noise range.
-
...is there some fundamental limit that would prevent say 50x the sample rate but only resolving to 3.5 digits (and similar steps in between)
You can go as fast as you wish.
Integrating ADCs do have great feature - you can have fixed integration time in multiplies of power line period (20, 40, 60, 80... etc. ms for 50Hz) and thus suppressing the power line noise right at the ADC level, with no need for digital filtering.
Having shorter integration times is indeed possible, but you are losing this advantage, so if you are into higher acquisition rates and you don't need much of resolution, there is nothing that keeps you from using other ADC types, like SAR. There is plenty of ADCs with 10-12bits of resolution running up to few MSPS, often even inside modern MCUs.
-
In the meanwhile, Any chance I could see the Mux / Integrator parts of your original PCB layout, Having a crack at re-spinning Klenstein's as a bit of a personal learning experience on high precision layout, but the 4053 does not make it easy to escape route the positive supply rail, and would like to see what the other side of the fence looks like with yours Jaromir. Equally the analog ground run to the integrator is a bit weird to me, its low impedance essentially, but has to be treated as a very high impedance signal best I can tell, having the input and analog ground treated almost like a differential pair.
-
Now, what about the 3 resistors at the integrator's input - Jaromir's 200k+100k+100k, vs Kleinstein's 50k+50k+50k.
There is the resistor's thermal noise, TC, ratio matching TC, the switches On resistance and self-heating to consider.
I've been thinking to use the LT5400 there - either 4x100k or 4x10k version (there is none other suitable version there available, afaik). Perhaps the 4th resistor as a heater with 4x10k version (the 100k creates only 9mW at 30V, not sure it is enough).
What would be the right optimal choice, considering the OPA140 as the integrator and LV4053 or DG switches??
PS: It is my current understanding nobody here considers to build a high speed MS ADC here.
A few/couple measurements per second max would be great with 6.5digits, or less for 7digits with longer integration..
-
Kleinsteins is 25K+25K+25K, he paralleled the resistors. there is a FB resistor on both paths that I'm not quite sure of the value of, which would increase the reference resistance,
-
...would like to see what the other side of the fence looks like with yours Jaromir.
There is dedicated thread about my design here https://www.eevblog.com/forum/metrology/diy-6-5-digit-voltmeter/ (https://www.eevblog.com/forum/metrology/diy-6-5-digit-voltmeter/) all with complete schematics, PCB layout, source files and stuff.
That being said, I'm not claiming this is the best possible design. In the meantime I found a few flaws with the PCBs and will do respin. I released all files to public, so anyone is invited to discuss, study and improve it. When I do respin, I'll surely update the uploaded files or start public repository, so it doesn't get too messy.
-
The resistors at the integrator are kind of a balance between noise from the resistors and errors due to self heating and the switch resistance.
In my configuration with 3 equal resistors the resistor contribution to the noise is as if 2 of the resistors are in series, contributing there voltage noise. So with 3 x 50 K one get the noise from 100 K which is about 40 nV per square root Hertz. The OP in the integrator contributes about twice its voltage noise. So for an OPA140 and 25 Hz (assuming a 20ms signal / 20 ms zero cycle) this would be some 8 nV/sqrt(Hz). So the resistor is actually more important for the noise than this OP.
I know a few more other noise sources, as the reference amplification, the buffer, but these should be small (e.g. 10 nV range).
For the difference of 2 readings (signal and zero) one effectively has a noise bandwidth of 100 Hz. So the measured noise of some 700 nV RMS corresponds to some 70 nV/Sqrt(Hz) for the single conversion. So there is still some noise not accounted for.
With 25 K resistors the noise goes down to some 550-600 nV. It looks like I have some 1/f type noise, as the noise gets worse at 2 PLC and 4 PLC. For the time being I consider the noise low enough.
With 100 K resistors for the integrator one would be at some 60 nV from the resistors. If the specified -<45 dB noise level for the LT5400 is true, the excess noise should still be not too bad. So the overall noise could still be good. With very stable resistors like the LT5400 one could get away without the extra 7 V reading in between.
Using a 4 th resistor as a heater is possibly. The 2 reference resistors see a constant power. The maximum signal voltage is at about 12 V. So a voltage up to 12 V would be enough for compensation. As there is usually alternating zero and signal reading the heater could get away with some 8.5 V or so as the maximum. Due to the good TC matching in the LT5400 I see no real need for heating though. Power compensation would be more a thing for something like NOMCA type resistors with less perfect TC matching.
Attached are the PCB files for the TOP and bottom. The bottom needs an additional connection drawn in red, as there was a mistake. With SMD type ferrites and without the initial error the layout may even get simpler. The board is an odd mixture of SMD and THT. The 4053 is the DIP16 below the center of the board. I had used resistor symbols in the circuit for the ferrite beads - these should have very little DC resistance. These are kind of a copy from the HP34401 configuration.
I consider the placement of 4053, integrator and resistors good - the position of the buffer amplifier and LM399 so close to the DG408 is more of a problem. The supply to the 4053 should still have some filtering. That is currently done with a bodge and cut.
-
...Perhaps the 4th resistor as a heater...
LT5400 does have exposed pad, and manufacturer suggests to connect it to quiet analog ground, to decrease resistor-resistor capacitance; groundplane helps to decrease self-heating, too.
-
I wanted to use the exposed pad as the contact place where to measure the temperature of the package while heated. But it seems it is not required with the 5400 (see above).
4x10k is too low then?
-
With 10 K resistors and some 14 V reference (twice the raw 7 V from LM399 / LTZ1000) there would be quite some power: some 20 mW for 2 of the resistors and up to about 10 mW for the 3 rd resistor. Even with the thermal pad the temperature rises by some 40 K/W. So 10 mW of variable heat would result in 0.4 K temperature variations.
The second problem it that the switch resistance gets more important.
A third problem is that the integrator would need to cope with larger current jumps. The usual OPs (like OPA140, OPA172) have an open loop output impedance in the 100 Ohms range and a 2.8 mA current jump would thus cause spikes up to 280 mV. This could well exceed the linear range even of JFET based OPs. A two step transition could halve the step, but it is still quite a lot.
So the 10 K array is on the low side, likely causing higher INL errors. A 100 K array (like Jaromir uses) may be a little on the high noise side. Still some 60 nV (compared to some 40 nV with 50 K) from the resistors is not that bad, especially for a first test. Though a little tricky from the layout, there could be the option to have a second array in parallel, if really lower noise is needed.
At least for a 1st test there are also MORN resistor arrays. These are same size as the LT5400, but cheaper and also available as 50 K and 20 K.
For comparison the HP3458 uses 40 K and 50 K resistors and +-12 V reference. Noise wise this is slightly worse than 3x50 K and +-14 V reference. They use some 10 K für the high speed modes - so using 10 K resistors (though with only 12 V reference) is not totally out of question.
The integrator resistors are important for the ADC gain stability and the one for the input can effect INL due to self heating. The critical parameter is TC matching if the resistors are coupled - so the LT5400 is really good quality.
The gain stability is also effected from the resistors used to amplify the reference. Here 4x10 K resistors is a suitable value.
-
Kleinstein might I ask what the value of R102 and R35 are, It seems to me that these should be very close to 0 ohms to prevent the references and bufffered input from effecting each other,
Equally I'm suprised you have not needed a negative supply on the 4053, as the internal switch resistance in the chip should mean the negative references input should be some small negative voltage.
-
R35 and R102 are ferrite beads. So likely something like 0.1 Ohms of ohmic resistance and some lossy inductance. Currently there are 300 Ohms nominal (at 100 MHz) - I am not sure if this is right.
The CMOS switches actually also work a little (like 200 mV) outside the supply range. So up to about -200 mV are OK without a negative supply. For highest performance a slight negative supply may be good, as for the 74 HC4053 charge injection is supposed to be minimal with some -0.5 to -1 V supply, at least for some manufacturers that show a curve. I have tried it with a negative supply, but at least the way I had it (with just a diode to get some -0.6 V) did not help.
With some 50-100 Ohms of switch resistance and some 200-500 µA of maximum current, the voltage should only reach some -20 to -50 mV.
However it is an argument against using much higher reference currents with 4053 switches.
The switching part I use is to a large part similar to the HP34401. This also includes the ferrites. I don't fully understand why, but they did some improvement.
-
Still working on the routing, It breaks a lot of conventions I'm used to, everything has to be planned as a differential current loop to prevent any kind of cross talk or interference with the measurement, meaning there are vastly different requirements for how quiet the ground should be for a given area, e.g. R35 seems like you would just connect it to the same ground as the analog filter, but that is not quite correct, the ferrite beads ground needs to be well away from it as its switching significant currents compared to the sensitivity of the system and its performance does not effect the measurement at all, its just giving that current somewhere to flow, and how the input filter needs to be almost directly at the input of U11, as that is the only place it forms a current loop with ground,
As far as I can see, the analog ground used for the integrator needs to be treated like a differential return all the way back to J2, with the references referenced off that point. but leaving something having to be done about all the current from the zener... I', slowly unwrapping it all, but I can see why people say laying out these boards can be harder than designing them. I suppose once its built up into a well planned block it will be a reusable module, but wow does this strain the brain.
In these type of circuits, how much effort is generally put to having ground planes on the reverse side of the board overlap the chips, as that could increase power supply noise coupling in, but I would imagine the shielding being a bigger benefit.
Or have I accidentally started trying to design far better than is actually required?
-
I also think keeping the analog / signal ground separate is a good idea. I just consider it as a separate, e.g. analog signal, though I have a connection (via a wire) at one point. In theory the connection could later be external too, e.g. at the output therminal or the voltage sense wire of a shunt. One could even consider to have the signal ground at a level of something like +300 mV to essentially get a negative supply to the 4053.
For the current to the zener reference, there is a resistor to provide most of the negative side current from the -13.5 V reference and not through ground. Anyway the residual current is constant and thus less critical. The really critical one is variable current.
For low frequency DC a ground plane is usually not the right thing to do - it is more like star ground. In may layout I did a few compromises on this, where there should be not much current (e.g. input to the NE5534), especially not much variation in current.
The digital part may like a ground plane. One point that worked well for me is to no only isolate those parts that are sensitive to RF interference (e.g. analog VCC of the µC), but also have the same resistor or ferrite type insulation for those parts that produce interference. It may be a good idea to add even a few more such resistors, e.g. in the supply to the OPs for the reference amplification. Ideally one would a void to have a low impedance supply trace to both side of the decoupling caps. Just a cap is not a good filter - a cap and resistor is much better.
The layout may be tricky, but it looks like other meters (e.g. the ADV6581) get away with some really odd choices in the layout / placement. So one may not have to overdo it in the first try.
I see some odd effects around the DG408 MUX, like different inputs behaving a little different. It may be a good think to keep the reference with it's heat a little more away from the DG408. Another thermal to observe is that the buffer amplifier is a variable heat source and should thus be not to close to sensitive resistors. This may be a little less critical with really good resistors as an LT54000 array. From my circuit, there is one more idea: the filter capacitor for the reference can be from the -14 V instead of GND. This gives effectively 1/3 the filter frequency.
-
I would not put the voltage regulators on the ADC board as they are a large source of heat. I think Jaromir had recognized that too as he moved the regulators off his ADC board (compared to his prototype).
-
That is correct observation.
It's always advisable to have little thermal gradients on sensitive PCBs.
-
Kleinstein for your design, It looks like by trimming R77 to a slightly lower resistance (about 14.3K) it reduces the references ground current to almost 0, is there a particular reason behind it being 15K flat, or could it be trimmed like this so ground is just a null point. Just trying to rework things to have there be a very quite signal ground shared by the references and integrator, so the less current I dump on it the cleaner things should get.
I'm also not quite sure how to manage the power rails, as it ends up that the integator charge current is looping through the supply rails, not the signal ground, meaning I need to make a very quiet connection between the integrator op amps supply rails and the buffer op amps rails, as that is where that half of the current loop is flowing
-
The ground current compensation with R77 can be tuned for better compensation if needed. I originally had 2 resistors in parallel to get fine steps if needed - though one turned out unusable.
For the current to the integrator, one has to separate the AC an DC part. The integrator itself can only sink AC current, as the current has to go through the cap. The other current path is from the reference currents either to ground or the integrator.
For the current to the integrator, I have the relatively large resistors (150 Ohms) in the supply and the AC current going through 2 x 2.2 µF (C6 and C14) to the ground to join with the current from the switches. 150 Ohms * 2.2 µF is large compared to the modulation period (some 25 µs) - so not much of the AC current flows through the global supply.
The 5534 and the integrator share the same supply island with 150 ohms for separation, as there can be quite some current flowing between them, through R12. Originally I planed with a lower value for R12 to reduce it's noise (it could be important with a larger integration cap). Currently the 5 K from R12 give more noise than the NE5534 - though this higher frequency noise is still low and would be an issue only for very short integration (e.g. < 1 ms).
The DC path is from the supplies via the buffer amplifier through the integrator resistor (R3) towards and than through the 4053 directly to ground or kind of mirrored at the integrator and reference sources through the 4053 to the same ground point. I would not worry that much about the DC part flowing through the supplies - thats what the supplies are good for.
-
I studied design of 34401 once more and one thing caught my eye:
The third switch (pins 3,4,5 and 9 of 4053), controlling input current from ADC input to integrator is constantly open *. In Kleinstein's design - which I considered to be similar to 34401 - this switch is operated by MCU. I have to admit his approach is easier to grasp for me.
If ADC input is never disconnected from integrator, how is integration time defined?
How do they perform residual integrator charge readout? I guess it's better to have integrator output voltage stable during readout, no matter how it's performed, that suggests turning the input off during that phase.
---------------------------------------------------------------------
* pin 9 is grounded, so that pin 4 is switched to pin 5 and pin 3 is never used.
-
The 3rd switch of the 4053 always fixed and thus the input always connected also looks odd to me. For the normal operation this is not a problem: the ADC in the µC is relatively fast and reads the charge in the integrator on the fly, at some point in time. This time is effectively the start of the integration. A second later reading sets the end.
However there are a few difficulties, odd points still unclear to me:
1) the modulation is very fast, especially for the integrator used. This seems to limit the input range and require the large resistor for the input signal - noise wise a poor decision.
2) reading on the fly it is not clear on how much of the current phase / reference setting is effecting the reading.
The last run-up step has likely only partial effect, but it is not clear how much.
3) the resolution is rather limited, as the ADC must cope with a relatively large voltage range of a full run-up step.
This could kind of explain the limited resolution of the 34401.
Even if not needed for the measurement, I would very much like to have the option to turn off the input do do the internal calibration of the auxiliary ADC scale. They may get away with switching at the very input to ground.
When switching between the input signal and zero reading, one still has to wait for the input amplifier to settle. So the continuous integration is not such a big advantage, as the non AZ mode is quite noisy from the OP27 anyway.
Some of the Solartron DMMs also have the input signal continuously connected, though they do not use an extra ADC, but the comparator timing.
I also see my design as based on the 34401, at least its a good point to compare: the 2OP integrator, 4053 switch, no integrator reset and using the µC internal ADC for residual charge reading. The improvement is mainly from the added rundown phase (so mainly a 'software' point), that adds to the resolution and from using better OPs in the integrator.
-
Taking measurements of integrator output "on the fly" is possible, and as far I understand, it's done by 80C196 processor. It's got 10-bit ADC and integrator output is routed to one of ADC inputs, confirming this idea. This allows to omit zero comparator and slope amplifier, both being critical components to integrating ADCs. So far so good.
On the other hand, the internal ADC isn't particularly stellar and I can see some compromises being made here:
- S&H sample time is 1,33us (8 states per 167us as it runs at 12MHz) in fast mode, compared to tens us period of modulation frequency.
- ADC has resolution of 1024 levels, but minimal 256 levels - minimum 8 bits, maximum 10 bits of resolution.
- ADC has INL of +-4 LSB
- ADC has DNL of +-2 LSB
- DS requires maximum input impedance 1,2kOhm maximal, but R405 and R407 are 4,16kOhm total. I guess violating this parameter is somehow worsening the internal ADC parameters even more.
I wonder how many bits (or digits of result) are they getting from rundown phase.
The Solartron DMMs has different ADC principle; mark-space type, as described in patent US3942172. I'd say it sits somehow closer to sigma-delta ADCs than to integrating ADCs.
-
Kleinstein what would you have used (or like to have used) for C13?
Never laid out a reference before, But think its coming up quite nicely, still any input would be appreciated,
main goal is just to improve on the layout without increasing the BOM to the level of the LTZ1000 madness.
Only connection left here is to escape the zener voltage to the input MUX, but that is what the third thermal leg is intended for.
-
For the proposed layout, it would be a good idea to have R4-R7 well matched. These resistors effect the ADC gain and thus the scale factor. So I would at least try to keep them together, or even better use a resistor array (e.g. AORN, NOMCA, MORN or LT5400-10K). 10 K resistors should also be Ok.
Especially with a resistor array one could consider a slight change: create the asymmetry / slow slope not with R8 parallel to R7, but an extra divider at the + input of U8. Though not that critical, TC matching would matter inside the extra divider and not from R8 to R4-7.
With not so good resistors I currently do a gain measurement for every reading (just like old Keithley 19x DMMs) - this slows down the measurement and adds some noise. It could be still attractive for a low cost version.
For the filter cap C13 a relatively large values is beneficial. I currently have 4.7 µF and R22 now at 5 K. A slightly larger cap (e.g. 10 µF could be used, but they tend to become physical large. As the reference is usually a constant voltage and some warmup is needed anyway polyester cap (e.g. MKS) should be good enough. I would be a little suspicious about MLCC there. To a lesser degree this also applies to C26, C28 but the 100 nF MLCCs may be OK. As an additional modification the lower side of C13 is now connected to the -13.x V output. This essentially works as a x3 capacitance multiplier. So now I have 3 x 4.7 µF x 5 K or just short of 75 ms.
The main idea is to have the capacitor to average / filter the reference over the time of a whole measurement cycle (either signal and zero or signal, zero and 7 V). This should help ta avoid some avoidable noise of the reference without too much effort.
As the reference value is not really used in the zero reading this would make it somewhat sensitive to reference noise at around 16 / 25 Hz. This unwanted part is relatively easy to filter out - there is not much to be done about low frequency noise (e.g. < 1 Hz). The main purpose is to get rid of that extra relatively high frequency band that is avoidable. So the target filter time constant should be larger than some 50-100 ms. The minimum requirement for the filter is to keep out the >20 KHz noise, which is easy.
If the MUX in front of the ADC causes significant charge pulses on switching, one could consider an extra buffer for the 7 V to the MUX, especially if the fast gain adjust mode is used.
For the 34401 ADC, I also have some problems to see how they get there resolution for short conversions. The limited resolution of the µC internal ADC may explain that they still use 10 PLC despite of quite some 1/f noise from the OP27. One method they may use could be reading the auxiliary ADC multiple times and average. This would correspond to a kind of soft ends of the integration time. However this would come at the disadvantage of more time lost in AZ switching. Much of the multislope II ADC is described in US patent 5117227 - though I still kind of miss those details.
-
Any objection to using COG dielectric for the 100nF capacitors in this part of the circuit. Those polyester are big, Can certainly do for C13 as Its value rules out COG but for all other specs seems like its just as suitable
I can lay out for a resistor array, I suppose the question is how much do they cost and please give an exact model and I'll lay it out. (Should it not be a 5K array?)
e.g. I see this and would think its suitable, but you may feel differently, (Try and pick something that is normally stocked)
https://au.mouser.com/ProductDetail/Vishay-Beyschlag/ACASA5001U5001P1AT?qs=sGAEpiMZZMvrmc6UYKmaNaT%2FGf4mI0tTOw5gJ49cnpM%3D
If we need a better ADC for the residue, that is not a problem, Make use of the adjustable ADC Vref in the arduino to get the resolution where you need it. (I know its not the best ADC, but we can make better use of its features)
Give me an idea on what you mean for the slow slope and I can probably lay it out.
Also should that also not imply R2-1/R2-2 / R1-1/R1-2 / R3-1/R3-2 should be using a resistor array to increase matching?
edit: (Moving C13 to -15V makes things a lot easier on my side, that was the only other part left possibly adding noise to the ground)
edit2: Yep, that poly is a big-one
-
For C26 C28 COG caps should be OK too. Even X7R has a good chance to be good enough. They may be even smaller than 100 nF - in theory 10 nF would be good enough, not to amplify 20 kHz. 100 nF is just convenient when using film caps anyway.
C13 should be towards the -14 V reference output , not -15 V supply.
The SMD resistor arrays linked are more like at the low end. They may still need to use the frequent gain adjustment.
Still they are definitely an option for a low cost version, and they should no be so difficult to solder. I currently have individual resistors and rather poor gain stability (well possible my resistors are outside of there 15 ppm/K specs).
I though of something like the MORN series:
https://www.mouser.de/ProductDetail/Vishay-Thin-Film/MORNTA5001AT5?qs=sGAEpiMZZMvrmc6UYKmaNaFuYzg9D8IyI2HjpkrNNLo%3D (https://www.mouser.de/ProductDetail/Vishay-Thin-Film/MORNTA5001AT5?qs=sGAEpiMZZMvrmc6UYKmaNaFuYzg9D8IyI2HjpkrNNLo%3D)
At a little over $3 they are not that expensive and TC matching may be good enough to get away without the frequent adjustment.
AFAIK they could use the same footprint as LT5400 ( better specs, but 2.5 times the price), just without the exposed pad for improved thermals.
There is not need for accurate value matching - so the cheaper versions are sufficient.
The ADC in the 80196 used in the 34401 looks like it could be limiting performance. This is because there is no rundown phase in between and thus more contribution from the auxiliary ADC. In the 34401 the auxiliary ADC has to cover some +-1-2 µs worth of reference current. In my solution the auxiliary ADC only covers some 12 ns, and the ADC can work in hold mode. So it is much less demanding.
The 10 Bit ADC in the AVR is good enough for my version. I don't even need the full resolution - currently only some 200 LSB used, leaving plenty of head-room and tolerance for the trimmer adjustment. The ADC would be a little more critical in a version without the slow slope and thus symmetrical +-14 V reference. If the fast rundown resolution reaches some 100 ns the 10 Bit ADC should be sufficient.
Attached is the schematics for an slightly changed reference part. R19,R21 now set the slow slope. The voltage levels would be some 5% smaller, but this should not be an issue.
-
Schematic attached where?
I should be able to just include both the MSOP and the 0603 array footprints, looks like they fit together pretty well.
Also for the AVR you are using, don't forget that you can use the analog comparitor for any ADC pin, not sure if that helps simplify some stuff for you, but the option is there,
Edit: Resistor Network Change Over done, not that much needed to be altered, just some nudging to make it fit
-
Sorry for leaving out the schematics.
R1-R3 should also be good matching. R3 is even more critical, as it can contribute to nonlinearity.
So an array for R1-R3 is probably a good idea. The alternative would be really good resistors like BMF or good wire wounds.
For a low cost version the fast gain measurement is still an option to compensate for much of the thermal effects.
The analog comparator pins are not that bad positioned. So I have no need to route the comparator through the ADC mux. This would also need to turn off the ADC. So for a very fast conversion the µC internal ADC conversion could no longer overlap the next run-up. At least in my layout the lines to the comparator are not a problem.
For a time I was considering an external comparator because the AVR is faster waiting for an external signal (3 cycle loop) than waiting for the internal comparator (4 cycle loop). However a 3 cycle loops also has downsides and the µC internal ADC turned out to be surprisingly accurate: The ADC readings do not scatter over much more than the range of the time step.
The accuracy of the comparator is nice but with the ADC as the next step not important.
Edit:
There is no need to adjust the asymmetry / slow slope. It is much easier to measure the slow slope and use the measured value instead of a nominal. The same is true for the reference of the µC internal ADC: the ratio relative to the main reference can be measured relatively fast. These internal cal measurements are quite fast (some 20-200 ms). The values are also not that critical, so that an adjustment every month or maybe year / 20 C temperature change could be enough. Only just after turn on is not the best time.
-
Updated as you suggested, It does alter the output voltages closer to +13.4 and -12.2 as far as I can see, do we need to relabel the reference voltages?
And attached is more or less your schematic, but with tiny tweaks, like both op amps use +-15V and R77 is 14.3K to reduce ground current seeing as it only changes the final output by a few ppm.
Edit: For the R1 - R3 array, Is having larger values in parrellel benificial, or would a 4 resistor array be suitable, if there is a benifit would a series/parrellel arrangement for each be beneficial, e.g. 12 resistors in total.
-
Your RN201 - the pin 2 should be connected to pin 1 (not 8 ).
-
The supply current for the OPs would be towards the power ground, not the signal ground. So I don't see a problem using only 15 V for one of the OPs. There is not need for balancing the current to the supply ground.
For the resistors R1-R3 using resistors in parallel / series could be an option in some cases. It very much depends on the arrays and an available values: e.g. the LT5400 is only available in 100 K and 10K (which would be too low). 100 K should work, though 50 K would have a slight advantage with noise. So here 2 in parallel might be an option - though relatively expensive. Populating the 2 nd array is of cause optional.
With the relatively cheap and small SMD networks like ACASA, one could consider using 2 or even 3 in series (e.g. 20 K, maybe 10 K) to spread out heating and get slightly better TC matching from statistical mixing. Parallel connection would be more difficult from the layout and high value resistors may have higher excess noise (thinner film). The 4 th resistor each could in theory be used for power compensation (e.g. heating controlled via an DAC).
NOMCA resistors come with 7 or 8 resistors anyway - so a combination would be natural.
-
IMO can you explain your reasoning. It matches his schematic. And that first resistor does not have a steady state current like the other resistors.
For your LT5400 option what would be your preference 2x 10K in series or 3x 100K in parrellel. The 10K sounds better for thermal matching but less sure if 20K is getting to low.
-
IMO can you explain your reasoning. It matches his schematic.
Doublecheck the wiring of the first two 5k resistors wired to the IC9'th inverting input..
-
- S&H sample time is 1,33us (8 states per 167us as it runs at 12MHz) in fast mode, compared to tens us period of modulation frequency.
It could be they use the modulation patterns (see below) where the S-0 and S+0 are there for some long enough time allowing even a slow ADC to take a sample..
From HP Journal Apr 1989
-
This got me thinking for a moment.
Actuating two switches at once can't compensate input current (from ADC input) into integrator; all you can do is cancel two strong runup sources, achieving the same effect as having both switches turned off.
-
Yep, My mistake, Here is the fixed one with the resistor arrays for the input resistors
-
RN202/203 - I would use 7-2 or 6-3 for the heater :)
-
The 34401 ADc circuit does not have independent control over the positive and negative references, they both come from a single xx74 flip-flop. Otherwise it would make sense to at least turn of the references (or use both together) when reading the ADC on the fly. This would at least reduce the slope - there is still the input signal, so only a factor 3-4 advantage in worst case.
So the 34401 has to do ADC sampling with one reference active. This would add 2 partially counting phases at the start and end of the conversion. This could be a kind of internal calibration factor, that could likely be determined from test measurements (e.g. with zero input), possibly together with the auxiliary ADC scale.
The switching scheme with both reference on or both of has pros and cons. The good thing is that the step in current to the integrator is smaller. So the transient peak at the integrator would be smaller. the negative side is having two peaks and even. In addition there is a small change to get some nonlinearity, if the two cases of getting near zero are not behaving exactly the same, e.g. due to parasitic capacitance that is different. I had a similar case, that cause noticeable linearity problems right in the center of the range: in this range the use of both cases suddenly changes from one extreme case to the other. So even very minute differences get very visible. Anyway this is a simple software question and thus easy to change / fix afterwords.
For the asymmetry part in the references, I start to get 2 nd thoughts about the alternative version with R19/R21: the extra divider has more effect on the difference value. So it depends if this is more attractive. If matching between R19/R21 is very good, its a good way, but in a simple form the single resistor reasonable matching the array may be easier. I think it's not clear if R19/R21 matching is more than 3 times better than R7 to R8 matching in the old case.
For the resistor quality I see mainly 2 cases:
1) really good resistors / arrays, so that one can use infrequent gain measurement, just like used in many modern meters.
2) simpler resistors and a gain measurement for every conversion. This is slower (3 conversions instead of 2) and slightly higher noise (some extra noise effectively added to the reference).
This is a software question and one could still use the 1st. version for fast readings and the 2nd for slower ones.
Case 1 likely would need something like LT5400 or similar quality. If one accepts to use case 2 with the extra reading, the resistor TC is less important. Than the physical size of the resistors may matter, so they don't cool too fast over the 60 ms cycle. So there is slightly limited value of intermediate quality resistors. In the data-sheet of the ACASA resistor arrays I have not found noise specs. If rather poor in this aspect, it could be a deal breaker. So it may be worth a test before a final layout.
When using LT5400 for the integrator, the resistor value choice is a balance between noise and INL. For the 3458 design they found some 300 µA reference current a good value for good INL. The 34401 uses some 330 µA. So I would prefer 100K resistors, either 1 x or 2 x in parallel. Even with 100 K resistors low noise levels (good enough for a LM399) should still be possible. I had tested an earlier ADC version (still on the bread board) with some 105 K resistors - the noise was higher, but still acceptable.
Only 2 x 10 K in series would be on the low side - lower noise, but possibly INL problems as the current steps would be higher. Maybe I should first test such high current level to see if I get visible INL problems. However INL testing is difficult and I still have some problems with switching to do the test.
The choice of the resistors is a difficult one. And good resistors (e.g. LT5400 at some $9) could easily be the most expensive parts. For a low cost version and as a 1st test one can get away with simpler resistors and the extra conversion.
For the layout, i don't think one would need that much cut outs: the LM399 temperature is about constant and thus not so problematic. Everything behind the MUX is not that sensitive to small offsets. I would more consider the option to have either the LM399 or an external reference - e.g. like in the Keysight 34465/34470.
The heat source I would be more worried about is the input buffer. So a few holes or a small cut there may be worth it.
-
What about to layout a single package 4x10k for reference and a single package for 4x100k input, with the pads shape where both LT5400 incl. thermal pad (there are two grades available afaik) and those cheaper networks in similar package would fit? That would be the simplest solution, imho.
These latest DIY designs profit from using "modern" parts (thus making the design simpler), I would not mess with single resistors there.. The final effort needed with using higher TC ratio matching parts is not worth $10 price difference.
PS: could we somehow tell what will be the "noise increase in practical measurements" when using 100k vs. 50k input resistors?
-
..It's got 10-bit ADC and integrator output is routed to one of ADC inputs, confirming this idea. This allows to omit zero comparator and slope amplifier, both being critical components to integrating ADCs..
..I wonder how many bits (or digits of result) are they getting from rundown phase..
While looking at the schematics the output of the integrator has 3 connections:
1. XADIN - via 100k directly from the buffered input stage
2. COMP - it goes to the Asic (U501-A)
3. FLASH - it goes to 80C196, Slow_10bit_ADC0
While the XADIN mixes with integrator's output aprox 1:10 I think it may work as an overload (out of range) indication and the COMParator inside the Asic could be of more comp levels (ie. a "4-8bit Flash ADC" ??).
PS: As the Asic is orchestrating the 7474 toggling (+/-refs) the flash_ADC's results inside the Asic follow the integrator's output with say ~50ns delay..
The ADC value is then made of coarse ADC in 80C196 and the Asic's flash_ADC value (could be 10-14 noise free bits in total).
The Asic has got all its Addr and Data lines wired in parallel with the 196, thus it may write the Flash_ADC results into the memory (an external 32kB sram) and the 80C196 makes some statistics to get even better results then.
PPS: the signal names "COMP" and FLASH" have been chosen by HP to mislead the competitors, it seems :)
-
Kleinstein,
For R19 / R21, 2ppm tracking ratio arrays are about $1.80 in sot23, pick a ratio that is available that suits you and its easy to route in.
e.g. https://au.mouser.com/datasheet/2/414/DIV23-1551440.pdf
My understanding is for most of these resistor arrays, the absolute value doesn't matter at all, only that there relative tracking PPM is as close to 0 as possible, lets say better than 2ppm
As such, we don't really need to lock things to the LT5400, there are tens of alternatives in similar packages that meet that specification, All the use cases are relative, not absolute, it doesn't matter that that 25K became a 25.068, so long as all 3 have, or am I inferring that incorrectly. even your recent respin lets us lock down a fixed ration with R19/R21 instead of R8 being a mystery on the old one.
E.g. for the input resistors, we can use another morna array at 2ppm tracking for a 25K input resistance, I know its not the <1ppm of the LT5400, but in reality I feel it should be sufficient, and leaves us alternatives with higher values in the same series.
https://au.mouser.com/datasheet/2/427/morn-795262.pdf
You mentioned an external reference input, plan out the circuit and I can route it,
And finally added some more tabs to make it a bit more rigid, I was more trying to prevent board flex from upsetting the reference,
IMO, flipped around your resistor, now do we want to run current to heat that resistor, and how do you plan to implement it, or do we just use it to measure that resistor, e.g. use the second amp of the MCP6002 to measure the current from the positive reference and amplify it to an ADC or similar.
Edit: Is it not easier to measure the temperature of the array to better than 1C? this seems like it could be the easiest solution, then pulse some power every few seconds to hold it there. I can place an SMD NTC right next to it.
-
I think you must have some Temperature feedback to keep the temp constant. As I wrote above I was thinking to use the thermal pad as the point where to thermally couple an NTC or a diode.
The big Q is whether it is needed with LTC5400 and its 0.2ppm/K ratio matching TC..
-
While looking at the schematics the output of the integrator has 3 connections:
1. XADIN - via 100k directly from the buffered input stage
2. COMP - it goes to the Asic (U501-A)
3. FLASH - it goes to 80C196, Slow_10bit_ADC0
While the XADIN mixes with integrator's output aprox 1:10 I think it may work as an overload (out of range) indication and the COMParator inside the Asic could be of more comp levels (ie. a "4-8bit Flash ADC" ??).
PS: As the Asic is orchestrating the 7474 toggling (+/-refs) the flash_ADC's results inside the Asic follow the integrator's output with say ~50ns delay..
The ADC value is then made of coarse ADC in 80C196 and the Asic's flash_ADC value (could be 10-14 noise free bits in total).
The Asic has got all its Addr and Data lines wired in parallel with the 196, thus it may write the Flash_ADC results into the memory (an external 32kB sram) and the 80C196 makes some statistics to get even better results then.
PPS: the signal names "COMP" and FLASH" have been chosen by HP to mislead the competitors, it seems :)
XADIN is the same as ADIN, but has reverse polarity (not just buffered signal) and is amplified roughly 1,2x.
COMP is mixture of those two signals 1:12.
I have no idea what is the deal here.
The only IC that really receives the output of integrator is 80C196.
Stitching together results of slow ADC in 80196 and fast ADC in ASIC (we have no idea, if there is really one) IMHO brings more problems than it solves, especially on fast moving target, as is the output voltage of integrator. With +-4LSB INL of slow ADC there is no way of getting reasonable 10 bits, let alone 14 bits.
Since we are speculating, I don't believe there is much more involved analog circuitry inside the ASIC than one or few analog comparators or opamps. There is no reference going inside the ASIC (though the reference goes to 80C196) and whole ASIC is fed by "dirty" 5V rail. COMP pin is sitting between two digital outputs. I can't imagine how would anybody place ADC in here.
-
The noise from the integrator resistors is one of the larger components, but not the only noise source. Currently I get an effective noise level for a single conversion of about 60 nV/Sqrt(Hz) with 25 K resistors. With 50 K (but also a few other small changes) I had down to some 70 nv/Sqrt(Hz). This corresponds to the noise of a 220 K receptively 300 K resistors. The simple resistor noise should contribute twice the resistor value as a noise source. So 50 K rep. 100 K of this were due to the resistors. With 3x100 K resistors the expected noise would at about a 450 K equivalent and thus around 85 nV/sqrt(Hz). This is still very good and normally considered worth 8.5 digits, if the reference is good. I have not yet tested 100 K on the PCB - but it did work with the breadboard version and +-7 V reference.
Jaromirs configuration with 200 K for the input and 2x100K for the reference should contribute like a 600 K resistor (200K + 2x200K). The big downside there is the 200 K for the input and less for the reference. Just going to 3 x 100 K and thus a slightly reduced range (e.g. +-12 V ? instead of +-14 V limited by the buffer) should reduce the noise quite a bit.
So I think a single MSOP foot print with thermal pad for the LT5400 (100K) should be OK. This would also fit (just ignore the thermal pad) a lower cost MORN - 50 K array. Fitting the ASAZA (0612) size array would likely be borderline and tricky, as it is smaller and different pitch.
A second food-print is parallel is likely tricky from the layout, though possible (e.g. other side of the board).
In both cases the lower precision version should be sufficient - I see little need for much better than 0.5% matching of the resistor values.
For the ASAZA SMD arrays, I would consider using 2 x 20 K in series, but to be sure it may need a noise test up-front.
TC matching at the integrator is for 2 reasons: gain drift and INL due to self heating. Gain drift is essentially directly set by the TC matching of the resistors. There is a part from the reference amplification and a part from the integrator. Comparing with other DMMs, I would consider 2 ppm/K acceptable and 5 ppm/K (like with the ASAZA) would be more like on the lower end of the 6 digit DMMs. The INL part depends on the self heating: with these small chips even 100 K cause quite some temperature rise. 100 µA at 10 V give 1 mW and thus some 0.1 ... 0.5 K of temperature rise. With 5 ppm/K this would cause a 0.5...2.5 ppm of INL error. The self heating part could in theory be compensated by applying an additional voltage to the 4 the resistor to keep the total chip power approximately constant. The voltage could come from a small e.g. 8 bit DAC controlled from the last ADC result. So it would not be temperature regulation but a calculated power compensation.
The other mitigating option is measuring the gain more often. This also includes the thermal INL effect as the temperature change is usually slow. With the very low noise ADC to start with this is less of a disadvantage than it was in the K19x and similar meters in the old days.
Without the frequent gain measurement it makes sense to aim for <1 ppm/K range TC matching. With less perfect TC matching I would consider that either power compensation or the frequent gain measurement would be a good idea.
With the 0.2 ppm/K matching of the LT5400 should not need power compensation - due to the 100 K resistance the power is low anyway.
The other positive point about the LT5400 is that it has specified <-45 db current (flicker) noise while the other arrays often only give < -30 dB (actual noise could still be better, depending on resistor value). Form my estimates a -30dB noise level could already be noticeable.
For the 34401 configuration: the XADIN path goes to the inverted input signal. HP used this in some DMMs to reduce the effect of dielectric absorption. So the comparator signal is no longer suitable for an ADC in the ASIC.
My guess is that they called the ADC signal flash, as they may initially have planed with an flash ADC and later changed to the 80196 internal one.
By adding the inverted input signal to the comparator signal, the average integrator output changes less with the applied input voltage. The average integrator voltage is an important factor to set the effect of long time scale dielectric absorption. So keeping this more constant could reduce DA related errors.
However the extra part from the input signal only compensates for the linear part - so the DA part that is avoided is just a small contribution to gain, not INL. Though likely not helping with INL as intended, it still has a positive effect: it reduces the swing and thus allows for a smaller integrator cap and thus less noise for very short conversions and a smaller range for the µC internal ADC.
In my case, I decides against a similar part, as the slope amplifier is shared for the comparator and residual charge ADC. A second comparator for run-up is probably causing more problems than good.
-
0612 arrays are easy to add with the MSOP8, It just conflicts with the option of a thermal pad, as such I may run them under but leave the traces coated, if someone wants to use the 0612 array, then they can just scratch back the solder mask a little.
I can just throw a zone fill under the resistor array to add some thermal mass to it if it really must stay as constant as possible, 24 vias and a plane make for a lot of mass for components on this scale.
-
Another question still floating around - do we really need the composite integrator? Is an OPA140 (for example) not enough?
-
Rerouter:
Be prepared that the final circuit can be somehow different from what are you designing now. Don't forget to leave ways for "alternative plans" during the circuit tweaking and modifying. For example, if you are going to use resistor network, consider also placing footprints for discrete resistors. Bring out a lot of test points, that can be repurposed for components pins soldering. You may need to throw in decoupling cap here and there. If using THT components, design the holes to be larger, so you can resolder components with less risk of pad damage.
-
Another question still floating around - do we really need the composite integrator? Is an OPA140 (for example) not enough?
This is a good question. I think it depends, as even the OPA140 will leave a small approximately square signal at the input. Depending on the reference current and cap this can be some 10 mV or so.
The amplitude should be +- I_ref / (2*Pi*GBW*C). So with a 1 nF cap., 10 MHz GBWand 300 µA Iref this would be some +-5 mV
If the impedance stays really constant with reference switching, that is good resistor matching for the positive and negative side, one should get away with a single OP integrator. With some 0.1% resistor matching the 2.5 mV residual square wave would correspondent so to some 5 mV/14 V *0.1% or around 0.3 ppm of INL error from this effect. With a smaller capacitor the error could go up and down with a larger.
A 2 OP integrator will make the circuit more tolerant to resistor mismatch, as the residual voltage would be only fixed length pulses, that would ideally not cause an error even if the resistor do no match.
There is one more possible point: the OP for the integrator gets a input voltage dependent power dissipation (should be highest with an input near zero) and thus could cause a small thermal effect. with the 2 OP integrator the DC critical OP is the "slow" one and this one does not get mach variable power.
A downside of the 2 OP integrator is likely slower settling to a current step. This would mainly be an issue with really fast modulation that usually comes with a small integration cap. The circuit for the 2 OP integrator is that way that one can leave out the "slow" OP and get the 1 OP integrator as a fall back. So a layout could easily alow for both options :).
So a 1 OP integrator (e.g. OPA140, OPA1641, maybe OPA827 - expensive but faster) is a real option if the resistor matching is good and the integration cap not very small.
-
@Kleinstein: FYI - here is the simulation of the analog part V10 (the digi part is just toggling) of your MS_ADC with some parts added (the ferrite bead in Vee of the 4053) and with OP27 and AD711 as I can see in 34401A schematics. The opamps with their critical params as the universal opamps level3.
With HP's values of the input resistors (30k) and integration capacitor (440pF) and 220pF against GND, the modulation freq looks like >100kHz for, say, <=10Vpp at the integrator, otherwise the integrator's output will be saturated.
Also when looking at the 34401A pcb I can see there the 2 ferrite beads in the integrator's input signal path are "huge in size", compared to the third one (in 4053 Vee). I wish I knew their values :)
PS: the V11 below is with your parts and values in the analog part (40kHz mod).
-
I wish I knew their values :)
Limited amount of wishes can be granted
L401 and L402 are HF50ACB-453215 from TDK - https://www.digikey.com/product-detail/en/tdk-corporation/HF50ACB453215-T/445-6172-1-ND/2465499 (https://www.digikey.com/product-detail/en/tdk-corporation/HF50ACB453215-T/445-6172-1-ND/2465499)
L404 is HF50ACB201209 from TDK - https://www.digikey.com/product-detail/en/tdk-corporation/HF50ACB201209-T/445-6169-1-ND/2465496 (https://www.digikey.com/product-detail/en/tdk-corporation/HF50ACB201209-T/445-6169-1-ND/2465496)
-
The ADC from the 34401 is reused in quite few instrument. I just found in the 34420 schematics that the ferrites are supposed to be 150 Ohms. This is usually the impedance at 100 MHz. So this are not that unusual ferrites. The ones I tried on my board are now 300 Ohms (0805 form factor) and before where some unknown (recycled) THT ones. I have not tried other ferrites yet.
In my case the ferrite at the 4053 is not relevant any more - the 74LV4053 does not use an extra pin for the negative supply.
One could still include the ferrite in case a different chip is used (e.g. HC4053, max4053, DG4053, CD4053).
The 34401 uses a rather fast modulation. AFAIK its around 600 kHz. The fast resolution is also needed to get the resolution, as there is no rundown part. 20 ms integration and 600kHz would be some +-6000 counts from the run up. So even with a full 10 Bits from the residual ADC this would be only some +-million counts. Due to the extra voltage swing when at higher input voltage the full 10 Bit resolution would not be fully useful - likely only some 9 useful bits.
AFIAK the run-up part used 2 patterns with some 400 ns positive and some 1200 ns negative or the other way around. So the actual integrator pattern in the 34401 looks a little different.
I also use two such patterns, but slower: more like 1 µs positive and 24 µs negative or 24 µs positive and 1 µs negative.
For watching the integrator the output of the "slow OP" (OP27 in the 34401 circuit) in the compound integrator is good test-point. It should give am amplified form of the square wave that would be present in an 1 OP integrator.
-
..The 34401 uses a rather fast modulation. AFAIK its around 600 kHz..
..For watching the integrator the output of the "slow OP" (OP27 in the 34401 circuit) in the compound integrator is good test-point. It should give am amplified form of the square wave that would be present in an 1 OP integrator.
This is with 600kHz modulation (simple toggling) and HP part values and opamps.
Green is the OP27's output and the Blue is the AD711's output.
Looks nice :)
PS: HP's 600kHz Mod period could be = 416.66ns + 1250.00ns = 5cycl + 15cycl of 12MHz
-
Jaromir. Give any thoughts on what to include and I will. A board respin only takes a week and while things are digital most of the changes have only taken minutes.
I will be loosening things up with probe points. This is just the framework. Would 1mm through hole test points be enough. Or do you have some pcb mount clip hooks you would like it to cater to.
Discrete vs array gets tricky. Mainly because the footprints cannot coexist like the dirt cheap arrays and the msop type ones. I could leave room on the back. But that will add capacitance and a risk of crosstalk to 3 sensitive nodes. Im not sure how that will effect things.
I prefer SMD for most things because its very easy to do a horizontal transfer of the parts to a new PCB. Equally I'm using Kicad so anyone should be able to modify it to there hearts content. If you want the design files early. Just ask.
-
I had a look at noise data for thin film resistors. Form these, quite some small resistor show high noise that would be not really suitable. so for the Cheap ASAZA arrays I am afraid chances are high they may be too noisy. At least I would not bet on them before doing a noise measurement.
With noise specs they tend to be not very specific (e.g. < 30 dB for whole series, though low values could be better than high resistors).
For the ADC part, especially the resistors in mind here, parasitic capacitance is not that critical. So THT and SMD Footprint combined would be an option. The really critical part is the integrator input on the other side of the 4053.
-
https://au.mouser.com/datasheet/2/427/morn-795262.pdf
And what about the MORN arrays? they have a similar noise figure, I suppose right now you could technically drop in a 100K lt5400 on the same footprint, but in that case I would just need to know what else would change.
-
I should also ask. Those integrator input filter capacitors. What kind of capacitors where you thinking. Its still in COG area as far as value. But if it needs to be poly then so be it
-
For the small caps at the reference voltage amplification COG is OK. They don't even have to be 100 nF, some 22 nF maybe 10 nF should be good enough. More does not help much, though it does not hurt.
For the caps at the integrator COG is also OK. Even if I did not use the cap directly to ground, I would keep it as an option. The choice can depend on the OPs and may need some iterations - so a little space around those foot-prints may be good to easy removal / re-soldering.
The MORN resistor arrays are a good option (already mentioned) and they should fit the LT5400 footprint (just no thermal pad connection). I see no additional change needed - likely twice the capacitance for integration cap, when a 50 K value instead of 100K LT5400 is used, but this does not effect the layout.
To have the option to use an external reference (e.g. LTZ1000 board) it would need something like 2 or 4 pins adjacent to the LM399, so one could fit a 6 or 8 pin pin-header. The extra pins would be for -15 V (or the -13 V reference level) to do ground current compensation and maybe one for a temperature sensor (going to the input mux). For mechanical reasons it may be better to have at least 8 pins, using the extra ones for doubled ground pins.
For the R19/R21 divider I would consider a ratio of about 1:20 to 1:50, likely best at around 1:30 or so. I don't see a good standard value here from the DIV23 series. However this divider is less critical (about by a factor of 20-50). So the small 4 resistor SMD array ACASA as 1K/10K should be Ok, used as 2x1 K parallel to 2x10K in series = 1:40 should be OK.
https://www.mouser.de/ProductDetail/Vishay-Beyschlag/ACASA1001S1002P100?qs=sGAEpiMZZMvrmc6UYKmaNfQm27WGhZG85qVnRW9dDAw%3D (https://www.mouser.de/ProductDetail/Vishay-Beyschlag/ACASA1001S1002P100?qs=sGAEpiMZZMvrmc6UYKmaNfQm27WGhZG85qVnRW9dDAw%3D)
-
So for C11, C37, C37, keep it a prototyping space, Do you have any thoughts on exactly what kind of footprints you want for the integrator cap if not a 0805 SMD, I would assume a 5 and 15mm spaced set of through holes for various types of integrator capacitors
Heres the first part of the options you wanted jaromir and Kleinstein, Again if you think of it, its not hard to layout.
Mostly adding the 7 way header with all the connections I think you would need for a reference combined with bulking up the through hole pads in the area a fair amount and providing footprints for discrete resistors on the back
For the temp sensor, is it something you want for both the LM399 and the LTZ1000, or just on the header, as I can approach it a few ways,
Edit: I should ask why you have the heater enable connection, I just added it as your schematic had it, was it so you could measure the heater current?
-
I would just keep the LM399 reference on board and 4 additional pins close to the 399, so that one can alternatively use an external LTZ1000 reference board. The sensor / read back signal would be just at the header for the external reference.The extra jumper to disable the 399 heater is not really needed - I had it in my initial board, because there were vias anyway.
For the integration cap C11, just a 0805 footprint is OK - depending on the resistors the integrator cap would be something like 1-3 nF COG with no really high demand. Low leakage would be good and thus a guard trace below.
For C37,C17, R20 just a little more space for the tweezers would be a good idea, as one may have to change them.
-
To make clear, I'm just breaking out all these signals so people can play and do whatever they please for the reference, be it removing the LM399 and hooking the LTZ1000 direct to the zener pin provided, or even remaking the whole reference circuit externally and connecting it, there just there for people to play, I should ask the zeners on the reference amplifiers outputs, do they need to be anything special? I doubt it, but doesn't hurt to ask.
For the integrator, I assume I need to Guard both op amps Pin 2 with signal ground, to make the only way current can flow in to that node is via the capacitor? easily done. any other points I should be aware of?
Also been working on the bootstrap supply, I'm assuming based on the power level everything can be sot23 for the transistors, R202 was just me adding a 0 ohm jumper to make the layout more symmetrical for potential alterations.
-
For the input buffer, the original circuit did not work that well. It is a little slow to react to input jumps and needs some extra caps to make it stable with load at the output. So I use a slightly different buffer now, not bootstrapped in the classical sense, but with a 2 nd OP to provide the supply. This version works much better. Attached is an update buffer version, similar to the one tested (omitting one more transistor and driving the other side with the OP). The SOT23 transistors are OK - just keep in mind they can be significant variable heat sources. In the old version the 2 TO92 ones were coupled to reduce the thermal effect.
The zener diodes at the references amplification are not critical - anything from some 3-9 V would be OK. They are there to extend the output range of the OPs. I would prefer some 5.6 V that would also be used in the new version of the bootstrapped supply.
The node at the input of the integrator should not be excessively large, to avoid leakage currents and parasitic coupling (e.g. to the control signals. The signal ground for guarding should be OK. For the 4053 it may be a good idea to have the critical integrator input part at the upper side and the +5 V supply more at the other side. The ground return path at the 4053 is already near ground so I don't see need for guarding there.
The 4053 switch chip does produce quite some supply current spike when switching. In don't think it would need extra decoupling to get a stiff supply to the 4053. It is more like avoiding spikes going out from the 4053 supply and GND pins.
The 5 V supply to the 4053 also should be reasonable stable. The resistor for isolation should not be a problem as the current is essentially constant. However the 5 V regulator position and ground return could be an issue. At least with an HC4053 on the breadboard there was an effect from the 5 V supply to the result (some 1 mV/V). So even a separate local regulator for the 4053 might be an option.
-
I can just gaurd the entire node, makes things easier,
For your schematic, any chance of shifting things around, the references and values are kinda piling over one another.
Hapy to revise that part as its not quite the right shape for a good fit for what I am trying to do.
In the image I have not yet replaced the integrator capacitor footprint, was more concerned about escaping all the digital, supplies and non signal grounds,
I'm also thinking to do the same type of guard ring with the input buffer signal out of the mux, to use it to guard the signal all the way back to the input mux pin. to my knowledge it wont really hurt anything by doing it, even if it doesnt really effect anything, this is really just because a high impedance signal is sitting next to a supply pin on the op amp.
-
I would not take so much priority to guard traces. They are mainly important in a high humidity environment. Especially between the SO8 pins they make soldering rather difficult. So I would only have them where they are not a problem. The main critical path is from the integrator output or later the slope amplifier and the integrator input. A constant leakage current, like from the supplies is not yet a problem. It is more like larger open areas that might collect surface charge - but in this case there is space for a guard.
For the buffer input, it depends on the use whether this node is really sensitive. There are 2 options for a use as a voltmeter:
A) with just the buffer and thus only protection before the mux. To reduce the charge pulse on switching it would better have some extra pre-charge phase and an another auxiliary buffer (also useful for protection) before the MUX. If gain (e.g. 1 V range) is needed the buffer would be changed to an amplifier.
B) the other version would use another amplifier / buffer before the MUX (e.g. LTC2057 or discrete slow chopper amplifier) in front of the MUX. So the signals to the MUX are normally relatively low impedance and one could use 1 PLC even for slow conversions without penalty on the input bias. The input would only see switching of the chopper amplifier, that can be better optimized for low bias current / charge spikes than the full swing (0 V to signal and maybe 7 V in between) switching at the ADC.
From the partial layout I see the 4053 somewhere far a way from the integrator resistors, the integrator and the µC. Ideally there should be relatively short connections to all 3 sides. So the 4053 switches are kind of a central part. With the orientation of the 4053 like in the picture the µC would be best somewhere to the left (maybe bottom). The resistors would be more to the bottom, may be right. The integrator would be best above the 4053. The connection from the reference part to the resistors is not that critical - so this could be longer if required.
A smaller C11 would already simplify things quite a bit. Even if a alternative THT version is wanted (e.g. for a PP cap) something like 5 mm spacing would be sufficient. I think there are also a few connections and 2 ferrites still missing.
I know the layout around the 4053 is tricky, one may consider to swap the gates A and C on the 4053. It takes compromises (e.g. extra vias) somewhere. The signal at pins 2,5 and 12 is near ground (only a ferrite to ground) and thus a less sensitive to leakage. If nothing else helps I would even consider a wire link as kind of local 3 rd layer.
I have changed the buffer circuit file in the last post a little to make it more readable.
-
I would just keep the LM399 reference on board and 4 additional pins close to the 399, so that one can alternatively use an external LTZ1000 reference board. The sensor / read back signal would be just at the header for the external reference.
LTZ1000 via a standard 0.1in 4 pin male/female is something the volnuts would be shocked :)
I've seen the 34470's piggybacked version and it looks so cheap..
You would need a quality connector there, imho.
-
The Integrator output is a regulated low impedance node, that doesn't sound like a critical node, I assume by "later the slope amplifier and the integrator input" That you want me to Guard U4's Pin 2 with signal ground to keep out the noise of the fast switching output.
I'll shuffle things around to get the integrator closer to the 4053, The "Summing Node" in the picture is who gets the ferrite to the integrator input, the ferrite connection to ground will be going off to analog ground along with R23's ground connection, as you are mostly just using ground there for even power dissipation in the resistor array, It doesn't need to share the exact same ground,
I have not yet reworked RN202 into supporting discrete resistors on the back, but that will happen once I get the input buffer and integrator sorted.
-
I would just keep the LM399 reference on board and 4 additional pins close to the 399, so that one can alternatively use an external LTZ1000 reference board. The sensor / read back signal would be just at the header for the external reference.
LTZ1000 via a standard 0.1in 4 pin male/female is something the volnuts would be shocked :)
I've seen the 34470's piggybacked version and it looks so cheap..
You would need a quality connector there, imho.
4 Pins would be difficult - I think it takes at least 5. If there is not much variation in the heat flow, I don't see a really big problem using the 0.1 in headers for a reference. 0.1 ppm of the 7 V reference is nearly 1 µV and it takes thermal gradient in different metals to generate thermal EMF. Pins that are close together tend to have rather symmetric gradients.
It may not be absolute volt nut style, but not too bad either. I don't think the construction in the 34470 is such a bad idea - I don't remember the mechanical connection, that would be more my concern.
Anyway the board would only set the pin spacing and those 2.54 mm are rather common.
For the shielding: the integrator output node and the slope amplifier part are not critical in the sense that they are sensitive to react to small currents or capacitive coupling. They are the possible sources of unwanted coupling. So the guard can be important between the summing node and the integrator output ( e.g. under the integration cap), while a guard between the summing node and the supply is less important. I am not sure the coupling from the slope amplifier is really that bad, but it is at least a possible source for nonlinear effects. There is no need for a guard around U4, if at all more like a shield. It should be enough to keep it a little away from the input side of the integrator and the 4053 to avoid extra capacitive coupling.
-
IMO, what connector would you like to suggest as an alternative, as No matter what you do, there will be Copper - Solder - Some Metal - | - Some Metal - Solder - Copper, So may as well beat the curve and just use solid core copper wire to bridge the gap.
I've bunched the integrator up to make that node much smaller, and added the updated guard trace, I'll also seperatly guard the integrator output with analog ground once I figure out the new placement for the slope amplifier.
For the input mux, you have the GND, Zener and Temp inputs all being low impedance inputs, so if you wanted to do a double buffer Its not a problem, would just mean buffering the 5 other inputs, or putting something else we want on those inputs that is already buffered.
Edit: when I work out what ferrite to go with, I'll nudge it up a little and just connect directly across 4053 pin 1 and 3, leaving the 2-5-12 node to have a similar orientation ferrite positioned across 4-6 but not actually connecting to that ground,
Edit2: for true volt-nuttery I will be removing any silk screening that touches the integrator node or guard trace, just takes some time.
-
IMO, what connector would you like to suggest as an alternative..
I would recommend at least the "rounded precision" male/female 0.1" pins, and use 2 for each signal.
-
so essentially for my part that just means change a 1x07 to a 2x07, easy enough, jeez, If i knew volt nuts where this easy to please....
At a glance none of the reference LTZ1000 boards out there have any kind of methods for mounting, so would you like to suggest what I should provide as far as say some holes for plastic spacers or similar?,
The current cutouts on the LM399 could technically be used to zip tie a piece of foam over it, but it doesnt help people who want to bodge in an LTZ1000,
If there is an agreed apon standard board, I could even plan a space for it, as the current LM399 area is pretty busy, So I was already thinking about expanding it a little. (space as in dimensions and input connection locations)
-
so essentially for my part that just means change a 1x07 to a 2x07, easy enough, jeez, If i knew volt nuts where this easy to please....
They will not be pleased, sure, I am definitely not a volnut and I would consider that as a "suboptimal" solution.
The slots around the 399 - in past I saw volnuts wrote the slots are actually worsening the situation, better to have a bigger mass of copper around the pins (in a symmetrical way) without the slots.
PS: the rectangular shaped 0.1" female/male headers are, imho, not suitable for messing with uV precise signals. The female part is just a simple Y fork shaped, and when messing with the connector for too long (especially when you use only a few pins) it may loose a good contact fast. Those connectors are ok for Arduino folk, and when you insert in once and let it be for years connected.
Imagine you knock on your ADC case and the voltage readings will jump +/- 100uV :)
-
To me it is just a plated through hole, spaced 0.1" apart, what you solder in to it is your own choice, The hole is also suitably large so a multi meter probe could poke it without slipping during debugging after construction. and this is just an option space breaking out all the reference signals so people can do what they like. again, If you have a better suggestion that still fits e.g. a 0.1" spacing but needs some more room, now is when its easy to make room for.
Now the slots I thought where to take stress off the chip, I was weighing up doing something a bit more curvy to let it expand and contract with a twist translation, but that was a bit hard.
So they want a thermal mass around the pins to reduce any differential EMF issues, easily done. again point me at where they discuss it and I can address it,
Knocking on the ADC case causing an offset would not be too big an upset. so long as it settled right back where it started,
Currently the reference polyester capacitor is the heaviest thing in there, and I would guess that will couple some flex in to the PCB, so not quite sure how to marry that with the LM399 if slots are out.
-
So they want a thermal mass around the pins to reduce any differential EMF issues, easily done. again point me at where they discuss it and I can address it,
https://www.eevblog.com/forum/metrology/lm399-based-10-v-reference/ (https://www.eevblog.com/forum/metrology/lm399-based-10-v-reference/)
https://www.eevblog.com/forum/metrology/lm399-based-10-v-reference/msg617201/?topicseen#msg617201 (https://www.eevblog.com/forum/metrology/lm399-based-10-v-reference/msg617201/?topicseen#msg617201)
Knocking on the ADC case causing an offset would not be too big an upset. so long as it settled right back where it started,
It will not settle back with crappy contacts, be sure..
-
I don't think it need the slots around the LM399. With it's relatively long leads the Lm399 is not sensitive to board stress - if at all it is the heat from the 399 that can cause some board stress and long time drift in SMD parts close by. So I would go without the slots.
The integrator looks better - things would tighten up even more if the OPs are rotated clockwise.
A guard trace only makes sense without the solder mask and this is tricky for soldering so close to the pins.
For the references there are a few LTZ1000 board with connectors, especially HP A9 board for the 3458. Another type of connector / pin out is probably OK too. The 34470 type looks mechanical not very robust though. Even just wires soldered to the holes are also an option.
For the signals to the MUX, it may be good to also have some series resistance with the zero reading, just for symmetry.
The temperature signal is not critical - resolution is good anyway and MUX channels are likely plenty.
The 7 V reference signal to the MUX can actually be a little tricky. In some cases the filtered signal would be better than directly from the LM399 - in this case an extra buffer (e.g. OP as a follower) might be beneficial.
The input section with protection and amplifier / gain changing would be a different topic - more like a separate board.
Just for initial test, some resistors as a minimal protection level could be OK.
If at all I would leave possible additions at the inputs for the end, if it turn out that is much space left.
-
Not a volt nut, and again, pick a connector if you prefer it for the purpose. Its just copper at this point, It could be 5x5mm copper pads if you would prefer to spot weld copper - copper if you really want to keep to the same metals :P
Ok, So I read that thread slightly differently, Strain / Stress is not a resulting factor, more the better the thermal isolation of the regulator the hotter the leads meaning any thermal gradients are amplified, so doesn't really rule out slots, just means top focus is that the zener pins are the exact same temperature, so high thermal mass would actually benefit the LM399, the faster heat is sunk from the part, the lower the gradient at the cost of power consumption
So I'll revise him
On to Kleinstein,
I've checked a number of cheap PCB vendors and there minimum silkscreen thickness means what you see is what you would get, a line of solder mask separating the guard trace from the SOIC pins, does that make things easier for you, or still not quite, I'm too used to soldering wire strands to MSOP pins, So I'm not the best general reference for what is or is not easy to solder.
I'd prefer to not rotate the integrator op amps, as the other orientation makes other parts harder to route, what exact parameter are you trying to work by minimizing that node to such an extent?
There will be lots of room left on the PCB, its bigger than 50 x 50mm, and not a good shape for 50 x 100mm, meaning work on a maximum of 100 x 100mm which leaves tonnes of room. This is why I hold no issue with adding connectors, Big through hole test points, or alternative footprints,
Planning the middle left to be AVR and bottom left power supplies, leaving almost the entire right side to input
-
For the references there are a few LTZ1000 board with connectors, especially HP A9 board for the 3458. Another type of connector / pin out is probably OK too. The 34470 type looks mechanical not very robust though. Even just wires soldered to the holes are also an option.
The 34470A's LTZ1000 board connector is a joke. It could easily be the problems with 34470 ACAL (see the thread) come from that connector. I cannot remember whether the board itself is actually mechanically supported other than free hanging on that cheapo connector.
-
For the reference I suggest looking at teardown pictures of Wavetek 7000 and the like, a bare copper ring around the reference on top and bottom layer, though they use a four layer board.
(https://doc.xdevs.com/docs/Wavetek/7000/img/w7000top.jpg)
-branadic-
-
Fluke's pattern:
https://www.eevblog.com/forum/metrology/the-ltflu-(aka-sza263)-reference-zener-diode-circuit/msg2501298/#msg2501298 (https://www.eevblog.com/forum/metrology/the-ltflu-(aka-sza263)-reference-zener-diode-circuit/msg2501298/#msg2501298)
-
The row of hole could already be good enough for an external reference. For mechanical reasons another point to screw down or just another few pin could be sufficient.
I don't think the 34470 ACAL problem is due to the connector. I would more expect things like thermal effects, a software problem (e.g. with temperature compensation) and maybe DA in filter caps. Due to the usually very fast modulation in the Keysight ADCs, I don't think it's DA in the ADC itself.
With a 100x100 board i can imagine enough space for at least a simple input stage:
A possible input part could be an AZ amplifier like LTC2057 with selectable gain of 1 and about 10.
A gain much higher than 10 has limited use, as even with a gain of 10 the amplifiers noise would already be about as high as the ADC noise. Protection for higher voltage and a divider at the input would however naturally take up quite some space, just for the minimum spacing and a relay. Control could be via SPI from the AVR.
-
A possible input part could be an AZ amplifier like LTC2057 with selectable gain of 1 and about 10.
I think Jaromir did a negative experience with the 2057 as the input buffer (input noise with high impedance).
PS:
2057 170fA/sqrt(Hz)
1050 1.8fA/sqrt(Hz)
1152 0.6fA/sqrt(Hz)
-
The LTC2057 has quite a bit of current noise, so it will be a problem with really high impedance sources (e.g. > 300 K). The noise resistance and thus the impedance for lowest noise figure is supposed to be at some 70 K. So it should be acceptable for moderately low impedance sources. The input bias current may need compensation (or possibly selected 2057). It would also need some filtering at the input (e.g. a few 100 pF and some resistors, inductors).
For the use in combination with a MUX an AZ OP may present some extra challenges - there may be additional current spikes if the slew rate reaches the limits. Also input filtering is tricky. Before the MUX at the ADC there is relatively little use for an AZ OP anyway, as one would normally to some chopping with the MUX. So the buffer directly at the ADC can be a simple JFET type - no need for AZ.
There are not that many auto zero OPs for a 30 V supply range available and most (if not all) of them (e.g. ADA4522, OPA189 or MCP6V51) have even higher current noise. The LT1050 / 1152 are for some 15 V. Such OPs would need some bootstrapping for the supply - still possible for a buffer. Due to their high noise there would be little use of gain anyway.
A high voltage (e.g. +-15 V), low noise (current noise and voltage noise) zero drift input stage is a topic on it's own. So far my best bet would be something like a slightly simplified (no bootstrapping for the OPs supply) copy of the input stage of the old Datron 1281 DMM: a discrete slow chopping amplifier in sync with the ADC, so that the ADC also provides residual ripply filtering. Low current spikes may need some trimming.
I consider using the MUX from the input for auto zero even more challenging, as the switches operate with variable voltages and sees a voltage jump. So balancing charge injection is much more complicated than at a chopper with near zero voltage over the switches.
-
To better understand it. The charge injection issue is for charge being coupled into the inputs of the mux or its output to the buffer?
-
Charge injection is acting on both side of the MUX, input and output. How much charge comes from both sides depends on the impedance on both side. With low impedance sources (e.g. less than some 20-100 K) the MUX input should recover before the ADC conversion starts.
With an AZ amplifier one often uses some filtering at the inputs and the extra capacitance can make the recovery slow, so that is may takes longer to fully settle after a charge pulse from switching.
-
I should also ask, for R10 / R11, how much current can be expected as a maximum, I'm working hard to keep any DC currents off the signal ground because the trace that leads back to the signal connector ground point will end up being about 0.1 Ohms of resistance, so it doesn't take much current to make some noticeable offsets. I will reduce this as I can, but there are limits.
I've shielded the output of the integrator node, (no solder mask gap, so just a shield), Are there any other nodes you would want shielded, currently I'm thinking both mux digital pins,
-
R10/R11 are used to compensate the OPs offset and for the small residual voltage to make the OP move. So it depends on the OP U2. E.g. with an OPA172 this would be something like typical 0.2 mV and 1 mV max. for the offset. The AC part could be some 5 mV of so, depending on the integrator current. So the current would be something around 1 µA DC + maybe 5 µA AC.
I would not worry about the DC part at all, as it's constant and thus just an offset to the ADC. The AC part may be more of a problem, as it could in principle be an INL source. At only 5 µA and with a relatively short trace, this should not be so much.
One may consider slightly larger values for R10/R11 (e.g. 2 K and 10 K).
Shielding may be good from the control signals to the 4053 towards the analog part. The signal next to those lines is the near ground (still with a ferrite) signal, that may not be that sensitive. So one could get away without much shielding there.
The point I still have a slight problems with, are high frequency signals on the 5 V and maybe power ground - so the decoupling at the µC and 4053 can be relatively critical - not just the capacitors, but also the layout to them.
The digital signal to the MUX are usually operated during rundown and only once. So there is some time for recovery at the inputs. It's more the supply current spike during switching that could be a possible error source. This is also the reason for the series resistor in the supply I added in the updated input buffer schematic.
-
5uA AC means up to 500nV AC offset, So I'll route him on analog ground, It ends back at the same connection point, just routed completely separate
Attached, means everything thing digital / 5V is shielded to ground, to your liking?
The extra cap and resistor are just for the option of giving the mux a negative rail, e.g. -5V, If you don't use it, you would just bridge it to ground at the regulator footprint.
Edit: this is also why I wanted to null the reference ground current, the original 160uA meant 16uV, the AC component was far lower, but I suspect in your old circuit some of this appeared as non linear behaviour, expecially the slope amplifiers R23, sure it only has 10uA max on average, but it changes with the itegrator value, which I would assume is the worst kind of offset for this circuit.
-
Let me ask why do you plan 2 buffers actually?
There is a bootstrapped buffer after the mux, the another one is planned before the mux.
Considering, say, +/-12V range you may need a single buffer before the mux, bootstrapped one, with switchable 10M or "high" impedance.
With say >12V range you would need a ~1:10 divider, placed after the bootstrapped buffer, made of an LT5400 array, for example 9k/1k or 18k/2k or 100k/10k or 200k/20k, etc.
Input impedance 10M or "high".
The LT5400 could be reused in the buffer's feedback for x10 range as well.
Something like:
10M/High --> bootstrapped buffer ----> LT5400 /10 or 1:1 or x10 ---> MUX ----> ADC input
An idea I did in an another thread (2057 is just a placeholder there, you may place a bootstrapped buffer there, even with +/- 130V Vcc/Vee (?? mind the divider's mWatts), R5/R9 is an LT5400):
-
For the negative supply pin at the 4053, i would consider the series ferrite like in HPs 34401 design. I tired this as a bodge and it did help a little. My guess is the ferrite slows down the switching and this way reduces interference and maybe ringing. I expect a similar effect of a ferrite with a negative supply. The negative supply would likely not be good at -5 V, more like -1 V to get low charge injection.
I would expect R11 to be relatively close to the central analog ground point anyway.
In the layout I have not seen C6 and C14 - these may need a larger (e.g. 1206 footprint), to still get 2-5 µF at some 15 V at the capacitor.
For the general setup of a voltmeter there are several options. I favor the type with 2 amplifier stages, so a little like the Datron 1281 or Kethley 200x, as opposed to most HP meters with a single amplifier.
A single amplifier with AZ switching at the amplifiers input is tricky to get the charge injection / leakage low for the MUX directly at the input. This is more of a problem with my ADC to usually work at 1 PLC may be 2 PLC, os opposed to old meters often using 10 PLC for highest resolution.
The 2 stage concept has a chopping/AZ amplifier (could be just 2057 for a simple version with a little more bias/ current noise) at the input and only than the MUX at the ADC with the extra buffer at the ADC. Like in the 1281 I prefer gain in the first stage. This way the Chopper part does not have to be fast and fast settling is only required for the buffer at the ADC. In addition there can be a filter between the 2 st. amplifier output and the MUX (the Datron design has the filter after the MUX, which looks odd to me). This can help to reduce the noise bandwidth seen for the input signal - to get a better reading with a noisy signal. This is especially practical with the fast AZ cycle, so that settling is not excessively long.
For a long term zero and internal cal one would still need a MUX at the input, but this mux is only switching very rarely and thus charge injection is not an issue.
A high voltage input with a divider is currently not my priority and I would consider the more or less normal configuration with a 10 M divider that is switched with a relay to the input if needed (or for 10 M input impedance). For slightly higher voltages, up to about 22 V, there would be slightly odd looking option: the negative terminal is not directly connected to ground, but driven to about the inverted input voltage (-0.5 times the external voltage). The ADC with MUX is used as a pseudo differential ADC switching between the positive and negative side instead of the simple signal / zero cycle. There are some limitations to this (e.g. for amps measurements), but is should work and can even reduce the INL a little as positive and negative side are added / averaged. It may also allow AZ mode a little fast than 1 PLC.
-
Ok, Ferrite added to the VEE pin, simple enough, The exact supply voltage is arbitrary, by having it broken out, you can tweak it.
I'm also planning to fit 220 Ohm resistors inline with all your MUX digital lines placed near the micro to reduce any noise spikes from them,
yes the supply for the integrator have not yet been flushed out, that will happen, just not yet, as I was more working on the signal chain, They all have there local decoupling capacitors, So I am left with a fair bit of wiggle room on how it will work, Its probably going to end up positioned under U4, Is there a reason U11 is not also on that supply island as well?
I suppose as a question of where things stand, should we be able to get a decent 6.5 digits out of this thing, is there room to make that a higher number, or are we closer to 5.5 digits,
-
The ADC board I have is noise wise (only the ADC) in the 8.5 digit range. The AZ reading (difference of 2 readings at 1 PLC) has an RMS noise of some 600 nV. So this is good for 7 digts at 1 PLC - more would be with averaging (e.g. 50-100 PLC for 8 digits). There is even a slight chance noise could improve a little with better resistors.
With the current resistors in simple AZ mode, the gain stability is horrible - something like 20 ppm/K, so more like 5 digit level. There is also quite some gain-noise, so not just external temperature driven gain variations. The non AZ mode is similar with low stability and also the INL is expected to be limited by the resistors (self heating).
As a work-around I use a 3 conversion cycle, like the Keithley 19x meters uses, so doing a gain measurement for every reading. With this mode the conversions are a little slower (60.6 ms instead of 40.4 ms per reading), but the ADC gain is very stable. I have not tested it but I would expect something like 0.5 ppm/K plus reference ( < 1 ppm/K spec.). With the longer cycle the effective noise is a little higher, but still good.
DNL tests so far look good showing no problem (down to 8 digit level). Also the test for the wiggly part of the INL looks reasonably good (down to < 0.1 ppm level, likely better).
I have not yet done much INL tests for the more smooth part, as I still have some odd effect on switching from one level to another. At 1 PLC the turn over error measured was at some 1-1.5 ppm - which is about where the specs for 6 digit meters are. It looks like it gets better with 2 PLC. The INL test is still the large open point. So far it looks like there is a good chance for 6 digit performance, with hope for more.
One can clearly see the limits of the LM399 reference used. This kind of limits the performance when reading larger voltages. Usind the 3 reading mode adds a little (some 100 nV/SQH white noise) to the reference noise. Here it helps that the ADC is so low in noise to start with. On the other side the extra filtering removes a similar amount of noise, by reducing the effective bandwidth, avoiding aliasing. Anyway the critical noise part of the LM399 is more the popcorn type noise and thus quite some 1/f noise.
Even with a relatively noisy reference the low noise ADC should be useful to do a gain calibration for an amplifier stage / divider in front. The main two parts to upgrade are the resistors (for better gain stability, possibly slightly better INL) and a better reference.
The U11 OP is separate from the supply island for U2 and U4, as this is the critical OP in the integrator and it might be effected from common mode shifts or similar. U2 and U4 are connected, because there can be quite some current through R12 between the 2 OPs. A separate solution is thus not that practical. So the unusual part is more having U2 and U4 together and C6+C14 returning to the central ground like an analog signal and not normal power ground.
-
And if we used the morn array vs the lt5400. The specs alone would indicate much better gain stability. But how much is 2ppm max vs 1ppm max tracking cost in terms of resolution.
Also how low a PPM should the 2 resistor divider in the reference that sets the offset.
At this point it seems like I want the resistors in the reference and the signal resistors surrounded by as much thermal mass as I can throw at it. You said there was no issues with capacitance. So If i flood filled with signal ground around it and fenced it with vias to add even more mass. I would imagine it should be fine.
Im trying to work on the basis of that last resistor in the signal array not being used. Something like a differentiator with a weak bias could alternatively be used to just try and hold it say 2C above ambient. As a way to smooth out any thermal variations.
-
LT5400 is 0.2ppm/K ratio tracking. The divider resistor's TC which sets the offset should be no more than 0.2ppm/K*div_ratio, imho.
-
The ratio is 22.4 with the current resistors. So they should be on the order of 5ppm. Done.
-
Yes the resistors for the asymmetry / slow slope are less sensitive by about the divider ratio. The ratio 1:23 is more on the low side - this could well be 1:30 or 1:40 (just a little slower). My current favorite would be a 4 resistor 1K/10K array (e.g. ACASA1001S1002P100) used as 1:40 divider. Two separate resistors could be acceptably too. There likely also is the option to get away without the asymmetry with a slightly different software and only slightly higher noise (less resolution so that some quantization noise comes in, but not much).
The resistors in the reference amplification part don't need much thermal mass heat sinking. They run at constant power and with about 5 mW per resistor not yet at a very high power level.
The resistors at the integrator get less power (especially a 100 K LT5400), but the power is variable with the input signal. So the TC mismatch could be a contribution to the INL, as a U³ contribution from self heating. 10 V at 100 K gives some 1 mW and thus about a 0.2 to 1 K temperature rise. So the expected contribution to the INL error would be something like 0.2.. 0.5 K times the TC mismatch. So something like 0.05 ... 0.1 ppm with the LT5400 and some 0.2 to 2 ppm with the MORN network (the higher values with 50 K resistance).
The other effect is gain stability / voltmeter TC. Here the main parts are the reference and the 3 sets of resistors. The one at the reference has a slightly reduced weight (3/4) and the small slope divider the extra factor of about 1/23.
-
http://www.vishay.com/docs/60001/mpm.pdf (http://www.vishay.com/docs/60001/mpm.pdf)
They have got 1:20, 1:25, 1:50 ratios, SOT-23, 2ppm/K tracking..
-
The other thing is if someone does want symmetrical. It would just mean not fitting that divider. So the option is already catered to.
Will make it work for both msop. Sot23 and 2 seperate footprints. So far nothing too crazy has been suggested just fancy well stocked resistors. And sheild a few nodes.
So any objections over using something to try and smooth out the heating on that input array. I still have to plan the circuit. But it would essentially be a single op amp servoing its output to keep that chip at lets say 1C now. Above a sensor placed a bit furthur away. Its the lazy oven. To just slow the rate of change of the array.
-
I think Kleinstein's idea on servoing the heater inside the LT5400 based on the "input voltage" is worth of considering. The standard ovenizing the LT5400 with a temp sensor placed somewhere on the pcb may not work well as the thermal gradient (resistors->chip->package->pins->tracks->pcb->senzor) would be large.
-
That would most likely mean a DAC controlled by the micro.
As the power dissipation is a bidirectional non linear amount. If you have an analog circuit for it. I'm willing to add it.
Edit. It would be an analog cos trigonometry function. So there may well be a circuit out there from the analog computing days
-
10 V at 100 K gives some 1 mW and thus about a 0.2 to 1 K temperature rise. So the expected contribution to the INL error would be something like 0.2.. 0.5 K times the TC mismatch. So something like 0.05 ... 0.1 ppm with the LT5400...
How did you find thermal resistance of LT5400? I can't find any specification, just this sentence in DS
For example, if each resistor dissipates 250mW, for a total of 1W, the total temperature rise inside the package equals 40°C.
40K for 1W is 40mK for 1mW, that implies a few ones to few tens ppb of INL influence.
Not sure about the exact numbers.
-
The thermal resistance of SMD parts very much depends on the layout. For the estimate I used the curve on the power limit depending on temperature for the MORN part. This gives nearly 400 K/W = 0.4 K/mW.
The LT5400 data-sheet has a number hidden below the pin diagram next to the maximum ratings. There it is 40 K/W - looks rather low to me and may include using the thermal pad. With this low number the temperature rise would be even lower.
With less thermal resistance and better TC matching the compensation is not really needed any more.
There is no need for an analog calculation of the voltage for power compensation. The µC can do that in SW based on the last result.
A 8 bit DAC (e.g. MCP4901) should be sufficient to get some 98-99% compensation. It would need some gain as the resistors would need some 0-8 V (0-12 V for non AZ mode).
-
for 0-10V across the resistor, its a very simple circuit, for more, it just needs another external resistor.
edit: ideally it would also have a feedback capacitor to slow it right down,
edit: attached a 12.5V version
-
:palm:
-
I do not follow IMO, the circuit shown was for DAC control, to actually simulate a Cosine function is a bit beyond my ability. this would just take the current reading, feed it in to a cosine function and output the 8 bit value to a SPI dac running off 5V, so 0-5V in = 0-12.5V out.
If you have thoughts on a cosine op amp circuit, It can be used. It is just hard to find anything not based on analog multipliers or very specialized chips,
-
When you look at above tables, and my calculations are somehow correct and relevant, in order to keep the LT5400 4x100k resistors at constant T aprox 0.3C above their max temperature spread, you have to alter the voltage at the heating resistor from aprox 26V to 29V for ADC input voltage -12V..+12V (LT5400 Heater Budget B).
-
The reference resistors get a constant power. So they don't have to compensated. In the simple 1:1 case the compensation heater would have to get as much power as the input channel in the normal working range. So some +-12 V would be enough.
The voltage would be something like U_heater = sqrt( U_max² - U_in²).
In an AZ mode with only 50% using the input voltage, the heater power could halve the value, thus 70% the voltage.
A 26-29 V range may actually work, but would result in a higher overall power. I would not go that far, but a smaller offset could i deed be an option: So maybe 10-15 V instead of 0-11 V. This may even work without amplification after the DAC (the 100 K resistor toward the +15 V (maybe +14) and 0-5 V from a DAC that can sink the current.
-
With compensating only the P_IN.
-
The different between 15V and 12V is not enough, so you would need a small amount of gain to compensate the entire input range. Seeing as we are doing that, may as well leave the option and just give full supply range,
IMO, the relationship is Cosine, so for 10V, "12 * Cos((10/12)* 90)" gives 3.106V needed to balance the power.
-
IMO, the relationship is Cosine, so for 10V, "12 * Cos((10/12)* 90)" gives 3.106V needed to balance the power.
Here is an added column with Kleinstein's Heater Voltage Equation (see above).
-
The feasible setup with 100k heater wired against +15V and to an unipolar DAC is with 2.2mW max at the heater, where the DAC's output has to be from 0.167V to 6.282V.
-
It's a bit hideous, but some piecewise linear opamp circuits might work for constant power compensation. (Obviously the first step would be a full wave rectifier.)
It's also plausible to use a servo loop with squaring detectors:
error = ref - (k*ui^2 + k*ur^2)
servo error to 0 by adjusting ur
constrain ur to always be a little above 0
ui is input voltage
uh is heater reference
ref is target voltage - a smidgin over k*ui^2
k is multiplier scaling factor
-
JBB, I don't suppose you could draw that as a schematic, I am not familar with how you would approach that in the analog domain, the DAC approach is still the current method, but I'm curious how it might be done, I was exploring things like a log amp and subtracting the output, but so far no where near
Have done a spacing pass around the ADC area, And I'm about ready to lock that in, leaving the reference and input buffer to get settled. Just have to figure out where to shove the heater amplifier, all components where possible have a 1mm gap between any legs to make it easy to tweezer in and out parts. the silkscreen is stripped off any places that would cross the guard trace, I will include a SMD footprint option for C22 (likely 2 parallel footprints), I'm assuming this being power rail we can use an electrolytic, If not, I will correct it. Also added more thermal mass to the resistor network and planned out some space for 4 discrete footprints on the rear side of the PCB.
I caught an issue with my reference not using seperate sense and force connections, So next tackling the re-spin reference area. after that it will be getting rather close to littering test points and ordering boards territory. So I may aswell ask, what signal points Should I expose as test points
Edit: attached the bare layout, barely anything is routed on the back side.
-
The ground side layout of C6 / C14 still looks odd. this is supposed to have a relatively good connection to FB35 (was R35), as they carry the AC current from the modulation. They should also be closer to U2 C22 can and should be electrolytic.
I think there is a wrong connection from U4-pin6 to U13.
I had a dual OP for U13 with the 2 nd OP used for a test signal (average integrator output) to the µC internal ADC. The 2 nd OP is not really needed. A possible use is a fast temperature reading from a diode.
For the heater the easiest solution from the HW side would likely be one side of the resistor tied to -15 V and the other side directly to an DAC that can deliver up to 5 V, 200 µA (e.g. MCP4901). I would put the DAC relatively close to the µC, so that the SPI lines are not so long. The SPI signal would eventually (e.g. external - reusing the ISP connector) also be used with something like HC595 for other controls (e.g. gain, other MUX controls, relays), but with a different select line.
I have also thought about analog power compensation. Nonlinear analog parts are always tricky however. In principle would be a little similar to RMS calculation - maybe such a chip could be used. Alternatively even a small µC may be an option. Still I doubt it's worth the effort - though interesting, especially for something like a high voltage input divider. Here some DMMs use an extra heater - though I don't know if as power compensation or temperature regulation.
The test points I have mainly used so far are TP1 already there, the integrator output, the NE5534 output, U13 output, the +14,-13.x V reference, possibly both sides of C22, the 4053 control signal for the input signal (convenient trigger source), the buffer amplifier output, maybe the supplies to the OPA145 (bootstrapped OP) in the buffer amplifier.
-
This is with 5V DAC and -15V (100k heater) and Rtheta=210C/W (typical MSOP8 without thermal pad).
Also mind the placement of the resistors inside the LT5400 could be important.
-
If there would be say 4-5 free pins at the Atmega328 you may create a simple resistive DAC (
the resistor's values such it fits the highly nonlinear range best) and use a free opamp as a buffer driving the heater. The DAC's output values based on a lookup table would be enough, imho.
An low-pass put somewhere to filter out the MCU's noise (ie. an ~1nF to gnd at the opamp's input).
Not sure the temp compensation loop via the MCU would be fast enough, however..
The thermal mass is pretty small with those 4 resistors. My bet we talk 10um*10um*0.03um volume..
PS: A 5bit bin DAC with heater (HC245=Atmega328, heater's mW range as in the above table):
-
Yep, schematic capture error strikes again around U13, now fixed up,
Moved C6 / C14 right between U2/U4, there is a direct connection from C22 to both caps, then from there to the op amps, also moved the modulation current ground around for you, currently R23 is also using it, not sure if that is a issue,
C22 is a bit further away still, however the traces between the capacitors are only 35mm long, which seems local enough.
TP2 was placed exactly 5mm further from C11's hole in case anyone is so inclined to use a 10mm lead spaced fancy capacitor
I will write the test point descriptions on the rear of the PCB silkscreen,
-
JBB, I don't suppose you could draw that as a schematic, I am not familar with how you would approach that in the analog domain, the DAC approach is still the current method, but I'm curious how it might be done, I was exploring things like a log amp and subtracting the output, but so far no where near
OK, I don't have a drawing program on this machine, so let's see how we do with some ASCII art.
The basic principle is to control the sum of the input voltage ui squared and the compensation voltage ucomp squared. Squaring can be achieved in the analog domain with multipliers. There is no need
Sum / Difference
+---+
Uref --------------->| + |
| |
| |
+--------+ | | +------------+ +--------+
Ui -->| square |---->| - |---->| controller |---->| buffer |--+--> Ucomp
+--------+ | | +------------+ +--------+ |
| | Maybe PI? |
+--------+ | | Limit to +ve output |
+-->| square |---->| - | Note loop gain will |
| +--------+ +---+ change with Ucomp |
| |
+-----------------------------------------------------------+
Notes:
- If Ucomp falls to zero, there is no feedback signal and behaviour will become erratic
- If Ucomp falls below zero, the loop gain will invert and the loop will become unstable
- The buffer output load isn't constant, which means the buffer will generate varying heat loads (much like the input buffer amplifier, actually). A simple NPN BJT might do the trick
- Analog multipliers might be prohibitively expensive
.
I suggest setting Uref a little higher than the maximum input voltage squared, so that Ucomp naturally settles above zero. Adding a limiter to the controller such that the output is always positive is likely a good idea too.
Doing an approximation in the micro controller might be a better plan.
-
Ok. take 2 at the reference mount, No slots, lots of thermal mass and as low a gradient as I can give for the area within reason
Edit: It was interesting figuring out how to make an equally spaced spiral. turns out 90 degree arc segments, and a small square pattern to offset the center point in a pattern, I've added more via's to the outer ring since, The noise Calcs, and exactly how sensitive given nodes is a bit out of my normal knowledge base, But I can at least try and lay this thing out to a point where the components are the only limiting factor.
-
There usually is no need for crop circles around an LM399. The LM399 runs relatively hot, but with relatively long leads the heat flow in the leads is quite symmetric. Especially a gradient would be mainly constant, so even if there is some additional thermal EMF this part is essentially constant. Enough space to have a cap to protect the LM399 from air flows should be good enough - even that is more than used in commercial DMMs. The other point may be to keep really sensitive parts out out the static thermal gradient around the LM399. This would be mainly the DG408 mux and front end amplifier. The ADC parts are less effected because there is still an offset correcting AZ cycle anyway.
I would also not put to much effort to thermal compensation: the LT5400 should get away without it (down to 0.1 ppm INL level). The MORN type resistors (especially at 50 K or even 25 K) may like it - still it's only some $4-5 more for the LT5400, that also has better noise specs.
The actual resistor element is very small, but the thermal contact on the chip is very fast. So the thermal mass would at least include the substrate. Most of the time the input voltage is also relatively constant, so it would only be the signal, zero cycle to cause thermal modulation and if needed one could follow this.
A few of the µC pins may still be needed: one may want a pin for a separate chip select to control external parts.
It could help to have one pins to do a small shift at the comparator to shorten the rundown a little, by reducing overshoot for the slow slope (PD5 with my board).
To detect overflow of the input amplifier, one may want a comparator signal to indicate overflow. I have not included this with the simplified plan (but already on my board, though not yet tested and used in software).
If an external slow chopper is used, this one may like a ADC synchronous clock (e.g. OC1A).
-
Kleinstein, An extra footprint for the DAC costs nothing, but if its not there, it makes things harder, so better to have and not use than to not have and want. Its like adding that ICSP header, In my early years I killed so many chips flipping DIP packages back and forth from a dev board vs just having the programmer connected via a header and left connected for 90% of the troubleshooting phase.
Half of the reference side it me playing, Its a nice mental challenge having to take so many different contributing factors to mind at the same time, think of it like 3 dimensional Suduko,
if someone wants to suggest more than a 2x7 row of 0.1" pins for interfacing with an LTZ1000, I'm all ears, Breaking the reference area down has revealed a much nicer way of routing it now that a few things have been changes since I first put it together. letting me space things out more nicely, Included IMO's SOT23 package, and shorten some nets that where annoying me.
The overflow comparaitor, that would just be a basic window comparator on the buffer output when it gets within say 0.1V of its output limit? or did you have something better implemented
And based on what you said, will ensure any unused AVR pins get routed to a header for easy access along with some landing pads for bodge wires.
-
I suggest to avoid crop circles, but use a circle of copper around the reference. Your spiral will do more harm than doing anything good, as it forms an antenna, leading to unwanted coupling.
Don't forget to put a 100nF cap (0603 or 0805) at the zener of LM399 between the legs, as done e.g. in Prema 5017. This is how I would do it, but without the slots.
(https://www.eevblog.com/forum/metrology/lm399-based-10-v-reference/?action=dlattach;attach=568093;image)
Maybe the best way would be to put the reference, no matter which one you use, on an extra piggyback board. This way you can select for the best reference performer to put in and can compare on the same ADC board which works best.
-branadic-
-
For the thermal compensation just the DAC on the SPI bus is a good idea and this is about it. With connecting the other side of the resistor to some -15 V one does not even need amplification. The MCP4901 is fine driving 200 µA and gives sufficient range (e.g. 0-4.8 V).
The overflow comparator is just a simple window comparator: LM393 comparing against fractions of +-15 V supply with both outputs wired together with a simple level shifter.
I would more like test the output of the input amplifier (e.g. LTC2057 or discrete chopper). Still a bridge / resistor would be good to allow a later change of mind. The other signals to the MUX would be more fixed test signals (7 V, 'temperature', filtered amplifier output, ground (for reference), optional 2 nd GND from terminal/amplifier, ... ) that should not result in an overflow.
Signal filtering could be relatively bulky (e.g. 1-3 µF range PP cap(s)).
As the board is more like testing the ADC part, I would consider the LTC2057 and just 2 gain settings good enough for a first test. A discrete chopper might still need quite some tweaks and not sure it's really better than the AZ OP. I would be more tempted to include the inverter/floating negative terminal to test the extension of the range to some +-20 V. This needs direct connection to the amplifier (gain setting), so it's a little tricky to do external.
-
OK, I don't have a drawing program on this machine, so let's see how we do with some ASCII art.
The basic principle is to control the sum of the input voltage ui squared and the compensation voltage ucomp squared. Squaring can be achieved in the analog domain with multipliers. There is no need
Sum / Difference
+---+
Uref --------------->| + |
| |
| |
+--------+ | | +------------+ +--------+
Ui -->| square |---->| - |---->| controller |---->| buffer |--+--> Ucomp
+--------+ | | +------------+ +--------+ |
| | Maybe PI? |
+--------+ | | Limit to +ve output |
+-->| square |---->| - | Note loop gain will |
| +--------+ +---+ change with Ucomp |
| |
+-----------------------------------------------------------+
This looks a bit like mark-space ADC modulator, see Solarton patent US3942172 from 1974
They used this scheme in most of their voltmeters.
-
I would recommend to "review and finalize the schematics v1.0" first, as the number of add-ons grows :)
-
Well it is iterating towards this rev being done, the digital and the power supply don't really have any special requirements other than fit on the board and keep away from the analog stuff, my only recent addition has been some output resistors for the digital signals to reduce the coupling near the MUX's
so for the input buffer, include a jumper and test point to inject a lower voltage than -15 to just the bootstrap area, done.
I've removed the spirals, and am just doing the final cleanup of the reference area before sliding him in to place,
Right now things have mostly settled as far as the schematic goes, the reference and ADC took some prodding, but that has not changed in a way that requires a significant layout change, It was more a case of technical debt, I packed it up nicely before things where settled on the reference area and did patchwork as they kept changing.
Edit: I can make a piggyback board easy enough as all the signals are broken out, the main question that seems to be hard to get an answer on is what is the agreed upon normal board for the LTZ1000, If I had to go piggyback, then I should cater to both (wont be on this rev)
-
Perhaps the LTZ board design is something for higher revisions of your board, as it will certainly start a long discussion on the very details. The first rev of your board shall show it works fine at 6.5digits and LM399, mind there are still several untested concepts outstanding..
The connectors - I think the rounded precision 0.1in male/female with TWO 2x7pins (or 2x10) sockets at both opposite edges of the piggyback pcb may work fine, provided you would use say 4 pins for each signal and the power lines. 2 connectors give a pretty sturdy mechanical support for the board as well.
PS: The clearance between the two boards will be around 5mm with the rounded precision connector - doublecheck..
-
The LTZ board would be a thing for later. It's just to have the option to use an external reference. I don't think it would even take that many pins. There are essentially only the 2 connections for the reference voltage are really critical (e.g. use 2-4 pins each), for the rest, like power 1 pin should be OK.
We try our best, but chances are there the board would need some bodges or even a re-spin anyway. As boards are not that expensive anymore, I would not overdo the planing and better leave some space for bodges than squeezing everything to make it a handheld meter.
I don't think it takes so many vias at the LT5400 footprint - this is not a high power part with very low junction to case thermal resistance. There is little need to have the copper area much lower thermal resistance. More vias mainly make soldering more difficult. Just space for 3 small THT resistors right over the array also gives some copper area (and test points).
The same is for the LM399 just a really closed circle on the top (or bottom), some 20-25 mm OD is well good enough. A first board is more about the general working, not such tweaking. The LM399 has it limitations (popcorn noise) anyway.
At least with OPs like OPA145 and OPA172 the buffer amplifier is working rather well to the lower supply. The weak point is more at the positive supply.
-
removed the vias under the array, It was more intended to remove any gradient effects from surrounding parts and acting as shielding (recommended in the datasheet for the array) , the part does not actually electrically connect to the plane, meaning the thermal load should not be too high when soldering.
Room for 3 through hole resistors over the array footprint, easily done, any other places you want me to cater to through hole parts?
Also you want test points on both sides of each array resistor? done,
So currently the test points for each section, any more to add?
ADC Area:
AVR ADC1
AVR AIN0
Slope Output
Integrator Output
R79 - Integrator input offset
Signal Ground
Reference Area:
-15V
+15V
Signal Ground
Zener
Input Array:
+Ref
-Ref
Buffer Output
And the 3 points for the other side of the array
Input Buffer:
Mux Output
Bootstrap -
Bootstrap +
-
Input area put together, I suspect I will have to pretty it up a little, leaving just the AVR / power supply which I have grouped up, but not yet worked in to the board
-
AFAIK the thermal pad on the LT5400 should ideally be soldered to the extra copper. I have no experience with this and could imagine manual soldering could be tricky and the preferred method is using solder paste. This detail may be worth checking before the final touch.
The input buffer part is thermally one of the bad guys: it has power consumption depending on the input signal. So I would prefer to have it not too close to the ADC - part. It may still be OK with good resistors (e.g LT5400), but this is one of my concerns. I think thermal coupling here is more important than from the LM399. The LM399 is hot and likely the highest power part, but it's constant temperature (though variable power and thus variable gradients).
The central ground point at the input connector is a little odd, as it makes the distances quite large. The more logical point would be closer to the center.
R61 should go to normal power ground - this is just for a zener bias, so not at all critical.
Getting clear about the schematics (except of pin swaps) is normally a good point before doing the layout. Especially the input area still has a few options / unclear points and maybe parts that are optional depending on the space available. One point, that I mentioned before was a buffer for the 7 V signal (to get the filtered 7 V without loading it by charge injection).
Another point is a possible amplifier in front of the MUX, as this needs a ground connection of some kind.
The UART connection is also an open point there it may be good to add some more supply filtering, as the UART would likely be used during conversions.
-
Changed the LT5400 footprints to exposed pad, I have also exposed a mask area to heat with a soldering iron to melt under the pad if you really are limited to an iron, If you had to use this method, I would recommend getting the pad hot, apply some solder to the pad, clean it back with some wick and try and hold it molten, and only then tweezer in the part,
Buffer is variable heating so keep away from the temperature sensitive parts, check, Its part of why I went a big overkill on the array thermal situation, the vias and copper will reduce the amplitude of any thermal gradients, but I will shift it around,
The input connector is the star grounding point for all the measurement side of things because it is that point that all measurements to the outside world are relative to, this was part of why I was going a bit out of my way to keep certain parts of the grounding seperated (I went well overkill in that respect and can lower it to 4 connections) So my thinking was, if any variable current is sent down a shared connection back to that master ground node, you get a measurement offset or noise. To this end I was thinking of changing it to a 2x05 Connector to give each external signal its own ground connection.
That ground point is then connected back to the power supply like a more conventional ground star point because any offsets there do not alter the measured voltage, everything is relative to that point.
R61 falls under that point, But if you want I can route him back to the power supply star point,
I am building the circuit up in easy to rearrange chunks, anything with a silkscreen square and label is what I would call "Locked down" as in, I'm happy with it and should not need to do any major changes to, just possibly shift the chunk around. At present I have not done any pin swaps, and for the analog mux's I'm happy that I will not need to,
The AVR is a bit uglier at present but that is more to do with where the ADC pin is, and no matter how I swap it is not going to help it, the digital outputs are actually ideally positioned and ordered, all grouped at the edge of the micro, routing out the spare pins will also be a bit awkward, For the DAC, I would recommend using 14, 15 or 16 for its chip select
I'm laying out function blocks that I can slide about with very little change to the interconnecting wires, e.g the buffer is only 5 connections out of the block, If that bias was to +15V, it would be 4, so dragging over the entire block and moving it does not cost me much in terms of layout, its more the building of those blocks that take more time. This is why changing things is not hard, even for bigger changes it is just shift the block off the board, make the changes to that block then slide it back in,
There is lots of room left, We agreed to a max of 100x100 just to support almost all dirt cheap PCB suppliers, If you need more room for the Input, I'll just rotate the reference, input mux and buffer clockwise 90 degrees, should have shown the entire board, but space is not at any kind of premium, So throw down any options you want to cater to, The +7V signal to the mux already has 100nF tied to it, so it would appear to be much more immune to charge injection than any other signal.
The UART will end up very close to the Power supply at the moment, likely going to be towards the bottom left of the PCB, I was intending it to just share the AVR ground and 5V, but if you want it run seperatly no issue, was just thinking to close the loop, (The micro is sinking the TX current) As its an isolated interface all I need to do is prevent any capacitive coupling, I was thinking to flip it to the attached image style to make it more in line with normal UART,
Edit: for AVR pin PB2, I would recommend leaving that disconnected or only an output, if he changes state during an SPI transfer it kicks the SPI over to slave mode.
-
For soldering the LT5400 with an iron, the describes method was one I considered too.
Anyway, I already have my version of the board, that is so far reasonably working - though with low quality resistors and thus the work around mode.
For the UART Tx it makes sense to have the extra MOSFET (alternatively BJT) to shorten out the LED in the OK. This way the supply current does not change much.
I would even add more filtering for the current (Split R96 and add a large cap), or consider a PNP + 3 resistors as a simple 1-2 mA constant current source.
The extra inversion from the FET may help, to get the non inverted UART signal out - so possibly directly connecting to an µC on the output side.
Which package of the AVR is planed ?
-
So far I have just been using your same DIP package, As a QFP package would put it on par as the hardest part to solder so far used, and QFN can be stupid to get good reliability out of, especially if people lack hot air for the LT5400 thermal pad,
My own motivations for this circuit are for slower high resolution sampling for an SMU type power supply plugin, so this laying out process is helping me narrow down a lot of the specifics,
For the UART, it is active low, so the inversion is taken care of in the current configuration, The current noise would be about 1mA, As I was already planning to route analog 5V and ground on the AVR seperatly, Is there any other benefit to keeping the digital supply so low current?
Edit: alternativly instead of opto's, If current variation is an issue, we could use a digital isolator for about the same cost, and have the option of much higher data rates, https://au.mouser.com/datasheet/2/368/si841x-2x-datasheet-1398047.pdf (Si8422AB-D-IS cost is $1.50)
-
Soldering the package with the exposed pad - I do QFNs with hot air, as it works fine, imho the other option would be to design a 3mm dia via at the exposed thermal pad and try to solder it from the bottom (after you soldered the top pins in). The 7mm2 x (1.6+0.3)mm of tin will increase the thermal mass too..
Optocouplers - they have to support >115k2 baud, imho..
FYI - Isolators - I've stocked the 100Mbit ISO776x ones.
http://www.ti.com/isolation/digital-isolators/products.html (http://www.ti.com/isolation/digital-isolators/products.html)
PS: below one of my boards with an via in the exposed thermal pad
-
Other isolators are OK too and could be even a little simpler with less current. The 6N137...139 opto couplers are also fast enough. With 20 ms conversions the UART needs some 7000 Baud minimum speed to send the data during the next conversion. I currently use 9600 Baud and some 100 kBaud should be OK with the optos. With a little compacter data format (some bits are currently fixed and short time also means less resolution) this would be OK for 1 ms conversions.
1-2 mA current pulses from the UART could still have a little effect. The 4053 does react to variations in the supply voltage (I have measured some 1 mV/V for the conversion result this was still on the breadboard, but that is about order of magnitude to expect.
Also jitter from the µC could have an effect - this should be well below 1 ns. The 34401 even uses the external flip-flop for synchronization, but the AVR seems to be really good in this aspect. Variations in the supply could have an effect at that level.
With the AVR I also have the difficulty that the SMD packages are really small and make the routing difficult - negating some of the small size advantage, while the DIP package is more on the large side, but makes routing easy. The trace to the ADC may be longer, but it is not that sensitive.
-
You may use small sot23 5V ldo voltage regulators for each critical part of the ADC (ie one for AVR, one for switches, one for optos, etc.) and the master regulator will be for 6-8V (there are 7806/8 afaik, or use an LM317).
-
1-2 mA current pulses from the UART could still have a little effect.
In my ADC I arranged timing so that CPLD sends UART data (four bytes at 31250 baud) via optocoupler during integration cap zeroing and is quiet during runup and rundown.
Perhaps one may add timeslot for data transfer, when no measurement takes place. At 115200 baud this will not introduce much of time penalty.
-
What about to run the avr at 20MHz? It will give you a nice 50ns clock period and better match with higher baudrates.
-
A high baud rate (e.g. 500 kBaud range) and sending during a not so critical phase is a option. This could for example be the waiting time before starting the µC internal ADC or the µC internal ADC actual conversion time. As I currently send out raw data there are some more bits to send.
Really need would be something like 19 Bits for the runup and fast rundown (these two points are easy to combine with a simple integer multiplication), 5 to maybe 6 bits for the slow rundown and some 8-10 bits from the µC internal ADC. So this is rather tight to get into 32bits (may work for short integration times as than the runup part is reduced). It is a little more than the actual resolution (some 28-29 bits) because there is some additional headroom (e.g. for comparator drift) and the parts generally don't have a power of 2 range.
5 Bytes at 500 kBaud take some 100 µs. This would be probably acceptable, as waiting time is already in the range of 50 µs and for a 20 ms conversion some extra 50-100 µs are not that bad. I currently use some 150 µs for an auxiliary reading anyway. As a side effect the result would be available earlier and not delayed by some 20 ms.
If the output side is not a normal PC, one may not be limited to standard baud rates.
-
After Jaromir had kindly posted his cpld code I replaced his uart with "SPI" for fun (there is the code in his thread). With SPI and that 100MBit isolator you may read the 4bytes out in 1-2usecs, for example.
PC: with a serial/usb dongle it has to fit the serial/usb chip's baudrate, the PC baudrate does not matter..
With original PC's rs232 you may set the baudrate to a nonstandard one too, imho (matter of driver).
-
If the 4053 has such extreme sensitivity to its power rail then that for the most part rules out the lm7805. It might have to become an lm7808 with some local LDO regulation.
My thoughts for a higher data rate was to reduce the dead time spent sending the data. I would guess a faster clock frequency would also speed up the conversions slightly. But do not know what the trade offs are.
-
The supply to the 4053 can be rather sensitive. However this is essentially an offset only, so only short time (e.g. 60 ms) variations (e.g. noise) are a real problem. The 7805 is not very good, but should be still just good enough, though data from different source may vary. At least the version I have is good enough - but I think it's a very low noise variant (though not low TC :().
An extra regulator for the 4053 is definitely a possible option.
Instead of an extra LDO, I would consider a divider from the LM399 and OP as buffer.
The 4053 uses only little current (e.g. 100 µA range). So no extra 8 V level needed. 15 V should be Ok to start.
I currently have a 16 MHz clock - thus not that far from the 20 MHz maximum. A lower clock gives a slightly slower conversion, though not very much. A relatively high clock rate would definitely help for a version without the slow slope - this one would be faster in conversion as the slow part would be saved. The version with the slow slope gets a little fast with a higher clock rate, but not very much (about 100-160 CPU cycles should be the clock dependent part). I have tested 10 MHz and 16 MHz so far, some 4 MHz should still be possibly - with a little extra time as the modulation would also start to slow down. A lower clock speed gives less power consumption and likely less RF interference.
P.S. : I checked my old values. The effect of the 4053 supply was a little smaller, more like 0.2 µV/mV. This was also with low reference current and the not so good HC4053 version. So time to measure it again.
-
I should ask how you where planning to implement the slow mode. Was that the 2 combined references idea ir ssomething different.
-
For slower conversions (more than 1 or 2 PLC) I would use just averaging of many conversions. This method is also used in other meters to keep the 1/f noise down. The 3458 uses up to 10 PLC integration at a time and more with averaging. AFAIK the DMM7510 uses 1 or 3 PLC and than averaging. Noise wise shorter conversions have the advantage of less 1/f noise, but the disadvantage of more time lost to the rundown, more switching effects from the MUX at the input (this can be especially important in a 1 stage amplifier concept like the 3458) and possibly limited resolution (not in my case for 1 PLC).
So to get data at let's say 1 reading per second, this would be alternating between 1 conversion for the input signal and 1 conversion for zero for 24 repetitions.
For the case with not so good resistors there is an alternative method using 1 PLC each for signal, zero and the 7 V reference. This gives a little more noise as less readings (e.g. 16 for 1 SPS) are averaged, but also better accuracy as the ADC gain is measured essentially in real time. This can method compensates much of the resistor TC effects, but adds some noise. It is attractive mainly for longer conversions.
I should ask how you where planning to implement the slow mode. Was that the 2 combined references idea or something different.
I don't know exactly what 2 combined references case you had in mind. There are a few DMMs (e.g. Keithley 2001, 2182, 2010) that use 2 references, probably (quite sure for the K2001) in a way of 1 low noise reference for the ADC itself and a second long term stable reference. However I think this is more like a bad idea, as this makes the ADC gain measurement noisy, often adding more noise than possibly saved by a separate low noise reference - just the filtering of the LM399 reference should be more efficient.
Using a frequent ADC gain measurement with separate reference is likely the reason for the Keithley 2001 to have relatively poor noise performance but good linearity and stability.
I don't know if I mentioned it before: there would be an option to use 2 LM399 in series to make it a +-7 V reference and use +-7 V for gain measurement. Compared to just 2 x LM399 in parallel it has some slight advantages if the resistors are not as good. However this would be a odd combination of cheap resistors and dual reference. So I no longer think it is worth it.
It would be an option for relatively high current 1N829 or 2DW232 references, if one really want's this way. This option would use the "-7 V" tap of the reference amplification.
If a better reference is really needed, the next logical steps would be 2x LM399 in parallel (moderate effort and same SW) and than a LTZ based reference, even if with not so good resistors (e.g. like 34470).
-
Sorry, bad wording on my part, I was more thinking along the lines of using a mixture of +13.4 and -12.2 by switching on both at the mux to get a lower average voltage, or alternating them at variable on time to get a specific average voltage, but if that adds too much noise I can understand,
Starting to work out how your software is working and filled in the gaps of what you had loosely assigned for the other AVR pins, was the comparitor shift part (PD6) intended to offset the comparator by more than the residue? or just to create an offset so you can edge out some more resolution?
-
The slow slope is by using both (+13.3 and -12.x) references together. As this is only used for a relatively short time (e.g. 10-16µs) the slightly higher noise is not a problem. The main contribution is from the difference (e.g. 13.x to -12.x), the sum (together with leakage currents) is needed as a correction term anyway. With the intentional asymmetry its also used for the slow slope.
The optional shift at the comparator (resistor between PD5 and PD6) would be there to reduce the overshoot, e.g. from reaction time of the µC / comparator / slope amplifier. This is not for more resolution but for a speed up, especially if the asymmetry is chosen small. Without it it currently takes the slow slope some 10-20 µs to make up the overshoot. Less asymmetry would be more to center the range better and get less effect from the resistors, not for higher resolution.
Pure numerical resolution is high enough, up to the point of the option of not using the slow slope at all and just rely on the fast rundown and the µC internal ADC. This could still give some 27 bit resolution and thus more than the noise limit of some 24 bits. So especially in an implementation with an FPGA/CPLD with a little more timing resolution the slow slope / asymmetry is not needed.
-
I suppose the next question is 24 noise free bits of resolution over what scale, I presume +-12.5V so about 1.5uV / bit, and other than the reference, what effects are setting that noise limit other than the reference, or is he our main lynch pin, (as more of a curiosity)
a raw value of 27 bits is exceptional, places it in the ballpark of 7-8 digits,
For PD5/PD6, shall I include the footprint anyway?
ADC0, the temp sensor, what part of the circuit where you hoping to measure,
ADC2, is the Peak overflow for detecting input buffer out of range, or something else?
-
The noise is relative to the +-10/12 V range. The measured noise I have is at some 0.6-0.7 µV RMS or some 4 µV_pp for the 2x1 PLC conversion. Much of the noise is just Johnson noise of the resistors. Some noise is from the OPs, especially U11 and in the current setup some noise is from a source I don't know. My suspicion is a little on excess noise from the resistors and maybe higher than normal popcorn noise of U11. Some jitter effect is possible too.
The numerical / raw resolution better than the noise limit essentially avoids the quantization noise. It's also useful for faster conversion, as the resolution goes down linearly but the noise only goes up with the square root. So at 1/16 PLC the raw resolution would be down by 4 bits, while the noise limit goes up by only some 2 bits. So the extra resolution may get use for faster conversions.
To a large part the ADC noise is white noise, while the reference noise is mainly popcorn, 1/f noise. So the comparison is a little difficult. It depends on the measured voltage (and due to the 1/f nature also the integration time) wether the dominant noise source is the ADC itself or the LM399. The ADC noise is low enough so that when measuring a 2 nd LM399 reference, most of the noise is due to the 2 references, even at 1 PLC. At 10 PLC it should be at about 1-3 V where ADC and reference are about equally important.
So in quite a few cases the reference is limiting. Still at low percentage (e.g. 10-30%) of the range the ADC is limiting.
On my board the temperature reading (via MUX) is near the input resistors and 4053. In a case the exact position of the sensor may not be that important - just not too close to the LM399.
The peak overflow detection would be for the input amplifier before the MUX or alternatively (if no such amplifier) at the buffer at the ADC. Some DMMs have the overflow detection at the protection - though this would net detect out ouf range peaks in lower ranges. It depends on the use whether the extra overflow detection is needed.
-
And for the buffer, Q4 and the op amp handling the upper half of the bootstrap would be the variable heating? just figuring out how to best shift things about
-
a raw value of 27 bits is exceptional, places it in the ballpark of 7-8 digits
I'm sorry to be 'that guy', but bear in mind that having reasonable 7 or 8 digits of result needs more than resolution. I think it's perfectly OK to aim for 5 or 6 digits for starters, learn the limitations and problems along the way, measure the real outputs, then look for better performance. From 5 digits on, each additional digit brings exponential growth of expenses, both material and development time. And we are talking just ADC itself, you need some frontend too and finally results verification. There is a long way from ADC to finished instrument.
Proper verifying INL - for example - of "just" 6 digit voltmeter is not simple task unless you have real 8 digit voltmeter with proven parameters and appropriate calibrator at hand.
If all you need is ADC for your instrument, you may also take a look at recent single-chip ADCs, like AD7177, ADS1262 or LTC2380, develop/verificate it at the same time as this multislope ADC and compare the results. I believe it will not bring you much of time penalty and you'll gain a lot valuable experience.
-
Yea, managing the expectation of "diy makers" is important as many projects, even after a large effort spent, finished abandoned.. From my experience prototypes always work nice, until you start to mess with a final "production". As I wrote earlier, 6.5digits with 399 and the AVR firmware people could "enhance and cultivate" easily would be one giant leap for mankind :)
-
My only real requirements are about 5.5 digits repeatability over an hour period, and an integrator stage under my own control, so any more above that is nice. Even if I where to use those all in one ADC chips, most of the layout knowledge over laps significantly. and there datasheets imply I would likely have to use an external reference anyway, putting it in a similar pricing window, So a nice learning experience if nothing else.
The main thing is the way of thinking about how 1 part of the circuit can influence others on a scale I have not had to visualize before, e.g. thermal gradient EMF and how small variances are enough to upset things at distances of multiple centimeters due to differential heating causing offsets,
-
At the 5.5 to low 6 digit level thermal effects are not yet that critical, unless something goes really wrong. The LM399 should be relatively simple to use and is not really sensitive.
Those ready made ADC chips also have there downsides and tricky points. For high performance one has to care about the termals and RF interference too. Another difficulty is the need to start with a 2.5-5 V reference. These tend to be more drifty than the LM399. Those ready made chips are quite good up to the 5.5 digit level and for very fast conversions (e.g. more than 1 kSPS) there is little chance to get it better with a DIY mutislope or similar solution. However for the slower conversions a DIY multi-slope converter can be competative, and the 6 digit range does not need magic. For the noise level even the 8 digit range is not that difficult.
The difficult part is more with the INL due to those effects like thermal interaction, nonlinearity in resistors, secondary effects on charge injection and so one. But this is more like the fun part to learn about. INL testing is also a really difficult topic, but at least a partial test is possible. A full test at every possibly reading is not possibly anyway for a slow high resolution converter - it just takes too much time. For the tests it helps a lot if the noise is low. So it's nearly required to aim for a noise level considerably lower than the expected INL errors. To avoid the quantization noise it also help to have a numerical resolution better than the noise level.
The numerical resolution (quantization limit) is one of the least important properties, as long as it's good enough. The very high resolution (e.g. some 2-3 bits more than the noise limit) is more like an easy way to avoid the quantization noise, not a important property by itself. In the combination of rundown and residual ADC, high numerical resolution comes essentially automatic and with very little effort.
An ADC with numerical resolution higher than the noise limit and more INL error than the noise limit is kind of normal for high resolution ADCs. The numerical resolution and noise part are relatively easy. The main uncertainty is how good the INL will turn out. It is possible to calculate / estimate some effects up-front, but there is a chance to miss some.
The limit for a DIY solution is the INL test that can be done without even higher grade gear. Some such tests, like the turn over test and the simple sum of 2 voltages can be done relatively easy, down to about 1 ppm level, possibly even better with many repetitions.
-
The are some parts of the ADC that change with input value, that may cause INL errors, e.g. the integration capacitor voltage (DA, leakage / offset causing drift), and the Input resistor self heating (which we now have a method to try and compensate for) below are my thoughts on how me might be able to try and reduce the influence of each, but happy to hear how you where planning it.
I suppose as a silly thought, we could use the DAC heater to instead measure how changes in heating create offsets while using ground as an input to remove any heating
For charge injection, we could likely measure it, have the input mux grounded, so the net current flow is rather low, switch the input, and measure the amount of charge by the known amount of capacitance on one side, and the resistance on the other (essentially an RC to ground) as the 4053 always operates at roughly 0V, this should be fairly consistent for all 3 channels. you then measure the other injection by switching the input off, and then back on, complete the same measurement but subtract the first measurement.
The error current from the op amp - inputs can be directly measured by disconnecting all inputs from the integrator and measuring with the ADC for the direction and magnitude of the offset, you could also perform a normal conversion and measure it that way if the amount was significant enough, this would give the error current that would have to be subtracted from all inputs, You may be able to isolate what factors are causing what by also measuring it by the offset voltage caused over the input resistor with the input grounded. (e.g. 4pA * 100K = 0.4uV), which arguably puts it well under the effects of the op amps input offset, so I guess he will be the dominating factor... guess that becomes a direct measurement of the offset voltage then, convert to a charge per unit time and subtract.
The linearity over the entire integrator range Is fun, technically the EMF effects of U2 from getting warm when the clipping begins should be cancelled by U11, which I assume is an unintended bonus, C11 being a COG really should be as ideal as things get, most spec sheets show almost no difference with temperature or voltage, I suspect there is on this scale, as at this point input resistor heating and the bias of the integrator are taken in to concideration, I suppose a ramp up / ramp down set of tests could be used to try and find any kind of non linearity with the capacitor, going up for X time, then down for Y time crossing the comparitor line should be equal to going up for half X, down for Y and up for half X, I suppose by flipping around the ratio you could determine where any voltage based deviations may sneak in,
The slope amplifier, with as high a Gain as it has, I'm not sure how much of an influence self heating causes, it would be easy enough to measure, just leave it clipped for variable amounts of time to heat the diodes more or less, R12 gets warm and will be changing value unless we spec him low PPM it will offset the low level gain of the slope amp, R13 really only gets heated by the diodes
U13, nothing really gets hot, and the power of all the parts remains pretty stable,, cant speak for how your using the other half currently, but if it was unused, should not be an error source.
I suppose a fun thing about the test points is you could technically measure the ADC's own performance,
Power supply rejection should be OK for all op amps included, but possibly bad on the MUX,
Crosstalk from the digital signals should not be an issue as they are shielded to ground and have resistors to limit there slope.
I would ask what other sources of INL where you thinking?
-
A good think of the multi-slope ADC is that many off the non ideal effects just produce an offset or gain error. So charge injection by itself only causes an offset current, that is essentially constant and this represents an offset. It would only be the changes in charge injection that really matter, especially those not linear dependent on the input. It still helps to have a constant number of switching events and even the same switching sequence for the 4053 - it is only the timing that changes, not the sequence.
Similar the input offsets and input bias of the OPs just add a slight additional current and thus result in an offset.
U2 doing all the work and getting signal dependent heating while U11 sets the precision is a nice side effect and could be now one of the main reasons to keep U11.
Input offset of U11 would not matter as it's one a general offset and corrected with a zero reading. One without an AZ mode the offset drift of U11 would matter. However the non AZ case is likely not that important for us, as it's only a thing for very fast measurements.
The capacitor C11 does not even have to be very linear. Most of the resolution is from balancing charge going in an out. So it's more about leakage and DA that do really matter. Only the last fre bits from the C internal ADC need linearity of the capacitor to maybe an 8 bit level. I have no doubt the cap linearity is good enough. Also G0C caps have a relatively low TC, so the scale factor for the ADC does not change much with temperature. C0G in this respect is better than PP, PS and maybe even PTFE.
The DA usually is composed of 2 contributions, a slow one with a time scale of some 1-10 seconds and a fast one with a time constant in the 1-10 µs range.
The effect of slow DA can be estimated quite well theoretical and it should be low, if the modulation is faster than some 5 kHz (I currently use some 40 kHz). Such a slow modulation is not attractive anyway, as is would cause a slow rundown. The slow DA effect should correlate with the average integrator output voltage and I have measured this as an additional test signal. I could not see a correlation down to a really low level. Due to the extra waiting time before the final µC internal ADC reading, the fast time scale DA should not have an effect in my AC version. With MKS type caps it's visible on the scope but still not much effect on the result. Still no reason to use anything else then C0G for the cap - at some 1-3 nF these are cheap anyway.
The heating of the 5534 OP should not be that critical. AFAIR 1 LSB of the µC internal ADC corresponds to some 5 µV (changes a little with resistors and integration capacitance used) at the integrator output. A more critical point could be heating of the diodes. In an early version with a higher values for R23 the diode temperature had a noticeable effect on the gain of the slope amplifier. Still not relevant for the result, but visible in the scale factor for the µC internal ADC. With 47 K I see no more effect.
If power consumption is an issue on could also use a different OP (e.g. OPA197) for U4. The noise is still low enough.
The other half of U13 is currently used as a buffer for an auxiliary signal, reading the average integrator output voltage to another channel of the µC internal ADC. The alternative use is for a temperature sensor via the µC internal ADC.
Other INL sources I thought of are:
The residual voltage at the integrator input combined with a resistor mismatch between R1, R2. This could be an issue with the 1 OP integrator.
Nonlinearity in the settling of the integrator input voltage - possibly an issue if switching comes before the input is settled. Changing the minimum delay should effect this.
A effect of input signal on the temperature of the 4053 or the supply to the 4053. Settling of the 4053 supply after a switching.
Capacitive coupling from the input buffer to the integrator, so that switching the MUX effects the rundown just in progress. No such effect is visible. Charge injection at the MUX and input current of the buffer effecting the 7 V reading. This is a possible reason to have a buffer for the 7 V to the MUX.
Capacitive coupling from U4 output to the integrator - this could effect the settling of the integrator depending on the current slope amplifiers gain. I test this with additional capacitance and the effect was minimal even with a lot of coupling.
So there are a lot of possible paths for small errors. Many of those I though of turned out to give no significant error.
Measuring the ADCs own performance is indeed a tricky part. For a first self test I did the comparison of two slightly different run-up versions with different modulation frequency. Ideally these two should give exactly the same result, but quite a few of the errors related to the run-up phase (like capacitive coupling, integrator settling, ...) should be different and also DNL errors from combining the parts should be different. So the difference of the 2 conversions is good test for much of the conversion. It is easy to do and low noise and thus fast and can thus test a large range.
-
Been calculating the maximum error terms,
E.g. the worst case error current on the integrator assuming u11 was a OPA145 would be (150uV / 25000) 6nA for your earlier design, which means the drift rate for the current cap would be up to 2.73V / second. and that would offset the input charge the same every time, but the slope back to 0, being a variable length will be effected based on how long it took, so it would be an offset/conversion time
The actual input bias / offset currents of both op amps is swamped out by that offset. even with a 100K input resistance, it reduces the maximum drift by 4, but still dominated by that offset voltage.
If you are applying that offset multiplied by the total conversion time, then yes its a simple offset.
Could an OPA189 be a better alternative? most of the specs seem equal or better, the bias current then becomes the dominant factor, but ends up being a lower error current for the circuit in total, around 0.137V / second,
Edit: Ok now I see, that would instead appear as an offset in the +- ref voltages, and can be resolved with a fixed offset there, because the error current effectivly stops in that moment between resistors, a very high input resistance when the integrator is open circuit means a very tiny current for a given offset voltage, getting the hang of this math, still would appear an option
Edit 2: now I partly understand your modulation, now just trying to interprit the assembly for exactly how you approached it.
-
Ok, Iq of the OPA189 would have it running a lot hotter so will give him a miss for now, at present the ADC could be dissipating about half a watt of heat, so I'll be trying to do some shuffling to keep components aligned to the gradients, such as R12, D1, D2 and D10, If they are oriented so there longest side is towards U4, it should remove any EMF there, R12 will be getting warm, the normal spec for an 0805 package is about 120C/W junction to board, so about a 5.4C rise, the diodes do not really generate any significant heat, its R12 that takes the brunt, I would assume a larger value for R12 would add too much noise?
-
Under normal operation the voltage over R12 is not that large. Usually more like some 2-3 V_RMS. This would be some 2 mW. The high voltage would only be reached at the extreme input voltages. Even than the parts around R12 are not really temperature sensitive. R12 already has higher noise than the NE5534 and the OPA145 in the relevant 50 kHz range. Still this higher frequency noise is not yet critical - it will get important for short conversions like 1 ms. The diodes are also no more that temperature sensitive - if at all one could consider using other diodes than 1N4148 - ideally lower leakage, but still not very slow like many low leakage diodes (e.g. t_rr should be less than some 100 ns, but no need for the 4 ns of the 4148). The slight temperature effect (still more like slightly higher noise) was there with only 2 diodes or to high a value for R23.
I have not measured the total power consumption, but some 0.5 W is a reasonable number and not extra high. Still it depends on the OPs and the specs for some OPs (OP07 and NE5534) have quite some range for the current. If power is critical the OPA197 / OPA202 could be used instead of NE5534 / OP07. One could also run the µC with a slightly lower clock (e.g. 8 MHz, maybe 4 MHz).
There is limited use for an AZ OP for U11. It would help mainly with the non AZ mode. However zero drift is not only from the OP but there would be similar acting effects from leakage currents at the 4053 and drift of the resistors. A 1 ppm drift of the resistors R2,R3 would act like some 12 µV of offset. So even with the LT5400 arrays chances are the resistors would still give more drift than an OPA145. In normal auto-zero mode the offset is compensated by taking the difference. So OPs input bias, most resistor drift, leakage of the 4053, charge injection from the 4053 and similar contributions are corrected.
AZ OPs tend to have higher noise than the OPA145, the low voltage noise ones have quite some current noise.
With the final µC internal ADC reading at a fixed time, even quite some drift of the integrator would not cause a problem. In an earlier version I have tested a BJT based OP (TLE2021 with typical 25 nA bias) for U11, with no real problem. With just the classical comparator based rundown a high drift could causes a little of DNL error, as the time to stop varies.
-
In schematics I noticed output of integrator being shielded. There is nothing wrong with it, but shielding/guarding the input of integrator (inverting inputs of U11, U2) makes more sense to me. Output of integrator has fairly low impedance, while input has much higher - so lower leakage and/or coupling can disturb the integration process. Leakages from DC nets will display mostly as offset, while dynamic leakages (control signals or integrator output) could induce INL or noise.
If you are going to shield/guard input of integrator, connect shielding/guarding to analog ground, the same potential as noninverting input of U11.
-
Integrator output was sheilded to ground to prevent it from injecting noise into other parts of the circuit.
The slope amplifier output was also considered and I may go back and sheild that aswell. As they can behave as antennas for the modulation frequency. however the slope amp output is already 20mm away from anything sensitive, So he should be fine without
The integrator input is guarded. To remove any risk of variable leakage. This connects to the non inverting of U11 as he is the precise one of the pair. The input resistor connection to the mux may benifit from the same. But it was easier to just sheild all the digital and power supply connections to ground.
-
OK, makes sense. I was confused by the schematics, your explanation makes it clear.
-
Checking over the input buffer heating, the main 2 parts that need to stay close to cancel out is the bootstrap op amp and Q4,
With a 25K input resistor they would then have a variance of 12mW, with 100K input resistors there is only a variance of 3.5mW,
I'll rearrange things so they are closer together and away from U12, this way we can call the input buffer about as thermally stable as it will get.
It is not the paired transistors vs the second op amp that make the difference, It is more that U12 has to source for positive voltages and sink for negative, with a current that depends on the input voltage
As such I'll nudge U12 around aswell to keep its inputs, and the input resistor as close as possible to being inline with the expected thermal gradient.
I would ask if there are any alternative picks for that OPA172 that may be a little lower supply power. e.g. the OPA171, it has higher noise, but for this case I do not know if that would matter. or is the bandwidth and slew rate critical.
Edit: Total system power consumption is not what I am chasing, more reducing the slope of any thermal gradients now that I have reached thermal emf considerations for layout.
-
For the auxiliary OP an OPA171 might be Ok, it's just a little slower. I had problems with input current spikes and thus used the OPA172, as it's also a candidate for U2 and I had some at hand. A high slow rate is nice, but I don't really know how important.
Another lower power alternative would be OPA197. I don't think the constant power consumption background should be such a big deal, as it would only cause a constant temperature field. It's only the MUX that could be effected by a constant gradient and produce a small offset from this.
U12 current consumption and noise matter. The OPA145 looks like a good choice in this respect.
-
As you where saying R12 was a large noise source, could we flip the structure a little to reduce it furthur, e.g. relying on our own clipping schottkey diodes for the ADC and AIN, instead of having to use them on U4, or does this cause other issues I am missing,
-
R12 contributes a little to the noise in reading the residual charge. However at 20 ms conversion and not too large an integration- cap the noise is not yet relevant. It only gets relevant for much shorter conversions (less than about 1 ms) and a little more gain before the µC internal ADC.
The noise from reading the residual charge the noise source are U11 with some 7 nV/sqrt(Hz), R12 (at 5K ) with some 9 nV, the NE5534 with some 4 nV+some 0.5 pA*5K = 2.5 nV. The relevant frequency range is about 50 Hz to 50KHz, so mainly the higher frequency part and not so much 1/f noise. The relatively slow ADC and thus reduced BW also has some good sides. ;)
The shown alternative circuit with the clipping at the OPs output has about the same noise level, with a 5 K resistor in the feedback part. The easy way to reduce the residual charge noise is to use a smaller integrator cap and faster modulation. The software side could still run a little faster. One could also still reduce the value of R12 a little more, so some 3 K if really needed.
In theory there is the option to use a resistor and 2 JFETs or 1 JFET and 2 resistors/2 diodes to do a kind of current limiting for R12. Noise wise it could help, but I don't thinks it is need and it many result in some gain drift with temperature.
For the 20 ms conversions the relevant noise is more like integrated low frequency noise (e.g. 25 Hz range), like from the resistors R1-R3, noise from U11 - this time with a noise gain of 2, the buffer. For a 20 ms conversion this noise part is about 10 times higher than the residual charge noise.
-
R12 will be getting warm, the normal spec for an 0805 package is about 120C/W junction to board, so about a 5.4C rise,
Acccording to this paper it's not that bad - 38C/W for an 0805 film to end cap + a little bit for the solder joint to the PCB (an extra 1 C/W perhaps).
http://www.cetti.ro/v2/download/materiale_bibliografice/Thermal%20Management-SMD-Vishay.pdf (http://www.cetti.ro/v2/download/materiale_bibliografice/Thermal%20Management-SMD-Vishay.pdf)
And this one suggests only 23C/W
https://www.vishay.com/docs/53048/pprachp.pdf (https://www.vishay.com/docs/53048/pprachp.pdf)
Quite a big difference between the two so no calculations to three decimal places please!
[EDIT] Of course you'll need sufficient copper and board area to avoid compromising those numbers significantly.
-
Another day another PCB re-arrangement, moved any variable heat loads away from the input resistor and adc as much as possible, means the ground run is a little longer, but grouped up all the quiet grounds and ran them as a nice 0.8mm thick trace back to the input plug.
Shifted the ADC around U4 a little to make things more ideal for the heat gradients it will be seeing. added some extra guarding because its not easy to shield the slope output and gave each input its own ground pin, The temp diode will end up close to the input array. and the gap on the top left will likely be where the heater dac footprint ends up,
-
Hi,
Would some one please brief me on the progress on this interesting thread?
-
The new placement is odd: where is the µC supposed to be, especially when in the relatively large DIP case ? . The old placement looked more logical. If one insists in having the cental ground point at the connector, the connector should not be that far away from the areas where the ground is needed (the integrator and reference part).
The connection from the 4053 to the µC is quite a critical one, as there is quite a bit action.
With likely some space left for optional parts / extensions, it may be good to have some of the spare space more close to the MUX / input side, where some optional parts could be used (e.g. extra buffer/amplifier) before the MUX), possible buffer for the 7 V to the mux.
-
ali_asadzadeh:
Both Kleinstein and I designed their versions of MS ADC; results are in two separate threads:
https://www.eevblog.com/forum/metrology/diy-6-5-digit-voltmeter/ (https://www.eevblog.com/forum/metrology/diy-6-5-digit-voltmeter/)
https://www.eevblog.com/forum/metrology/diy-high-resolution-multi-slope-converter/ (https://www.eevblog.com/forum/metrology/diy-high-resolution-multi-slope-converter/)
and now Rerouter is trying to redraw Kleinstein's version to KiCad.
Any particular detail you are interested in?
-
Kleinstein mentioned for his design he was suffering in small ways due to iterative changes in his design since he first laid it out, So I felt I would have a crack at it to nail down all the things one has to consider for an ADC of this resolution (not quite accuracy just yet, INL tests have not happened to my knowledge), So I'm refining it down into a Kicad PCB, If you want the design files, Just PM me. once it reaches a near completion state I was planning on just attaching to this thread,
Right now I'm trying to flip around the main analog chunks to make everything nice, with the least chance chance of non linear effects that may hurt its performance, and adding optional / alternative footprints and test points to make it easier to diagnose and expand on.
Placed in crude locations for the micro, UART header and where the power supply will likely end up, also left some room in the buffer area, Again its very easy to slide these blocks around, did not even use Undo from your post.
Edit: For the 7V buffer and secondary input buffer, what op amps would you suggest and I will add them to the schematic with some breakable jumpers (so if you dont use it, it is bridge by default)
Edit2: I can rotate that input mux and buffer stage so the ground is smaller, but that means moving a heat source closer to the input resistor, if that is fine I can pack that in closer.
-
jaromir Thanks for sharing, Big thumbs up :-+ :-+
I wonder if there is good explanation on how the ADC works? Also How to add ohm and current measurements into the design?
-
There is some description in the other thread on how the ADC work. However it is a bit scattered over several of my posts.
Adding resistance and current measurement is in principle no different than with other ADCs. With the ohms mode one could consider to measure the voltage over the DUT and reference resistor in series to the DUT separately. This would like the old Keithley 19x series DMMs. With not so good resistors at the ADC this could give better results, as it does not rely the gain stability. Anyway a good voltage measurement and likely the current reading would need an additional amplifier before the MUX.
The MUX at the ADC is mainly meant to provide the AZ modulation for the ADC and gain correction back to the 7 V reference. In DMM, I would prefer to have a separate amplifier in front, as the fast 1 PLC mode causes quite some charge pulses to the inputs. So the MUX inputs are not really suitable for high impedance sources. Already at a few 100 K settling gets noticeably slow and it would need extra delays.
For a buffer to the 7 V reference the OP07 could be still acceptable, for higher performance one could consider something like OP177, OPA202, ADA4077 or maybe LTC2057 - they usually still use the same pin-out and no need to use the offset adjust pins.
For the input buffer (or possibly amplifier) the LTC2057 should be OK. There are not that many AZ OPs for 30 V supply to choose from and others like ADA4522, OPA188, OPA189, MCP6V51 have even higher current noise and input bias. If the input current is a problem, one could consider compensation (e.g. with a photo-diode across the inputs).
-
The 7V buffer, is that direct, or still using the RC to its input?
Also for the input amplifier, you could still use a bootstrapped AZ amp with a lower supply voltage, for the other inputs, if it was fleshed out with current (electrometer) and resistance (same as before with some current sources), that would be after an amplifier anyway, so its really only outside world voltages that may need buffering.
Would also like a walk through on exactly how the modulation works, Jaromirs Thread begins to touch on it, but doesnt really explain the specifics. and I'm still pretty new at interpreting assembly. my current mental picture is closer to a delta sigma, but that doesnt quite seem right.
https://www.eevblog.com/forum/metrology/diy-6-5-digit-voltmeter/?action=dlattach;attach=749595;image (https://www.eevblog.com/forum/metrology/diy-6-5-digit-voltmeter/?action=dlattach;attach=749595;image)
https://datasheets.maximintegrated.com/en/ds/MAX328-MAX329.pdf (https://datasheets.maximintegrated.com/en/ds/MAX328-MAX329.pdf) - Low charge injection alternative for the DG408 that is pin compatible.
https://datasheets.maximintegrated.com/en/ds/MAX4051-MAX4053A.pdf (https://datasheets.maximintegrated.com/en/ds/MAX4051-MAX4053A.pdf) - Low charge injection and lower leakage alternative for the 4053 that is pin compatible.
-
was doing a deep dig through the LM399 thread and came across "Mickle T"'s schematic for his own "8.5 Digit ADC" the overall design seems fairly similar wondering if there is anything that can be gleaned from it that could help get around some of the current limitations..
Direct link to the post, however most of it is in chinese, https://www.eevblog.com/forum/metrology/lm399-based-10-v-reference/msg589601/#msg589601 (https://www.eevblog.com/forum/metrology/lm399-based-10-v-reference/msg589601/#msg589601)
-
I would think about using the buffered 7 V from the filtered point at C13, not directly from the LM399.
For the input buffer before the MUX a bootstrapped AZ OP is an option. At least a buffer is relatively easy, it gets tricky to make it an amplifier with a bootstrapped supply for the input. It is complicated, but possible.
The Bootrapped buffer could look like the one Mickle suggests. The rest of that ADC circuit is relative close to the Solartron DMM, with a few improvements due to more modern parts and the simplification of using only one modulated reference. As there is resolution only from the comparators the numerical resolution is low and alone from this reason that ADC type is slow (I would expect it to be just a little fast than the Solartron original). So more like a few seconds for 7 digits and maybe 1 minute for 8 digit resolution. The noise level is also relatively high. It is a different kind of ADC, so not that much to really copy from there.
The modulation part during run-up in my ADC version is rather similar to a first order sigma delta ADC. AFAIK Jaromirs design is not that much different in the modulation - just slightly different timings, but nothing dramatic. My integrator would probably be OK with the modulation Jaromir used and vice versa. The main idea is to have a fixed frequency and switch sequence, switching between the positive and negative reference. Only the time when one transition is done changes depending on the comparator. One can call this a 3 step sequence with fixed positive (e.g. 1 µS) phase, fixed negaitve (1 µs) phase and comparator dependent phase (positive or negative) for some 20 µs. This version of the modulation / feedback is about as simple as it can get. I initially had a slightly more complicated version, but this one did not work out so well.
For the switches: I have tried the max4053 - it worked but not as good as the currently used 74LV4053. The LV4053 is also low charge injection, but likely faster and with less current pulse on the supply. Charge injection on it's own is not so bad, it would be only variations in charge injection that cause trouble. A possible alternative version to test would be DG4053E - it may have some advantages from low leakage and low charge injection. So far I have tested: (ST) 74HC4053, (Ti) CD74HC4053, HEF4053, max4053 and (Ti)74LV4053. The HC4053 from ST was worst and the LV4053 best, and the other about similar in performance. However the differences were not that large and the chips may have different weaknesses - it is not just one parameter, more like a good compromise. Also different bathes may be different a little.
For Jormirs design and the one from Mickle, the switching is at the reference side and thus needs higher voltage switches. There charge injection may be less critical at first sight, but it still effects the buffer for the reference voltages. It is not just the switch IC, but also the amplifier and layout that is important in that respect. The max328 are also much higher on resistance and this makes matching more critical. Leakage is not really critical, especially not in the configuration of Mickle.
-
jaromir Thanks for sharing, Big thumbs up :-+ :-+
I wonder if there is good explanation on how the ADC works? Also How to add ohm and current measurements into the design?
You are welcome.
Having functional ADC is first step to make complete multimeter, since both current and resistance can be "converted" to voltage output, being measured by voltmeter (ADC).
For current measurements you need current to voltage converter. It can be done as trivial as single resistor - from Ohms law you obtain linear relation between current and voltage. If you have 1Ohm sense resistor, 1V of voltage drop implies 1A of current. This is good fit and often used for higher currents - think of miliamperes to a few amps. For lower currents it is often useful to employ transimpedance amplifier, with benefit of nearly zero burden voltage.
Resistance can be measured by using constant current source to feed unknown resistance and measuring the voltage on it. Again, Ohms law dictates linear relationship between those. If you opt for 1mA of test current, 1V of voltage on tested resistor implies 1kOhm of resistance.
Theory may sound trivial, but as usual, devil is in details. Sense resistors and current sources need to be stable enough to fit expected precision bill. As usual, every digit on instrument mean exponential growth of component prices and technical hurdles that can be otherwise ignored on lower resolution meters, like thermoelectric voltages.
Another example is input buffer/amplifier for voltage measurement. This is project by itself. Looks innocent, but the need for switchable 10M (that is the simpler part) and 'very high' (usually higher than 1 or 10GOhm) input impedance while having decent noise and offset in +-20V input range makes the design choices complicated. Usual 'throw LTC2057 at it' approach gives horrible results. Problem leads to less common design topologies, such as bootstrapped supply amplifiers or discrete JFET autozero switches, both bringing fairly heavy baggage of other difficulties to solve.
-
Usual 'throw LTC2057 at it' approach gives horrible results.
People talk about LT1052 (bootstrapped) as the input amplifier (I think you too), and I wonder what is a better opapmp there - the LT1052 is 0.6fA/sqrt(Hz) input noise current, two external capacitors, and, afaik, 335Hz chopper freq.
The 1050 is 1.8fA/sqrt(Hz), no ext caps, and 2.5kHz chopper freq.
I would consider the 1050 even with the 3x higher noise, but higher chopping freq, which may interfere less with, say, up to 1000 measurements/sec..
-
For the bootstrap supply op amp at the input buffer, you mentioned it needed a high bandwidth, however C27 is limiting its corner frequency to only 67Hz? Is this intentional?
-
AFAIK Kleinstein's ADC has 1PLC integration period, the same goes for my ADC, I'm not sure where 1000 measurements/second figure comes from.
LTC1052 does indeed good job with both current and voltage noise and is good candidate for bootstrapped input amplifier - at least that are my plans, I will see shortly how it works in reality.
LTC1050 is cheaper.
-
I wonder if he is talking about trading resolution for sample rate, e.g. 0.05PLC
-
You are welcome.
Having functional ADC is first step to make complete multimeter, since both current and resistance can be "converted" to voltage output, being measured by voltmeter (ADC).
For current measurements you need current to voltage converter. It can be done as trivial as single resistor - from Ohms law you obtain linear relation between current and voltage. If you have 1Ohm sense resistor, 1V of voltage drop implies 1A of current. This is good fit and often used for higher currents - think of miliamperes to a few amps. For lower currents it is often useful to employ transimpedance amplifier, with benefit of nearly zero burden voltage.
Resistance can be measured by using constant current source to feed unknown resistance and measuring the voltage on it. Again, Ohms law dictates linear relationship between those. If you opt for 1mA of test current, 1V of voltage on tested resistor implies 1kOhm of resistance.
Theory may sound trivial, but as usual, devil is in details. Sense resistors and current sources need to be stable enough to fit expected precision bill. As usual, every digit on instrument mean exponential growth of component prices and technical hurdles that can be otherwise ignored on lower resolution meters, like thermoelectric voltages.
Another example is input buffer/amplifier for voltage measurement. This is project by itself. Looks innocent, but the need for switchable 10M (that is the simpler part) and 'very high' (usually higher than 1 or 10GOhm) input impedance while having decent noise and offset in +-20V input range makes the design choices complicated. Usual 'throw LTC2057 at it' approach gives horrible results. Problem leads to less common design topologies, such as bootstrapped supply amplifiers or discrete JFET autozero switches, both bringing fairly heavy baggage of other difficulties to solve.
Thanks for the feedback, I have other questions and suggestions too.
what about the AC voltage and current measurements? what's the sample rate of your ADC? can it be done for getting samples and calculating RMS based on the samples? is it fast enough? or do we have other options to measure AC precisely.
Also I have an Idea ;) can we put the whole ADC PCB and it's parts in a thermal chamber and hit them up, and regulate the temperature there? Say for example 65C degree I mean using cheaper parts for the Reference and precision resistors and op-amps, use normal parts but keep them at a certain temperature, something like a 3D printer bead as the heating element, and all of the PCB sealed in an isolated box, it could be much cheaper!
-
The 2 precision arrays are way cheaper than most of the stuff of this class, about $3 each for the really bog standard grade, $7 each for the almost perfect, and about $12 for the best you could conceivably need, as you only need to pay for stability not accuracy, Not to mention I have generic 0805 footprints on the back side of the board if you really want to keep it dirt cheap
Even the op amp footprints are standard, you could swap them out for some cheapies if you don't have as good supplier options. I've been trying to add test points and alternative footprints where possible to leave these options.
Heating everything up hurts quite a bit, all the resistances have thermal higher noise, the op amps generally have worse specs in general and increased noise of there own, its generally better to just pack it into a good insulating box with some desiccant to keep the humidity stable as well, (If you look at the datasheet almost everything is trimmed in to perform best at 25C)
Equally the op amps are way cheaper than I had imagined, I'll have to check my BOM, but I suspect the whole board so far falls under $100 including PCB.
The other issue, and what I am trying to work around by layout is making sure every part of the board is the same temperature is literally impossible, but you can minimize how much variance is seen by components and connections. and try to ensure that differential signals (say both op amp inputs) see the same temperature / same line on a thermal gradient map as possible. every connection between dissimilar metals is technically both a voltage and current source depending on what hurts you more.
E.g. the parts of the circuit I went through and worked out the power dissipation for, normal engineering brain would say a change of 25mW is literally nothing, but it causes a peak on the thermal gradient map (something I really wish I knew how to model) and have a slope leading away from that part,
25mW in a SOT-23 package is an 6C rise because the package is 250C/W to pcb, which while not a crazy steep gradient does effect what surrounds it, or on the more exterme, U4, he is dumping out 300mW just sitting on the PCB, but he has a very low noise figure, so its more a case of working out how that heat will effect the things around him, the reference is easy to hide on its own little thermal island, the op amp, not so much.
-
The upper OP in the 2 OP buffer amplifier is mainly working as a follower, and as this it is fast. The capacitor in direct feedback will not see much voltage change even on a large voltage step. So the important initial settling is fast. The capacitor may slow things down when it comes to the last few 0.01% settling, but for the precision part there is the 2 nd OP (OPA145). The 100 nF capacitor does not need to be that large some 1 nF would also work and chances are it works without the cap.
So far my ADC runs with 1 PLC integration and for tests also 2 , 4, 8 , 16 PLC are possible, though not very useful for real life.
I initially did a few test with very short integration of some 100 µs (still with just an integration phase like in a dual slope), and even this worked quite well. However sending out the data was limiting than. Even now I get some UART errors at higher baud rates though the opto-coupler should be fast enough. Something like an 1 ms integration time is a plausible short time, some 100 µs is probably the lower useful limit as even with some speed ups the run-down will take about that long and sending the data also takes some time. The noise from R12, the 5534 and so on would be relevant for those faster conversions, but not at 20 ms.
There is no real need to get a constant temperature for the whole board. Using good resistor arrays is easier and the resistors need to good anyway for good linearity and gain stability. Measuring the ADC gain for every signal conversion (e.g. cycle with signal , zero and reference instead of just signal and zero) is a working option if lower grade resistors are used. The LM399 reference brings it's own oven and there are not that many alternatives for a cheap long time stable reference. The LM399 is also easy to use.
The ADC principle also works with cheaper parts - my first test used TL072 and normal 1% thick film resistors. For lower demands a single OP integrator should be OK and the buffer can also be a single OP. There are surprisingly few really critical parts where high quality parts help: the reference, 1 OP in the integrator, to a lesser degree the buffer OP, the 3 resistors at the integrator input and 3(4) resistors for the reference amplification.
The input amplifier / buffer is a difficult part. For just a buffer a bootstrapped AZ OP is a good solution. The choice of AZ OP is a compromise between input bias, current noise on one side and voltage noise on the other side. In any case it needs some filtering at the input to avoid higher frequencies to cause trouble going both directions: RF interference from the outside and the switching / chopping spikes from the AZ OP. Just as a buffer I would consider MAX4238 or AD8551 good enough. In a configuration with gain the LTC1052 or AD8628 may be more suitable as they have less noise. For just a buffer, there is no need for the low voltage noise of the LTC2057 - with gain the low noise level may be needed to make full use of the ADC resolution. The LTC2057 is not suitable for really high impedance sources though, but should still be not that bad with some input filtering. The high input impedance of good DMMs is not there to make them useful with Mohms source impedance, but more to get full precision even with sources in the 10 Kohms range. For low noise just a 100K range series resistor for input protection is no longer an option. For really high impedance sources there are separate electrometers.
A JFET amplifier with AZ switching at the input is also not a simple solution. The really hard point here is getting the switching spikes from the AZ switching small. The possibly large voltage step makes this in my view more demanding than switching on a chopper amplifier, with voltages of a few mV at the switches.
-
The micro area is mostly done, and have fleshed out most of the power supply routing, the micro will end up nudged a bit to the left, and the reference likely rotated clockwise 90 degrees depending on how I have to handle room for the input buffer idea.the 7V buffer is included, and have already planned out room for the power supply regulators bottom left and the diodes / input caps bottom right.
Any thoughts on even a general layout for what your planning for the input buffer, or would it be nor far off a mirror of what we have after the input mux?
-
i am very interested in releasing a multi slope ADC , but i wanna know the advantage of this kind of ADC instead of using a Delta Sigma converter ?
-
The general placement looks acceptable. The control lines the the MUX are not that critical (they are switched only a few times) and I see not need for surrounding them with ground.
For the input butter a circuit quite similar to the buffer behind the MUX is possible. The main difference would be using an AZ OP instead of the OPA145. The normal buffer could also drive some bootstrapping for input protection.
An alternative version would be similar to the buffer Mickle has in his circuit, with bootstrapping the supply from the OPs output. This is slower, but not a problem for the input.
@namster:
Sigma delta ADC converters as a chip (e.g. LTC2410) have a lower voltage range, like +-2.5 V for the input and 5 V for the reference. This makes is rather difficult to find a really long time stable reference. The INL of the chips is also limited to some 5 ppm. The low noise chips tend to be not the lowest INL ones. One the positive side they are relatively easy to use, cheap and low power. If the performance is sufficient they are an easy way to something like 5 digits or low end 6 digits resolution.
Building a high resolution sigma delta ADC from separate parts is quite difficult, as the switching and integrator has to be quite fast to get high resolution like 24 Bits. The SD ADC has it's own difficulties, like idle tones and more critical switches. Existing implementations like in the Keysight 34465 are quite complicated. They have advantages for high speed, e.g. to do digital RMS.
Due to the high speed control it usually takes an FPGA for control and a more critical layout.
For the multi-slope ADC principle one can get away with slower switching and still get high resolution. Difficulties are more in the way combining the contributions. Also the speed of the conversions is limited as the run-down takes some time and thus limits the speed.
The multi-slope implementation I showed uses rather simple hardware (my first version was even on a bread-board + small PCB for the µC) and still gets high resolution and low noise. It is not a classical MS-ADC but also uses the auxiliary ADC. The more classic solutions tend to need more hardware and still get higher noise.
-
Just my opinion: It kinda looks odd to use a THT package for the microcontroller, while almost everything else is SMD.
Don't forget to place some mounting holes.
-branadic-
-
well technically have the digital signals, ground and digital supply voltages all bunched up as much as possible when even close to the sensitive areas to try and reduce any risk of coupling. It may be overkill, but the board area is free to use.
Branadic, This more falls under not having fully broken down his original assembly programming into psudocode (I am not good with reading assembly), the dip package being as large as it is, means it would be easy to swap out to a QFP or other micro of your choice. there is nothing particularly special about the ATmega8 used in this circuit. you could even plop in an atmega328 if you have an old arduino board floating around. it was more keep the code the same until I know how to adapt it.
Mounting holes can be done, means I will need to shuffle the power supply area and input connector a little, to fit M3 holes with 5.5mm diameter exclusions at the corners, a 100x100mm board is quite firm, and luckily most of the more sensitive stuff lives towards the middle, so the board stress and heatsinking from the mounting posts should be OK, just wondering how they should be in relation to the circuit, I imagine tied to ground at the bottom corners near the power supply and left floating up the top
-
Just my opinion: It kinda looks odd to use a THT package for the microcontroller, while almost everything else is SMD.
It used to be more common and it is sometimes still done so that the microcontroller can be easily programmed before assembly.
-
A THT µC looks odd, but the space it there and allows swapping the µC if really needed.
The other point is that the SMD packages for the AVR are rather tiny - so it's either rather large or rather dense compared to the rest.
The current code for the ADC uses some 1700 bytes of flash and little RAM, so even the mega48 is large enough.
I know reading other peoples ASM code is difficult.
For the mounting holes it would be good to have grounding at one hole. For the others I would prefer the option to keep them isolated.
-
at ATmega's actually come in a 0.8mm pitch TQFP package, so its still in the easy to solder area, Once I get this board locked in for version 1, I can do a quick spin for a TQFP option, but in reality any micro with a comparator and ADC could likely be substituted. I'll likely end up using the TQFP, as I have a tray of 328's still floating around,
I actually prefer smd micro controllers with a 6 pin ISP connector sitting next to them, there is always another software revision, so may as well make it easy to update,
Ground 1 hole, done, will do it in the power supply star area so any shorts are where the traces are thick, and its easy to repair.
-
..., but in reality any micro with a comparator and ADC could likely be substituted.
I am not so sure with this. Some other µCs may need extra external synchronization to keep jitter low, especially if a PLL clock is used, but also just the internal structure of the IO ports may cause more jitter. There are usually not specs for this, so one has to check. At least some other ADC designs (e.g. 34401, some versions at CERN) use extra synchronization. Another point is the ability to get a defined timing - this may need extra HW support (e.g. use timers) if the µC is using caches.
-
well technically have the digital signals, ground and digital supply voltages all bunched up as much as possible when even close to the sensitive areas to try and reduce any risk of coupling. It may be overkill, but the board area is free to use...
Mounting holes can be done, means I will need to shuffle the power supply area and input connector a little, to fit M3 holes with 5.5mm diameter exclusions at the corners, a 100x100mm board is quite firm, and luckily most of the more sensitive stuff lives towards the middle, so the board stress and heatsinking from the mounting posts should be OK, just wondering how they should be in relation to the circuit, I imagine tied to ground at the bottom corners near the power supply and left floating up the top
Put a 27-51ohm resistors in each digital (and analog) signal (as close as possible to the AVR package).
You may provide slots around the mounting holes such you lower stress and heat sinking.
PS: I still think putting the voltage regulators on the inguard ADC board is not a good idea..
-
doesn't make any sense for the analog lines, as they are inputs, and there sources have resistances of a few kilo-ohm, the digital outputs already have footprints for series resistors, I just ball parked 220 ohm to knock things down to under about 1MHz but it can be reduced further,
Also thinking the power supply would be better on its own PCB leaving just the bulk decoupling locally, but then you raise the dangerous question, what to do with all that extra room ::)
In reality the math is saying it should be fine unless your asking the regs to drop a lot of voltage, the 5V rail has under 15mA of load, and the +-15V rail has less than 40mA, so being tucked away in its own little corner with only the micro to upset means the reference and the hot slope amplifier in the ADC will locally out compete any power supply gradient by a mile.
-
@Kleinstein
thanks for these clarification , for my final years project i release a prototype of Milliohmeter but the ADC is the main problem in my country its very difficulte to find an adequat adc , i realsed a dual slope ADC but the result wasn't very convincing i will start a prototyping a new multislope ADC based on the shematics you proposed .
-
If the possibly high current of the NE5534 is a problem, it would be Ok to use something like OPA197. The Ne 5534 is more like the classic choice on many other designs, as its fast and cheap.
@namster:
for a lower cost, easier version, one could use simpler OPs, a single OP buffer and single OP integrator. The asymmetric reference part is not absolutely needed - especially not for less than 7 digits. For the switches 74HC4053 or HEF4053 are also not that much higher noise.
-
Just my opinion: It kinda looks odd to use a THT package for the microcontroller, while almost everything else is SMD.
It used to be more common and it is sometimes still done so that the microcontroller can be easily programmed before assembly.
The DIL28 socket may serve as "a connector" for future FPGA based solution (a piggybacked board) :)
PS: also I would recommend an external 16MHz oscillator (instead of the AVR+Xtal).
-
doesn't make any sense for the analog lines, as they are inputs, and there sources have resistances of a few kilo-ohm, the digital outputs already have footprints for series resistors, I just ball parked 220 ohm to knock things down to under about 1MHz but it can be reduced further,
All atmega's pins radiate (the resistors are not there only because of fast edges), thus the resistors should be placed as close to the atmega's pins as possible (what is not the case in your latest design, imho).
PS: the usage of chopper opamps with different chopping freqs is not recommended (IMD products).
I would avoid that with an 8.5+ design.. :)
-
I have tried both an external oscillator and just a crystal at the mega48. Both versions work, with not much difference.
The external clock may be a little more stable, but the extra oscillator also tends to use more power and give a possible path for RF injected to ground. At least the old style large oscillators are quite power hungry.
The version with the slow slope can also run at a lower clock speed. So the µC does not have to run at 5 V. It may be OK to run the µC at some 8 MHz and maybe 3.5 V. The MCP6002 is still OK with 3.5 V or similar. If the 4053 still runs from 5 V, there are HCT / LVT versions that can accept 3 V drive signals. Compared to the old µCs with external ROM (e.g. 80196 in the 34401) the modern ones with internal flash reduce emissions quite a bit. Good decoupling of the µC supply is still needed - this includes a resistor/ferrite bead not only for the analog side VCC, but also for the digital side VCC. Just the usual capacitor at the supply and than direct (low impedance) connection to supply and ground is tricky, as there may be several low impedance caps at the supply and thus possibly currents oscillating between the caps.
Such a separation may even also be used with the OP07 at the reference - though these OPs are slow.
The current design does not use an AZ-OP in the actual ADC part. The amplifier before the MUX should be some kind of AZ amplifier or buffer - the different type discussed so far are more like alternative solutions. Even then 2 different AZ OPs usually work with quite different chopper frequency.
-
As an example how Fluke does it with resistors at the pins - here 22ohm (the source - xdevs.com).
External oscillator - a small smd 16-20MHz one adds 20mA worst case, imo.
The atmega328p works fine at 16MHz/3.3V.
PS: The atmega328p includes a "stable" 1.1V reference on the chip, thus you may use it for the ADC instead of the Vcc.
There is an on-chip thermal sensor you may read out as well.
-
I have them on the output pins for now, are you saying those are not close enough? I have been maintaining rule of thumb spacing to make sure average joe with tweezers can solder the things to the pcb, so these had to be a bit further away to fit a soldering iron tip next to potentially a socketed micro.
as for on inputs, I can add them, but I would like some rational behind how inputs with there input buffers disabled could be a significant noise source,
-
I have always wondered if it is worth phase locking the conversion cycle to the power line frequency to maximize normal and common mode rejection or if variation in the power line frequency just makes things worse.
-
I have always wondered if it is worth phase locking the conversion cycle to the power line frequency to maximize normal and common mode rejection or if variation in the power line frequency just makes things worse.
Datron did this starting with the 1051. I'd expect that many 6.5 or better meters will do this as it's relatively easy to do.
-
I suppose the question can be respun as. Are there any timing specific differences between starting on 2 diffent parts of the cycle while still integrating over an entire mains cycle.
If the non linearities are reduced below what the meter can determine. I do not think it would change anything. Mains frequency can shift. But it is not easy to measure that with low jitter if there are other harmonics on the mains.
-
I suppose the question can be respun as. Are there any timing specific differences between starting on 2 diffent parts of the cycle while still integrating over an entire mains cycle.
No, the problem is not when to start during the mains cycle. We know integration over a whole number of main cycles will cancel out power line interference and that this is necessary for good performance.
The question is whether the integration time needs to be frequency locked to follow the variation in power line frequency over time. How much mismatch is acceptable and does the natural variation in power line frequency exceed it? Or does having a slightly variable integration time cause even greater errors?
All of the precision integrating converters I have played with used a fixed integration time which did not track the power line frequency. They rejected 50 or 60 Hz interference or both but relied on an independent fixed oscillator for timing.
-
The HP3458a manual gives an idea on how much influence a mismatch in frequency gives,
Edit: Tek DMM4050 gives similar numbers aswell,
-
50/60Hz sync: 34401A does it simply such it takes the voltage off the bridge (+/-15V inguard), limits it with a 6.2V zener and feeds it directly into a "high speed input" pin of the inguard 80C196.
-
It may measure it, but it doesn't look to actively compensate for it.
-
It may measure it, but it doesn't look to actively compensate for it.
Good point, I've been just thinking how they do it.. You may phase lock the master oscillator to the mains freq (they do not), or lock the process on the rising/falling edge of that L[ine]SENSE "signal".
-
All of the precision integrating converters I have played with used a fixed integration time which did not track the power line frequency. They rejected 50 or 60 Hz interference or both but relied on an independent fixed oscillator for timing.
In my design there is no frequency locking to mains. Integration time is fixed to 20ms (1PLC) from local quartz oscillator (cheap +-30ppm one), giving me some degree of power line frequency suppression, but given the fact it floats in range of few tenths of Hz around 50Hz*, suppression probably is far from perfect and drifts a bit. That being said, I have yet to find a situation where it really matters.
Locking to power line frequency isn't trivial excercise.
Some older meters had PLLs locked to power line frequency (Datron and perhaps some Solartrons had it too), but I read a few maintenance/repair reports where PLL was disabled and meter was fed with fixed frequency instead in order to decrease noise in readout.
Modern-ish meters usually don't have PLL. Many of them seem to have no provision to sense line frequency to adjust integration time, though there is option to manually switch between 50/60Hz PLC base. Some instruments do seem to sense line frequency from power transformer, but I don't believe they are doing anything else than just automatic switching 50/60Hz PLC base, as seen in Fluke 884x **.
No idea about really new meters, since service manuals don't contain schematics anymore.
* https://www.swissgrid.ch/en/home/operation/regulation/grid-stability.html (https://www.swissgrid.ch/en/home/operation/regulation/grid-stability.html)
** https://www.eevblog.com/forum/repair/fluke-8840a-faulty-cpu/ (https://www.eevblog.com/forum/repair/fluke-8840a-faulty-cpu/)
-
Really locking the integration time to the line frequency is tricky. The line frequency is not 100 % stable - thus the possibly need to adjust. The later solartron DMMs did a PLL lock to the mains frequency and this was a constant possible cause of failure. They are kind of special however using a very long integration. Other meters offer some kind of line synchronous start, likely with the idea to have any line related error more as a offset than getting some low beat frequency.
With a multi-slope ADC with rundown, there is however the problem that the extra rundown time would require quite some waiting after each conversion - so I don't think it is normally worth it.
For realizing mains look there are two possibilities:
1) use PLL and really adjust the µC/ADC clock. This can be tricky to get low jitter, as the mains signal may have some jitter too.
So this would need to be PLL with rather slow reaction and thus difficult to build analog.
2) keep the clock constant and adjust the integration time by adjusting the number of µC cycles in run-up. Some adjustment is possible in software. I would normally not change that in real times as a different integration time could effect the ADC gain and offset a little. Doing the frequency measurement could be done in the ground referenced part.
If at all I would go for the 2 nd option.
For very short time (e.g. less than minutes) fluctuations it can be rather difficult to follow the true main frequency and not get upset by distortion, so it's not an easy thing to do in either way. Just a good measurement of the mains frequency is a tricky thing.
Mains frequency variation are rarely more than 0.05 Hz or 0.1 %. More typical seem to be some 0.01 Hz. So mains suppression should normally be better than some 0.1% 60 dB (single chunk integration).
With a fast running ADC (1 PLC) and using averaging instead of long integration at a piece, there may be an effect to make the exact length less critical: If the integration time is too long, there would short extra parts in excess of the full cycle that are extra integrated. As the total conversion takes a little (e.g. 0.2 ms) longer than a cycle, the extra portions start at different times on the cycle, on the long run (e.g. 100 PLC) more or less evenly distributed over the cycle. With the other extreme of a single long integration the extra times would be as one chunk and thus possibly more sensitive to mains disturbance. The larger number of short extra chunks should give better suppression around the nominal mains frequency at the price of more sensitivity to higher frequency (e.g. kHz range) components. These higher frequency components should be relatively easy to filter out analog. Averaging enough short integrations to get about evenly distribute the short extra (or missing) extra chunks should give extra suppression - ideally up to another factor of the frequency deviation. So mains suppression can get better for a certain number of averages (so that the total run-down time makes up 1 PLC, e.g. 50 Az cycles).
-
If it was pursued, I would say a software controlled integration time would be the easiest to implement as timer 0 is presently not used, pin swap PD4, hook up a mains to digital circuit of your choosing to give a clean signal,
For 60db of rejection, does require an average match of about 0.1% this is the harder point, 0.05Hz, but luckily the average mains is really slow to change in frequency compared to the sample rate, so it could be every minute or so, after the conversion, it compares timer0's delta to timer1's delta and uses that to calculate the average mains frequency and offset the integration time,
the amount of noise rejection is respectable, as that is the attenuation factor of the power line pickup noise which would already be attenuated by most measurement setups, I suspect the need for it is minimal,
edit: yes this is a very lazy and lower accuracy method, however it means that for the entire period, the ADC can be pumping out readings with no overhead, no interrupts, etc, and makes it very immune to any jitter on the detector circuit.
-
I would give the mains measurement job to another µC. At the low frequency there are already not that many zero transitions to measure, which makes a good mains look a really demanding task. Just doing a simple timing on the start and end of a longer gate interval is rather sensitive to noise / mains distortion, even with some analog filtering. Averaging over too long would give the result late - there is not that much sense in adjusting the integration time to the frequency to the average frequency of the last 10 minutes. How the mains varies depends on the grid one is in - some weak grids (e.g. Russia) may drop more and over longer time, while some forms of wind energy can cause quite some frequency noise on the shorter run.
The ADC would than only get send a correction value to adjust the integration a little in software. At the start of conversion there can be an adjustable integrate only phase of a few 10 µs, that could be used for fine adjust, still leaving the modulation part at the same length. This phase could be just long enough to compensate the normal mains variation. When off by more it may need to drop a modulation cycle.
The roughly 60 dB number would be for fast conversions (without time adjustment and a more bad case frequency). With enough averaging the number should improve as the extra/missing time is not as a single chunk. One could even consider adding a little extra delay to the rundown so that suppression could get better already at some 10 PLC. Without an extra delay it's about 50 PLC signal +50 PLC zero when the rundown times make up another PLC and should give extra suppression, even with only the nominal frequency.
-
ok, separate micro, so SPI and a chip select, easy enough to accomodate, the other micro is fully task specific, work out the mains frequency right now, and when the chip select is triggered, be read by the ADC micro to do the adjustments, easy enough,
for just about any micro, you would technically have the resources to just sample the mains and DFT it, But I would probably prefer a rolling average reciprocal frequency, (then converted to an 8 or 16 bit correction value)
Edit: Unless something specific is in mind, I will likely just expose some dedicated 0.1" header for the option.
-
Here is an example of "possible" mains phase shift against the 34401A clock.
The measurement started at 14:18 afternoon, and you may see aprox 5000secs long periods, which slowly disappeared towards the evening, which I cannot explain other than with the mains 50Hz phase shifts..
PS: the X axis is in seconds..
-
PS: The atmega328p includes a "stable" 1.1V reference on the chip, thus you may use it for the ADC instead of the Vcc.
The internal bandgap Vref=1.1V is for the newer atmegas (like 48,88,328) with the classic atmega8 it is 2.56V internal Vref. You may use your own external Vref as well.
-
5000 seconds would be a rather slow time scale to adjust the PLC lenght. It depends on the grid, but variations can be quite a bit faster (though a weak grid on the edge may show a daily drop at power peaks). The are other possibly internal things going on at such a period. Also external signals are possible like the AC or heating system.
The Ref. for the µC internal ADC is not that critical, as it only contributes a little (hardly 4 bits more than noise). So the µC internal ref may indeed be sufficient, as well as the 5 V supply. A divider from the main reference would also be possible. With a large temperature change one has the option to measure the scale factor - it is not just the reference changing, but also the integration cap and gain of the slope amplifier and final RR OP.
The mains-frequency measuring could be a dedicated µC or just from the ground referenced part at the display.
Adjusting the integration time can cause discontinuities, as the length can effect the gain of the ADC. Combining different length data can be tricky, even of the adjustments are not large.
-
fyi - an older thread on analyzing 34401A MS:
http://bbs.38hot.net/thread-17335-1-1.html (http://bbs.38hot.net/thread-17335-1-1.html)
-
Had a go at doing an excel calculation for your modulation pattern Kleinstein, seems the max input range is about +10 to -11.2 for the current modulation style and the current reference levels.
Atleast based on how you had it described,
1us +ref
1us -ref
10us + or - depending on comparator,
-
+10 to -11 sound about right for a 1 / 1 / 10 µs pattern. For a little more range, the comparator dependent phase can be slightly longer. I am currently using some 20 µs. This give some 10% more range.
The choice of the pattern is a compromise: less of the fixed phases makes the integrator settling more critical and can result in INL errors. More of the variable phase makes the rundown phase longer. Worst case one has about 2 of the run-up steps for the fast part of the rundown. A slower modulation also needs a larger integration cap. Errors due to dielectric absorption also limit maximum length of the patterns. With a reasonable good cap there should be no problem below some 100 µs however.
-
Try with 1us P, 1us N, 18us P_or_N --> that is 1000 phases in 20ms (50Hz mains).
-
Yep, the math makes it nice and clear, a trade of between pattern speed, capacitor size, modulation frequency and input range, with you pattern at about 45.45KHz, your original pattern would be 83.3KHz, and IMO's a flat 50KHz, have added in the drift, and resistor mismatch to the calc to put some actual numbers to the effect, main remaining quirk is working out the charge injection influence as the model of mux doesn't actually specify it, and there will always be some degree of charge mismatch as every time the fixed part changes polarity you end up with an extra transition, and that part is variable, vs input voltage,
Not accounting for capacitor DA, the rundown period for your method Klein should only be 40uS at most assuming single ref rundown. however knowing what the general way to model this would be ideal on these time scales,
Also still trying to understand exactly where your extracting the number of raw bits from, e.g. for 0V input, I would expect ~15216 Timer clocks for positive cycles, and ~16800 Timer clocks for negative cycles with a residue of -1.20545V
Have not yet fixed the math to get the counts at the exact comparator crossing, but this may help me to understand the specifics.
-
Also been looking into DA, and wow are the capacitors cheap, just at the cost of size,
https://au.mouser.com/datasheet/2/440/e_WIMA_FKP_2-1139852.pdf for 26c (Poly propelene),
I suppose at these modulation frequencies Dissipation factor would also come in to play. however both PP and COG seem in the same ballpark, with COG just being more stable vs frequency. with the poly winning by a factor of 20 to 50 on dielectric absorbtion
edit: also find it a little weird that PPS capacitors do not list dielectric absorbtion,
edit2: also found a link to how to design a circuit to compensate out DA, not sure if it would be a benefit though,
https://electronics.stackexchange.com/a/289322
-
I have not yet implemented reading the exact moment of the comparator switching (using the input capture function). Reading the time is the simple part. The slightly tricky part is than to switch with a fixed delay from that time. I think I got a working code for this, but not yet tested. The idea is to add 2 delay steps of 1 and 2 cycles depending on the last 2 bits of the ICP result.
This improved accuracy for control should allow to get away without the slow slope if the µC runs at a fast clock (e.g. >=12 MHz).
However the timing resolution does not effect the way the result is calculated. For the conversion the relevant time is not the point when the comparator switches, but the time when the output is switched.
The fast part of the run-down only takes some 40 µs, but there is also the slow part, that may take some 10-15 µs as there is quite some overshoot. Than comes some waiting time (e.g. 40 µs) to give the amplifiers and fast part of the DA time to settle. The final required part is some 15 µs for the sampling part of the AVR internal ADC.
For combining the result of the run-up and fast rundown, it helps to keep in mind that the main reference level is the difference from the positive to negative side. So a 20 µs interval from the run-up gives 20 µs worth of the difference. For the rundown the difference in the times for the positive and negative reference active has half the value. E.g. having some 1 µs neg. and 15 µs pos. would be 14 µs difference, that has the same effect as 7 µs of the difference. The sum of the times for the positive and negative active than is part of the slow slope contribution. If no slow slope is used it would be still a correcting parameter if the reference are not exactly opposite.
The charge injection and leakage currents at the switches act as additional input current. So this is just like an offset to the input. So it is not separately measured, but corrected with the OPs offsets etc. by taking the difference to a zero reading.
For the DA there should be no need to do a correction like shown in the link. From the estimates the DA effect should be small enough. If a correction would be done, it would be more by modifying the control during run-up, so that the average integrator output voltage is smaller. The HP34401 does this by adding some negative part of the input signal to the comparator voltage. From my estimates not even this is needed. The DA values of different bands / types vary quite a bit. So it may be easier to get a good cap instead of adding more circuit. With only some 1-3 nF there is plenty of choice. I kind of like NP0 because of the small TC. There is still the option to use a slightly faster modulation.
.
The DA usually is caused by 2 processes: a fast one with a time constant roughly in the 10 µs range. This part is usually material internal reorientation of dipoles. With the extra waiting time this effect should not matter much in my implementation.
The second part is very slow with a time constant more in the 10 s range. This is usually assumed to be due to surface charges in the capacitor. This part of the DA may vary between capacitor brands / types, e.g. with different amounts of air or humidity trapped inside. This part is also the relevant part for the ADC. The main effect is to kind of hide some charge proportional to the average integrator output voltage and give it back later. So the important number is more like the DA at 1 second. As a crude estimate the expected DA related error would be in the ball park of DA at 1 second divided by the modulation frequency in Hz, so something like 0.1% / 50000 = 0.02 ppm. Much of this would be a carry over from one conversion to the next, not directly an INL error. A linearity error can happen especially in the center of the range as the average voltage there varies with input.
-
Oh the joys of math, now working through rundown, 45uS is the maximum time required for a fast rundown based on the current parameters, which gets you an uncertainty of 27mV, (comparator could flag in the jump instruction or after the compare state was read)
Slow slope is another 3uS maximum, this gets you to an uncertainty of 1.3mV (2 clock cycles again)
For both of these, you will end up with a fairly fixed offset of 2 clocks, 1 for the response to switch the output, and ~1 for the delay to switch the mux, so that potentiometer for the AVR analog input is most effective when trimmed to a level about 2 clock cycles below the ADC's beginning of range + uncertainty, or about 0.75V
then an ADC conversion to drag those last few bits out. but it seems limited right now, as you said you expected this to reflect 5uV per LSB, it would be a simple case of altering the gain resistors at U13 to ensure it encompasses say 4 times the slow slope uncertainty, meaning right now it should be possible double its gain and remain in range. e.g. 2.5uV / LSB
-
The timing steps are 4 clock cycle. This is the time for the loops checking the comparator. The time it than takes to than actually switch only gives an offset / shift. Due to the shift and resulting oveshoot the slow rundown takes a bit longer. To reduce this there is the option to add a level shift using resistor between PD5 and PD6. However the extra time may not be that bad, as it's already near the target and thus already helping the amplifier settling. The variable part of the slow slope part can take some 250 ns times the slope ratio, so up to some 5 µs.
The residual voltage levels sound plausible. Resolving the 1.24 mV rest after slow rundown to some 5 µV only needs some 8 bit from the final ADC. So there is quite some headroom, as the ADC has 10 Bits. The trimmer at the comparator is used to bring the ADC readings in range - so it is relatively easy (not critical, just inside a rather large window) to adjust.
So far the level is quite stable and I see thus little problem with hitting the rails / limits due to drift / aging.
Less asymmetry in the references could be used - the main advantage I see is a higher reference level and less effect of the divider for the shift. The extra resolution is not really needed. If needed less gain at U13 could be used too. For the normal 20 ms conversions the noise limit is at more like 50 µV for the integrator voltage. So a 5 µV resolution is not really needed. It may help for faster conversions ( e.g. 1 ms). Doing a 2nd conversion for the µC internal ADC gives essentially the same reading - so the readout noise is at or below the 5 µV level.
It is more like there is enough room to use more of the µC ADC resolution and than get away without the slow slope, if the timing resolution can be reduced to 1 cycle. So one would gain a 2 bits from better timing, loose some 4.5 Bits from the slow slope and use 1 bit more from the ADC. So some 1.5 bit less of theoretical resolution, but still better than the noise limit.
-
Ok, if that is the case, we can forget the level shift, I like the asymmetric references, so no issue there, was just thinking of twaeking the ratio, but with the new info, it can likely be left as is,
If we tweak the ADC diff amp offset, we can move the comparator into its temperature insensitive range (about 1V), to edge out a little more stability of its switching point,
as for the assembly, it seems it is 3 cycles of uncertainty, should have double checked, RJMP is 2 cycles, and a false SBIS is 1 (assuming the comparitor fired at the exact moment before SBIS would treat it as true)
loop: SBIS ACSR, ACO ; Skip next instruction if ACO = 1
RJMP loop ; Go back to loop
However silly me forgot this is uncertainty in the overshoot, not the timing value, with is 1 clock cycle (using timer capture)
with this, the fast slope is down to 15mV, and the slow slope down to 620uV, if we set up the ADC to measure say a 30mV range, that is a 30uV LSB, so below the noise limit for the current hardware, but just barely.
-
Fyi - the simulation with KL modulation (3x100k and 560pF, 1us+1us+18us).
-
Apart from the polarity being reversed, looks like my calc is pretty spot on,
If you want to play, have fun https://docs.google.com/spreadsheets/d/124oaWnT20oyATqJzljLi7ERs9dDA7BqPNQoNRmwFV4k/edit?usp=sharing
-
CountN and CountP within a 20ms measurement:
Imagine we've got 1+1+18us=20us "phase", 1000 phases in 1measurement (1PLC).
With 0V input you have to count CountN=500 and CountP=500.
With 10V input you have to count, for example, CountN=100 and CountP=900.
With -10V input you have to count, for example, CountN=900 and CountP=100.
With 11V input you have to count, for example, CountN=60 and CountP=940.
With -11V input you have to count, for example, CountN=940 and CountP=60.
Or something like that..
-
...
as for the assembly, it seems it is 3 cycles of uncertainty, should have double checked, RJMP is 2 cycles, and a false SBIS is 1 (assuming the comparitor fired at the exact moment before SBIS would treat it as true)
loop: SBIS ACSR, ACO ; Skip next instruction if ACO = 1
RJMP loop ; Go back to loop
With some µCs this could in deed be a 3 cycle loop. However the Mega48 and most newer AVRs can not use SBIS with the internal comparator as the ACSR register is out of range. So it needs an extra IN R...,ACSR instruction.
For the fine delays from the ICP value a 4 cycle loop is also easier. With added delay one could get single cycle resolution - so more like 8 mV at the integrator. So the ADC could cover something like a 15 mV range. So the resolution would just enough to keep quantization noise low. However there would be little reserve for faster conversions. So while is helps to get an even faster rundown, it also limits the resolution for fast conversions. I would still keep the option for the asymmetric references - one can still populate just 1 resistor to get a nominally symmetric reference.
I think the temperature sensitivity of the comparator curve is more like a typical curve, not one to take to accurate. The comparator is only acting after the slope amplifier, so that the comparator drift is not that critical. The ADC covers some 200 -500 mV of the slope amplifiers output. So the comparator drift has to be compared to this number. So even 10 mV of drift of the comparator would be only some 2-5% of the ADC range.
-
The measurement of that voltage at the slope's amplifier could be a challenge, imho.
See below ADC input vs slope's amplifier output.
-
I was more suggesting the comparator change, as its a free modification, change R34 to 56K and AIN1's pot to ~1V, and the ADC diff amp resistors accordingly, and you move it into that range, with no layout changes, for now I'll leave it as a schematic note, was just to remove uncertainty if weirder modulation schemes where used
And the assembler timing is actually non critical, as the timer capture is 1 cycle at most, the assembler delay is variable by up to the entire register checking loop, and this will appear as an offset, however you can use the timer capture to bring this uncertainty down to 1 cycle, (you still do not know exactly when in the cycle it tripper the comparator), so lets say if you used a correction pulse of that length, luckily these uncertainties are not independant, so you end up with a fairly fixed uncertainty of just +-0.5 cycles for the measurement with those correction pulses.
Per clock cycle the fast slope adds up to 15.2mV, so the ADC range would be still have to be at least double this to ensure it never leaves this boundary, the less variability there is on the comparator switch point, the tighter we can keep the ADC range without having to worry
All this math is still based on 25K ohm input resistors and 2.2nF integration cap, these slopes can be changed a little if you wish, I have updated that google sheet so you can offset the comparator transition point,
As to IMO, those 1000 high / low descisions are not the only information you have on hand, you also have the timer capture hardware, so you know exactly what clock edge it transitioned on, so instead of 1/1000, it is 1/320000 ok, so 18.25 bits there,
-
With the fine corrections from the ICP register, one should not need extra pulses - it is just delaying the time when to switch of. Bit 0 would cause an extra
-
As to IMO, those 1000 high / low descisions are not the only information you have on hand, you also have the timer capture hardware, so you know exactly what clock edge it transitioned on, so instead of 1/1000, it is 1/320000 ok, so 18.25 bits there,
Afaik the 20us phases are fixed length, where that 320x comes from?
20us/62.5ns=320?
1000x(+/-0..62.5ns)=+/-0..62.5us
Is your resolution 20ms+/-0..62.5us then?
-
20uS is the pattern length,but the timer is running on 16MHz, so 1us = 16 timer counts, The hardware comparator and timer capature will fire when it crosses its switching point, capturing the time it changed at, giving you resolution based on that 16MHz clock, not just the pattern cycles.
To my understanding the pattern is mainly to ensure both references get used a similar number of times every conversion, however this seems fairly variable to me. and there is no real solution around it,
on my sheet you can see how Count+ and Count- are not always a count of 16, these are the 0 crossing moments, this is because the capture function on the timer would have triggered, and that is the captured time for that 1us step of the pattern.
-
:D That has to be understood well, I have not dug into the assembler, but I tried to capture the algo in one post in KL's thread, it seems to me now the algo is different then.. :)
-
Its more me doing my best to interprit it, He is using and reading from the capture register, and it comes inline with his ~18 bit contribution from the modulation phase.
also found the 1st magic value where this method can go badly, -0.6V on the current reference levels is perfectly inline with the reference contributions, so the modulation pattern is just +-+-+-+-+-+-, but the duty cycle of the timer pulses is 94.4%, and implies it would be there for a few other values where this can hurt things. up side is keeping track of the pattern switches, can be used to correct these magic values as they appear.
edit: may only be the 1 gap, as with symmetrical references, this would be the 0 point, or the average of the 2 reference voltages, so it makes sense that only at this sliver of the range it would not be able to resolve using the normal method, instead it would be inverted in a sense, but you could still resolve it, seems to be about -0.76 to -0.46V
-
The main purpose of the patterns in the run-up is to make sure that the number and type of switchings of the 4053 are the same independent of the input voltage. This ensures that charge injection only gives an offset.
There are other options to implement this part. The 3 step pattern type are just the simplest solution. Other systems like a more continuous PWM system could be used too, but are more difficult to control.
Currently I am not yet using the ICP function. So the timing resolution is currently "only" 4 cycles = 250 ns. Here I just use the timer register to get the current time as the program runs.
The initial part comes from the run-up. Some 850 patterns of some 20 µs each.
The next part is the fast rundown that gives some 20+ µs with 250 ns resolution. Here only 1 reference is active and thus the effective time resolution compared to the positive or negative double.
Together with the run-up this gives some 0.9 * 20 ms/250ns *2 = 144000 counts of resolution as the first contribution.
The next part is than the slow slope part, with a slow slope of about 1/20 and the same timing resolution. This second contribution gives another factor of about 20 to the resolution. So together this more classical multi-slope part, using the comparator gives a resolution of some 2.8 million counts, so about +- 6.5 digits.
The final part is than the µC internal ADC: this gives some 8 bits of nominal resolution. However noise limits the effective resolution to only some 3-4 bits from the µC internal ADC.
The -0.6 V range is indeed one of the more critical ranges. Much of the early test where about this slightly difficult range. There is nothing principle bad (like miscounting the coarse part) happening. The center point was a problem (INL errors in the 1-10 ppm range) with the slightly more complicated 4 step method initially used. The 3 step pattern made things much (more than a factor of 10) better. There is still a little of INL error of the same kind visible in my test, but at a rather low level (e.g. < 0.1 ppm).
-
Well I can at least say what I feel is the common tell tale, if there is never 2 of the same pattern in a row, it is in this middle area, if there is only 1 polarity of the pattern used, it is out of range, trying to make nicer the math to cope with this middle area. technically all the info to resolve it is there, just it currently has to be treated differently.
The basis of the math looks to revolve around if the first pattern was positive or negative, then using the dutycycle to tell where it was in that range, but the positive and negative responses need to be handled differently, as slightly less than -0.6V gives a duty cycle of almost 0, and a value slightly more than -0.6 gives a duty cycle of almost 100%, moving towards 50% the closer they get to the end of this magic range. (offset of 2 patterns over 20ms)
Edit: the exact center point of all this fun is ((refp +refn) / 2) + integrator offset voltage
-
Hmm, I can see why for the modulation it would be difficult to fit in, due to being 16 bit variables and all, technically it would be 8 - 8 then saved to a 24 bit number, and the real pain is that there can be up to 3 crossings in the same pattern, so however it was handled would need to happen in each pattern step, of which I'm unclear how many free instructions are left, and how far the modulation can be taken without effecting other things if the step size was increased.
-
In January we were discussing the schemes and I was suggesting here in the post (https://www.eevblog.com/forum/projects/multislope-design/msg2105410/#msg2105410) to gate a fast clock simply by the P and N phases into two counters. Thus a combination of the KL or Jaromir's patterns and counting the charge balance with a high precision may work best for the runup.
PS: the "PWM" in my post in the link is perhaps misleading, it is more-less a standard modulation.
-
@Rerouter: your Excel sheet - you are splitting P and N counts based on the signal slope at the transition moment (crossing the zero). But I see there you are counting Count- even the switch is Positive, and vice versa.. Why? I think when the ref is P you have to count 16 for the Count+ always, and if the ref is N you have to count 16 for the Count- always (except they are split).
-
Hmm, I can see why for the modulation it would be difficult to fit in, due to being 16 bit variables and all, technically it would be 8 - 8 then saved to a 24 bit number, and the real pain is that there can be up to 3 crossings in the same pattern, so however it was handled would need to happen in each pattern step, of which I'm unclear how many free instructions are left, and how far the modulation can be taken without effecting other things if the step size was increased.
With the 2 fixed phases in between, the center of the range is not that special. It is going between positive and negative and back, just the time moves around a little. So in the run-up it is just counting the positive 20 µs chunks and the middle is not special in this case. The integrator should be fast enough that the short pulses with 1 µs should not be any special. So no need to extra count those extra for possible corrections for possible settling effects.
Like IMO wrote, this is just the normal modulation - it looks like the HP34401 and 3458 use a similar mode, just with a higher frequency. The frequency is still a parameter that could be changed - there should be room to reduce the 1 µs fixed parts, if the integrator is well tuned.
One could directly add the times during run-up (e.g. add some 20 µs = 320 clock cylces on each comparator dependent phase). It the times are all the same, it is enough to just count one case (e.g. positive) and than at the end multiply by 320 (or what ever is the length). I just send the raw number and let the PC do the math. This helps a little with debugging.
-
:-//
@Kleinstein: Now, let me doublecheck following re the scheme of the pattern (as has been discussed in your thread) with two subsequent patterns:
PatternN1 1. you set refN for 1us
2. based on the comparator's output you set refP or RefN
3. you wait 18us
4. you set refP for 1us
PatternN2 5. you set refN for 1us
6. based on the comparator's output you set refP or RefN
7. you wait 18us
8. you set refP for 1us
PatternN3 9. you set refN for 1us
...Is this correct?
Am I missing something?
Is the comparator read only once in each pattern as described above?
What is the "variphase" in your asm?
At which points above you start and finish with the capturing the "phase duration"?
-
The DA usually is caused by 2 processes: a fast one with a time constant roughly in the 10 µs range. This part is usually material internal reorientation of dipoles. With the extra waiting time this effect should not matter much in my implementation.
The second part is very slow with a time constant more in the 10 s range. This is usually assumed to be due to surface charges in the capacitor. This part of the DA may vary between capacitor brands / types, e.g. with different amounts of air or humidity trapped inside. This part is also the relevant part for the ADC. The main effect is to kind of hide some charge proportional to the average integrator output voltage and give it back later. So the important number is more like the DA at 1 second. As a crude estimate the expected DA related error would be in the ball park of DA at 1 second divided by the modulation frequency in Hz, so something like 0.1% / 50000 = 0.02 ppm. Much of this would be a carry over from one conversion to the next, not directly an INL error. A linearity error can happen especially in the center of the range as the average voltage there varies with input.
Don't be surprised if you find a time constant of some 25 ms too. That's what I found for the integration capacitor in my 3455A. Picture here:
https://www.eevblog.com/forum/testgear/hp-3455a-last-digit-jitter-in-hi-res-auto-cal-mode/msg967855/#msg967855 (https://www.eevblog.com/forum/testgear/hp-3455a-last-digit-jitter-in-hi-res-auto-cal-mode/msg967855/#msg967855)
New WIMA MKP 4 were no better, nor was an NP0 that I tried. Only an absolutely huge Russian teflon capacitor was significantly better (see traces in the above post).
-
Last time I checked this, I found considerable variation between brands of capacitor with the same dielectric and sometimes between lots from the same manufacturer. High voltage safety capacitors tended to be worse.
So I suggest testing polypropylene parts from several different manufacturers. It is too bad Teflon parts lack good availability.
-
:-//
@Kleinstein: Now, let me doublecheck following re the scheme of the pattern (as has been discussed in your thread) with two subsequent patterns:
PatternN1 1. you set refN for 1us
2. based on the comparator's output you set refP or RefN
3. you wait 18us
4. you set refP for 1us
PatternN2 5. you set refN for 1us
6. based on the comparator's output you set refP or RefN
7. you wait 18us
8. you set refP for 1us
PatternN3 9. you set refN for 1us
...Is this correct?
Am I missing something?
Is the comparator read only once in each pattern as described above?
What is the "variphase" in your asm?
At which points above you start and finish with the capturing the "phase duration"?
The shown program is about how I use it. The comparator is only reed once for each "20 µs" phase, even a little before the constant phase.
The "variphase" part in the ASM code is the core part of the comparator dependent part, especially counting the number of positive cases. The code may be a little confusing because the actual comparator test is split in 2 parts: first read the comparator to a CPU register (t3) and only later test the register in a makro ( #define skipCompPos SBRS t3,ACO ). The macros are used to allow changing the hardware to negative reference more powerful than the positive without doing to many changes in the code. My HW on the breadboard initially was this way around.
For the integration capacitor, I have tested a few so far: 3 different, old PS type caps and 2/3 x 1nF NP0 (THT version) caps in parallel. They work reasonably good with very little visible DA effect. I also tried some low quality caps (MKC, MKS) and these show quite some DA effect - so much to even tend to leave the range of the µC internal ADC. So it kind of worked for a small range. For the PP caps I expect some possible difference between units, as the critical part is the slow DA. AFAIK this is the DA due to the surface effects and thus production dependent. Finding good caps may still need some trying.
Compared to classical dual slope ADCs, I don't care about the very fast part - though this should mainly be a dielectric property, and thus the easy part.
-
If you have already broken out the flag to a register. You could likely make it PWM without much change. To lock the number of switch cycles to always be the same
Positive pattern: 1uS positive fixed. 18uS positive variable. 1uS negative variable
Negative pattern: 1uS positive fixed. 19uS negative variable.
-
Thanks. I've been asking on the exact run-up patterns scheme because you often use wordings with "..variable.." (ie. see the above post).
There is not "a variable phase" in the run-up patterns today (based on the above confirmation in the post #400), all events related to the switching of the Positive or Negative reference voltages within a pattern happen exactly at fixed specific times and are of fixed exact duration.
The P and N ref_voltages run-up switching timing is therefore not based on the "zero crossing" information.
One may wonder where the 18.5bit run-up resolution comes from when all the events in the pattern happen at exact fixed times and are of fixed duration (and therefore the charge balance is given by the number of active Ps and Ns within say 20ms frame).. :-//
How the additional run-up measurement of the "exact" time between the two "zero crossings" improves (xxx times) the balance calculation?
Could you elaborate on the exact principle/formula, plz?
-
The variable part part is kind of either positive or negative. So the name may be confusing.
The resolution from the run-up part is limited. I get something like 1000 counts, so about 10 Bits. Even with more intermediate steps the resolution would not be that much higher, as there is the residual charge at the end of run-up as a limiting factor.
The 18.5 Bit resolution level is reached after the fast part of the rundown: this brings down the step size from some 20 µs to some 250 ns with half the reference weight. This gives a little more than 8 Bits. To the resolution. A faster modulation during run-up could give a little more resolution there but reduce the part from the run-down. It would not change much of the combined resolution that is given by integration time (e.g. 20 ms) divides by time resolution (e.g. 250 ns) times 2. The extra factor 2 comes from having either a positive or negative reference. Some of the integration time is effectively lost to the fixed phases - so some 10% of the resolution is lost.
The timing of the zero crossings could (with sufficient processing power) be used to get finer feedback during run-up. This gives more resolution from the run-up part, but it reduces the part from the rundown. It may still be helpful, but not for more resolution. A more accurate feedback reduces the average voltage and this way get less of the slow DA effect. The Solartron DMM kind of uses the exact timing of the zero crossings and a continuous integration with no rundown - however this is a different type of ADC.
-
Ok, so my example above with 1000 P+N counting is still valid for your run-up (we still discussing the run-up only) and it is basically what you get today in the run-up. The additional information for improving the resolution comes from the rundown and from the info on the residual at the beginning (and the end) of a measurement (the measurement = 1PLC = 20ms).
-
my rambling are not kleins', I'm just trying to infer each part of how these work,
My understanding of it is, lets say you feed in 7V, by feeding it though a fixed resistor we get a current or coulombs per second, in this case 70uA for 20ms, so removing the time component is 1.4 micro-coulomb,
You need to cancel out that amount of charge to get the integrator back to the switching point of the comparator, of which you have 2 other voltages you can feed through a resistor to cancel that charge,
In our current case that is 13.4V (2.68 micro coulomb), and -12.2V (-2.44 micro coulomb), it may be easier to think of these as 2 lines of a fixed slope,
Your trying to measure as best you can the ratio of these 2 that cancel out the charge, while still adding up to 100%, e.g. 40% negative and 60% positive. of which there is only 1 point it can happen, you can see this in the modulation pattern if you imagine first using all the positive bits, then using all the negative bits,
The pattern is mainly there to ensure at least 1 step of the opposite reference every now and then, for charge injection reasons, (or so I assume) but could also be to deliberately make the integrator go a bit further from 0,
so lets say you only counted the modulation patterns, a total of 1000 for a 20 step pattern, you can think of it like a triangle with a hypotenuse of 1000, with the +Count and -Count representing the contribution of reference, now that duty cycle is a fixed number after your conversion, but as its rare it will perfectly cancel with only those 1000 pattern steps, you are left with some residue, in the example image, you would use this to extract extra information, and move the true duty cycle amount to correct out that residue,
I was trying to determine this point by using the zero crossings to sum up the ratio of time above 0 (an excess of charge has been removed), and below 0 (there is still charge to be removed) to extract more information out of the pattern, on top of the residue, in a sense trying to make it behave like a much faster modulation frequency, but was still unwrapping the math on it, as its not as clear to imagine as the residue example. best example would be capturing lots of smaller triangles, and using them to reduce the uncertainty of the total count / residue
The PWM approach I was describing above could be used as a true PWM, by changing the ratio of positive and negative. per pattern, but in reality, the steeper the slopes those references contribute, the more information that can be extracted by the residue, as if you imagine it, if this triangle was a lot taller, moving that duty cycle to the left to remove the residue moves the duty cycle point less, with the most usable information extracted when that residue contributes only about 1-2 counts,
-
@Rerouter: Sure, the "PWM" like pattern was the thing we discussed a while back, and it is still a pretty sexy solution for how to improve the run-up resolution, imho. I even tried with simulation but had problems with keeping the integrator in the range (my naive approach perhaps).
I was thinking you really do some improvements of the run-up resolution in the current fw (with the additional zero-crossing timing information) therefore I asked.
I can imagine myself to use an FPGA, do the "fixed time pattern schema" as it is today, and, to timestamp the zero-crossings with 1 clock resolution (say 10ns), to save all the timestamps into the FPGA's memory, and (after the run-down) to provide the final calculation with the set of timestamps saved.
The question is how to incorporate the zero-crossing (run-up) information into the final calculation.
-
The zero crossing information would be used to reduce the uncertainty of that final count value to a fraction of a count, e.g. using an example of 7V, (I am fixing up my calculation to reflect this)
etc...
the first triangle is 16 Count+ | 62 Count-, 20.5%
the next triangle is 65 Count+ | 258 Count-, 20.12%
Third 303 Count+ | 1197 Count-, 20.20%
you can also use the sums of each triangle, e.g total for those 3 would give, 20.199%
after you have all of these, you get the deviation, weigh them by there uncertainty, and can use that to shift the final count a little before the residue is applied.
-
@Kleinstein: do you switch the ADC's input off during the short 1us_P+1us_N phases within the pattern (run-up)?
@Rerouter: isn't it such that all that zero-crossing uncertainties within 1000 patterns transform themselves into the final run-up residual as an offset?
-
I'm trying to work that out, the math is a pain for someone who never took calculus, and it may end up being a below the noise contribution,
Edit: the residue is due to discrete correction steps in the form of the entire pattern, but it may end up being about the same
-
For the current multi-slope ADC with rundown phase, the exact timing of the zero crossings does not give extra information on the DC voltage. The only part of the run-up that counts is the charge added from the references.
The position of the zero crossings in theory has some information about higher frequencies present, but his would be a mess to extract and we a usually not interested in those higher frequency part.
In theory the timing could be used in a different type of ADC, using only the run-up and the exact timing. This is about how the solartron DMMs work. However this is a different kind of ADC with limited resolution (or very slow).
The timing could be used to a more accurate feedback during run-up. However this is not easy and it would not help with overall resolution. It could help with keeping the average integrator output voltage more constant and this way reduce the DA effect.
I have a crude idea for a more PWM like feddback - however it is too slow for the AVR - more like something for an ARM or FPGA. Still I doubt it is worth the effort for maybe a fat 2 smaller cap and a reduced DA effect that should be quite small already.
-
@Kleinstein: do you switch the ADC's input off during the short 1us_P+1us_N phases within the pattern (run-up)?
@Rerouter: isn't it such that all that zero-crossing uncertainties within 1000 patterns transform themselves into the final run-up residual as an offset?
I only use the µC internal ADC in the run-down phase and with the integrator in hold mode when sampling.
-
well at least for the AVR limitations, you may be able to extract some more info by doing a modulated slow rundown to reduce the average slope,
edit:it would still leave us at pretty much the noise limits you have given... Now I suppose to figure out how to actually sum that up from what we currently have to cross check it. see if we have nay room for improvement, and to work out how much PSRR will hurt it.
edit2: this leaves open the question of what bandwidth range we need to calculate the noise across. for the reference that is pretty easy as that is heavily bandwidth limited, but the ADC is less clear,
-
@Kleinstein: do you switch the ADC's input off during the short 1us_P+1us_N phases within the pattern (run-up)?
@Rerouter: isn't it such that all that zero-crossing uncertainties within 1000 patterns transform themselves into the final run-up residual as an offset?
I only use the µC internal ADC in the run-down phase and with the integrator in hold mode when sampling.
I mean - do you switch off the input of the MS ADC - the "input of the integrator" during the 1us+1us run-up phases?..
-
Everything points to it having the input always on for the entire 20ms period, then off for the run down, the references having a ferrite bead I take as a hint,
Now for the noise calcs, will involve working out the bandwidths of interest for the various ADC parts,
reference noise is mostly done, with the LM399 being the dominant noise source, by about a factor of 10,
-
@Kleinstein: do you switch the ADC's input off during the short 1us_P+1us_N phases within the pattern (run-up)?
I mean - do you switch off the input of the MS ADC - the "input of the integrator" during the 1us+1us run-up phases?..
Of cause the signal input is not switched off during the 1 µs fixed phases.
A possible target for an improved run-up phase would be to get less average integrator voltage to reduce DA. There may be a few options for this, but one has to be careful not to cause other errors - the 4 step version I initially used was such a "solution" that was a little better with DA, but caused other INL errors.
However I would call this more like a later software option to play with, in case DA turns out to be a serious problem.
The question on which bandwidth to calculate the noise for is a good one. Here it is not only the bandwidth, but also the frequencies of interest as some noise sources are frequency dependent. Even the reference part only gets easy with the extra filter at the input.
The BW and frequency range is different for different noise sources. Also the way of using the ADC makes a difference. The main case of interest would be a simple 20ms signal - 20 ms zero cycle. So the lower frequency limit should be at some 25 Hz. A different (longer) sequence could include lower frequency noise.
One difficulty is going from noise densities for the parts to RMS noise for a conversion or better the difference of 2 conversions in a row.
-
I suspect that may be what C37 and C17 are for, to set the low pass bandwidth of the input, to reduce the maximum frequency range,
as a minimum, our input slew rates give us the bandwidth required to represent that slew rate, with 25K input resistors that would be about 18KHz needed for the op amp to represent it, we can also use pin capacitances to start reducing the maximum bandwidth of each part to get sensible numbers, also working out, but I suspect the modulation actually lets us discard most of the lower frequency noise,
-
C17 and if used C37 are used for adjusting the settling of the integrator input. So more a question of loop compensation.
C37 may also keep away the very high frequencies (e.g. > 20 MHz) away from the integrator. Both caps sit at a virtual ground point - so they don't act as a low pass with R1,R2,R3. The effective resistance they see is more the input impedance of the integrator of some 10-100 Ohms.
For the input noise the upper limit is set from the integrating action. The integrator gives an 1/f factor - so higher frequencies get increasingly less important. This reflects the input aperture integrating over some 20 ms and thus the sin(x)/x response typical for integrating ADCs. This frequency dependency applies to to the input buffer, but also the resistors and the integrator.
The lower frequency limit is set by the AZ cycle, so normally doing a 20 ms conversion of the input and 20 ms of zero reading.
-
IMO, as you have this modeled, any chance you can run an AC sweep to work out what frequencies we do not have to care about,
The NE5534 thanks to its small signal gain only has a bandwidth of 500KHz, this is what the comparator sees, and the ADC only has a 45KHz bandwidth,
If we assume just this part, then the NE5534 may be up to ~2500 nV of noise, and the ADC amplifier about 6000 nV of noise, just from the devices alone, and seem to get really swamped to crap by the resistors when the BW is still so wide,
My assumption on the actual frequencies would be, that anything below 1/8th a frequency of interest would at most be able to only add half of its amplitude, so a high pass 3db point If I'm not confusing myself, so taking this forward for the integrator, it is based on slopes, the bandwidth required to represent the possible range of slopes is 5KHz to 8.2KHz, so on the low end, we can probably discard noise sources under 625Hz when it comes to op amps and resistors, (PSRR and external noise still count here.)
As for any kind of low pass effect on the high end, I'm wondering exactly where we can draw that line, as if the 1/8th thing holds, it allows us to significantly cut out the low frequency components of the NE5534 (105KHz high pass) but the further this can be reduced the better, (The MCP6002 would not get this as you measure with no effective slope)
-
IMO, as you have this modeled, any chance you can run an AC sweep to work out what frequencies we do not have to care about,
Below the AC sweep of the integrator and slope ampl. I do not have a working NE5534 handy. Also the integration ampls are the universal models with important params close to the original ones.
EDIT: two versions: 25k + 2n2 and 100k + 560pF
REMOVED - wrong DC offset.
-
I don't have a good computer controlled frequency generator. So taking AC sweeps from the input would be difficult for me. Anyway the simple integration over a defined window (e.g. 20 ms) is well handled from the theory side.
The noise of the comparator is not critical. Any error the comparator may make can later be compensated by the µC internal ADC. The comparator is only used for a kind of 1st approximation so the range covered by the ADC gets smaller. Noise of the comparator would only enlarge the range to be covered by the ADC. Currently it looks the extra width due to noise is very small, maybe only some 2-5 LSB or so.
The relevant BW for the NE5534 noise is the one from the ADC. The noise from the MCP6002 is relative to the slope amplifiers output, so something like a factor of 20 less critical than noise of the NE5534. The MCP6002 is not low noise, but still not 20 times worse than the NE5534. The relevant frequency band is from some 25 Hz to around 50 kHz. One can experimentally see this group of noise sources, that set the error in measuring the integrator charge. Repeated readings of the µC internal ADC at the end give rather repeatable numbers. This noise is not much higher than the quantization noise of the 10 Bit ADC. So these noise sources would only be a problem with more gain before the ADC (or a lower reference voltage).
The other group of noise sources are those that set the charge actually going in and out from the integrator. Due to the integrator action this noise type gives more weight to low frequencies. The main relevant frequency range is from some 25 Hz to some 100 Hz or so. The main noise sources here are the resistors R1-R3, the integrator (U11), the reference with amplification, variations in charge injection, jitter of the controls to the 4053. A special case here is reference and amplifiers noise in the 50 KHz band, that gets mixed back to low frequency with the modulation. The noise from U11 is amplified by about a factor of 2.
-
It was more to figure out if my theory had ground, however it would appear that it does not, or at least not to the same level I was hoping for, we have a low pass filter on the input to the integrator of about 1KHz, which is nice, as that reduced the noise bandwidth we have to calculate for the buffer amp and similar to practically nothing compared to the rest of the system,
the integrator output has a high pass of about 330Hz, which shaves something off, but not as much as I was hoping to see,
Most of this is me working out how this is calculated without having to lean on spice too hard, and then how to figure out the specific contributions of each tradeoff, you quoted a noise figure, but I do not yet know how to calculate that number for a system like this, so I'm hoping to learn it.
IMO, does anything change if your voltage source is 0V DC with your AC signal?
-
With 0V DC..
-
I think the simulations still have some type of flaw, like having the integrator output going to saturation. For the simulation it may help to add a large resistor in parallel to the integrator cap.
@REROUTER: the integrator has the normal 1/f transfer function. The lower frequency limit is set by the integration time.
Calculating the noise is indeed not easy. Part of the problem is that some aspects are better described in the time domain, while other parts are better handled in the frequency domain. When analyzing the system in detail in the frequency domain one likely has to include the input mux and the kind of chopping action done with it.
I have not done a detailed analysis, but only an approximate one.
The main idea also valid for a more detailed analysis is the separation into noise for charge actually going to the integrator and the final measurement of the residual charge. Using the result upfront, the important part is the actual current going in. The residual charge measurement noise is at least for an integration time of 20 ms not relevant. The final charge measurement is also the easier part: in short it is some 25 Hz - 40 kHz frequency range, and noise mainly from U11 (with a gain of 2), the NE5534 and R12. This is some 15 nV/Sqrt(Hz) * 200 Sqrt(Hz) = 3 µV. This noise comes in twice at the start and end of the conversion. The noise is relative to the integrator output and would thus see the integrator gain ( = 20 ms / R3 *C11 ~ 200) for the signal. So for the input this would look like some 2*3 µV/200 = 30 nV. A faster integrator / modulation could reduce the effect. A much larger integrator cap could increase this noise.
For the current going in, the difficulty is especially the frequency range. This is not just a single range, but a combination of ranges due to the mixing action. The simple approximation is a bandwidth of some 50 Hz (= 1/ 20 ms) and assuming an effective frequency of some 25-50 Hz.
-
Here is the source, you may play with it.. Added 10Meg in parallel to the integration capacitor.
@Kleinstein: you may suggest the right value for it, plz..
-
It is rather confusing to use an OP with input offset. In all cases except for the 1 mV case - that just matched the OPs input offset, the integrator is in saturation and the simulation thus not giving the normal behavior with feedback.
-
Removed the simulations with input DC offset. There is the one with DC=0V left.
-
Due to the offset in the OPs model, the integrator still goes to saturation. By chance the 1 mV case did not saturate, even without the resistor. So the only good one was the 1 mV case. 0 V DC level and no OPs offset would be even better as it is less confusing.
-
The simulation looks more feasible with, for example, 2xLT1022..
-
Ok. I think I understand where that timing information sits. Being so close in design to a delta sigma means it could actually be treated as a delta sigma with a sampling rate of 50Khz. This should mean our quantisation noise is already shifted way out of band. And could be digitally filtered.
I am struggling to find any references that detail what happens when the feedback clock rate is not equal to the sampling rate. But it is a solid start on the math to descibe the noise high and low pass filters.
-
When you look into the sigma delta ADC datasheets you may see a lot of pictures with clock vs. sampling rate..
Some math is here as well
https://www.youtube.com/watch?v=z9u-QTDAeaM (https://www.youtube.com/watch?v=z9u-QTDAeaM)
-
found that video already, have re watched it about 6 times to try and get every last part of it to stick around long enough to understand it, But does not make clear what happens when say, the feedback clock is 50KHz, but the sampling clock is 1Mhz, as it would be walking its pattern between feedback clocks, and how it would deal with the small reversal each pattern, it certainly captures more information about the crossings, which would be equivalent to a faster sample rate, but not sure if the modulation noise is being hidden by the sampling rate being at the same frequency
edit: his math is saying the integrator should appear as a ~4KHz low pass filter for the input, so in the same ballpark as what the simulation gave us, and certainly helps deal with input noise.
-
There is some similarity to an sigma delta ADC, but there also is a significant difference. We don't care about the position of the zero crossings during run-up. The only thing that is used is the number of comparator readings (and thus reference settings) of one type (e.g. positive).
There may still be some help from the SD-ADC noise calculations, but the main part is different direction.
I think the more helpful part might be looking at the noise of chopper / AZ amplifiers.
-
Yep was only planning for noise calcs. As it is effectivly the same circuit and being sampled the same way for the modulation (and possibly run down phase with different parameters) and i now have an idea where oversampled sampling but same modulation would live. Its equivilent to a delta sigma with a flash ADC instead of a comparator.
Then the adc sample. Well it already only has 45KHz of bandwidth so it really cuts things down.
Main takeaways are the input noise is filtered at 1-4KHz. The quantisation noise. (Uncertainty in your pattern sampling) is reduced by the delta sigma math. And technically reduces the rundown uncertainty aswell. But working out those numbers will take me some time.
We also have from the simulations that where run that the integrator output is quite the low pass filter. So we should not have to add in much of its noise. Leaving the slope and adc diff amp to be calculated the conventional way. As they will still be the primary noise sources if I am interpriting it correctly
Edit: i think I may have the output low pass wrong. As it tracks the input with gain it may not have a dominant pole at all. And instead would be based on the slope amp bandwidth)
-
There is no 1-4 kHz low pass filter at the input. Quite some of IMO's early simulations run the integrator to saturation and thus don't work right. The added resistor to keep the integrator from running off, causes a low pass type action instead of the integrating action (low pass with extremely low corner frequency, e.g. in the µHz region).
I think the comparison to the sigma-delta ADC is more confusing than helping: for the normal ADC operation there is no oversampling. It is more like the classical dual slope ADC: integrate over a fixed interval (e.g. 20 ms) and than measure the charge.
The feedback from the references during run-up is not about quantization, but counting charge and keeping the integrator from saturating. For the noise, one should consider the currents from the references as part of the current going in - the switching pattern is quasi fixed for the small range noise is concerning. One can even do this for the rundown part.
So the noise can be divided in the 2 groups: noise effecting the charge going in and noise measuring the residual charge.
For longer integration (e.g. > some 1-10 ms) the main noise comes from the charge actually going in. The main noise source are the resistors and the slow part of the integrator.
Quantization noise comes from the µC internal ADC only, when measuring the final charge. However it is at a low level and not an important source anymore (for 20 ms integration). If needed one could even reduce it even further: e.g. with less asymmetry in the the refs. and thus more resolution form the slow slope part and more gain before the ADC.
In theory one could look at the run-up part data as a kind of 1 st order SD converter. However the resulting resolution is to low to be useful. It is not even useful as a helper, as it also includes the main errors from the normal ADC operation. So this part is not helping. The simple theory to the SD ADCs has another problem often ignored: it applies to the average noise, or the case with a significant external signal. With a DC signal, the quantization is no longer white noise and there are so called idle tones. So a SD ADC used for a quasi DC signal has additional complications.
-
sorry if I sometimes seem to repeat myself, there is a bit of this that I am trying to get my head around, and lack good examples elsewhere of it, I was way off on that corner frequency and should have stuck with my old math, the hope with the delta sigma stuff was mainly for a second way to approach the problem, there is not many resources out there for 3 or more slope converters, but the internet is overflowing with really detailed breakdowns for delta-sigma, including the concept of modulation noise being moved out of the frequency range your measuring, which may be a way to reduce the effects of crosstalk and the switching, but your right, the math behind it, while extracting information, does not actually give a quick and computationally cheap way to reduce errors in the slope measurement. FPGA yes, Micro no.
Based on a limited gain of 1,000,000, I think we can represent it as a virtual resistor R2 on our integrator, with a value of 25Gohm, so in this circuit there should be a 0 gain cut off somewhere around 18KHz, "IF" this is the case, the math for the rest of the noise works out nicely (not yet counting power supply noise),
during run down I would expect about 200uV RMS @ 500KHz bandwidth noise for the comparator,
during residue measurement I would expect about 750uV RMS @ 45KHz bandwidth for the ADC, or almost 1 full LSB of the ADC when treated as Pk-Pk, but in reality the breif moment the ADC sampling cap is open cuts off most of the low frequency contributions making it far lower than this in practive.
The reference noise seems to be mostly from the input resistors, ending up about 2800nV @ 18KHz bandwidth per reference if my math is close to the mark,
And for Charge going in, assuming 1 reference, and the input, there is about 4000nV @ 18KHz bandwidth of noise, this is not yet counting the buffer, so a noise current of about 160pA, or a charge noise of about 3.2 pico-coulombs RMS, out of about 800 nano-coulombs for say a 1V signal, or about 1 part in 250,000, I wonder if this is why some designs went for a current source method for there references.
Edit: eventually I'm going to have to write up a nicer way of representing the sum of all these noise sources, as the bandwidth limited parts being summed with higher bandwidth parts is getting a little complex, and I now fully understand what you meant about R12 being most of the noise in the ADC,
-
I have also not found much on theoretical papers on the noise of a multi-slope or just a dual slope converter. There is a little in the HP journal article about the 3458, but not much. After doing the noise calculation and looking back on the 3458 design some points look a little odd - so not sure they had a good theory on noise.
For the calculation of the noise the extra slow phase in the rundown is more like a side note. So good noise calculation for a dual slope ADC would also be a good start. So I had to make my own thoughts / calculations about the noise. It is only approximate, especially when it comes to 1/f noise and an effective frequency to use.
For the µC internal ADC noise and the slope amplifier, I also get about a noise level at around the quantization of the ADC. This is also supported by measurements (e.g. just reading the ADC a 2nd time).
For noise numbers it is common to have them relative to the input, not the output.
For the charge going into the integrator, the modulation is for most of the part not an important part. For most noise sources one can calculate without the modulation. So there is not 18 kHz BW, but more like the ADC input transfer function with a 50 Hz ENBW. It is only the switching related part (e.g. jitter and scattering in charge injection) where the modulation frequency really matters. Another part where the modulation matters is a small odd part of the reference noise, mixed back from some 50 kHz down to near DC.
My approximation is to assume an bandwidth of one over integration time (should be correct and is used for SD ADCs too). With the 20 ms signal and 20 ms zero cycle most of the amplitude would be at around 25 Hz and some at 75 Hz , 125 Hz and so on. However the contribution from the 75 Hz and up should be rather small, as there is a 1/f part from the Fourier components of the square wave (+-1 in software) and another 1/f from the integrator. So the 75 Hz part should be something like 1/9 the amplitude and thus 1/81 the noise power. For this reason I take an effective frequency of 25 Hz as an approximation, knowing that this slightly overestimates the 1/f noise. The data (e.g for the OPs) are usually not that accurate anyway. For the noise sources one can than use a Spice simulation (noise calculation) or calculate by hand. The noise sources are before integration and are thus directly comparable to the input. Ideally one would integrate over the sin(x)/x transfer function, somehow taking into account the lower frequency limit from input chopping (AZ mode).
Because of the sinx/x function it is mainly the low frequency noise (e.g. 50 Hz BW with an effective frequency of some 25 Hz) that matters here. This means for the relevant OPs (buffer and slow integrator it is the 25 Hz noise density that matters).
There are other noise source that are difficult to calculate up front: the jitter of the control signals and variations in charge injection (e.g. with supply, but also intrinsic to the switches). Jitter is also complicated as jitter often tends to be not just white noise, but often with a large 1/f part. The relevant frequency here is the modulation frequency.
The main reason for calculating the noise is in my few to see which parts / parameters are important and to help optimizing some parameters like the integration cap or choice of OPs.
I somewhere have spreadsheet to combine the known noise parts together, for my ADC and a few ADC from DMMs where I have plans and that can be handled with the same framework.
Using current sources instead of just resistors from a reference level helps a little with noise, but only a tiny amount. In the current sources the voltage over the current setting resistors tends to be smaller and this increases the noise - so if not done carefully the small advantage may be lost. I think the use of current sources is more like for INL reasons, as the current is not directly effected by the voltage at the integrator input. Still it depends on the settling of the current sources. The current sources also eliminate the switch resistance - however this also means there is no compensation with the switch resistance at the input.
-
A good topic for a PhD thesis, indeed..
Btw, in those "universal opamp models" in the simulation file above/below you may define the current and voltage noise density levels (currently zero) and corner freqs such you may do the noise analysis then.
Fyi - the "Slew rate" is in V/s, therefore 10Meg is 10V/us
PS: an another source of noise may come from a switching "asymmetry" caused by MCU's instructions "jittery".. An LA hooked at the signals may help.
Also I've fixed ;) the input 1mV offset of the OPA1641 to 0mV and now the result with DC=0V looks better..
-
If a PhD thesis was that easy to get by brute force math, I would happily take it :)
Working from the reference area back towards the ADC with frequency noise bins, the reference ends up filtered way more than I originally expected, at U9's input, it looks to be down to about 300nV RMS noise over a 100KHz bandwidth in big part to R22/C13 and some of its own roll off with C210. (this is working off the assumption of C13 to ground while I unwrap its actual characteristic)
Mainly now working out how to break apart the 2 op amp circuits to forward analyse these, the self converging parts are the hard bits, e.g. the bias point of U8's inputs,
edit: ignore the blue notes on noise for now, Still working through that part with the binning, and these will not match it
edit2: C13 through feedback action will end up servoing out most low frequency reference noise referenced to U9's input, but in turn will couple any noise from the -12.2V reference rail straight back into the reference input, which at that point will have all the resistors and op amp noise summed in, as the attenuation of the references noise is currently so low to the input, is there any issue with rebasing C13 back to signal ground, at present it is a stronger signal than R22 at only 1-2 Hz,
Edit3: caught my error in the gain calculation, had one term reverse, all ok with C26/C28 now
-
The Idea of having C13 relative to the -13V and not to ground is to an even lower corner frequency. This would not effect single conversions, but only has an effect on the AZ cycle reading signal and zero. For the zero reading the reference noise would have less effect. So the idea is to average the reference to make better use of the ref. signal during the zero reading. Looking at this in the frequency domain this gives some 25 Hz range noise than can come back.
There is some effect on the higher frequency noise - a little more noise for the positive reference, but less for the negative.
Effectively using the -13 V level works like a capacitance multiplier (about x 3).
For the reference noise part there should be 2 important frequency ranges: one is the obvious low frequency part, like < 50 Hz. Actually more like < 5 Hz and some 20-30 Hz (or some 10-20 Hz if a 3 step cycle is used). The main purpose of C13 is to suppress the 25 Hz part a little (for noise, already some 10 dB attenuation is quite effective. So one might get away with a slightly smaller C13 cap.
The other (I think some DMM design overlooked this) is the higher frequency part around the modulation frequency and some subharmonic (e.g. 50 KHz +-25 Hz , 25 kHz+-25 Hz), that can be mixed back to near DC. So no real need to worry about large bandwidth, but still a little avoidable noise at much higher frequency. Here C26,C28 and C13 help to keep this noise low. The LM399 has quite some white noise part (some 100 nV/sqrt(Hz)). Without C13 the measured noise in deed goes up noticeable.
Edit: for the noise, one can not use local bandwidth and multiply the noise densitiy with local bandwidth. One kind of needs to calculate the transfer function from the noise sources to the output or alternatively to the equivalent input. Only than at the end one can look at the relevant frequency bands and use the BW. This is something where Spice can be quite some help, at least to check if one gets the transfer function right and does not overlook some filtering or signal path. The reference amplification with C13 from the output is quite complicated on it's own to do the math by hand.
-
All good, it can stay at -12.2V for now, there will be a feedback loop that may cause issues, but that can be a later thought on how to mitigate it.
now just getting stuck with how to sum up the noise for U8 pin 2, as it is all a bit self referential, R201-2 Noise is summed with a gain of 2 into the 13.4V signal, which is then attenuated by the 47/2K2 divider, where it is summed with a gain of 2 to -12.2, where it returns to the same node via R201-3 and R201-4, this is a bit of a head scratcher.
-
With C13 to the negative ref. The Part around U8 and U9 gets quite tricky. So I would just leave that to a spice simulation. The extra small shift is another complication - though with so little shift, it should not change the noise much.
There is another feedback path around U9+U8 through C13. However stability is not a problem if C26,C28 are there a in a reasonable range. The point is that C26*R4 and C28*(R6+R7) should be well slower than the OPs GBW, but faster than C13*R22.
-
Well not sure how the spice simulation will differ, but I've ended up with a value of 63280nV RMS for the positive Reference, and 1080nV RMS for the negative reference at full bandwidth, at the op amp outputs (1MHz)
For your sub 50Hz bandwidth it would be 1080nV for the positive and 890nV for the Negative at the op amp outputs,
due to the arrangement, any coupled noise will always have a gain of greater than 1 on the output of the positive reference, however the integrator does a quite good job at knocking this down by the time its come back around, at 8.7KHz (refined math) for a single input, the AC gain of the integrator becomes 0.5, as the capacitors reactance is half of the input resistance, it never reaches 0, but under that point most of the contributions are heavily attenuated. e.g. at 50KHz, the AC gain is only 0.086, an input + a reference reduce the effective input resistance to half, so the low pass pole becomes double, about 17.4KHz, or a gain of 0.17 at 50KHz,
Downside is the low frequency noise gets boosted by a large amount, at 50Hz, there is a AC gain of about 60 on the integrator, but as we are starting with rather low noise this should be ok
As I begin to calculate the noise forward into the ADC, I expect the total amount of noise to be slightly higher than my blue notes, but it is much more heavily shaped towards lower frequencies, I wish the OP07 had its broadband noise graph another decade longer, as at present it is the dominant noise source for anything over 100Hz on U9, if you open up its bandwidth to calculate forward with binning over the entire range it becomes a real problem, (assuming a flat 10nV/rootHz), and ends up contributing far more high frequency noise,
edit: the attached images are the noise density at the output of the references, as the frequency goes up, it would currently converge towards a gain of 1 for the positive reference, so towards a value of 10, as the low pass elements mean the rest of the influences are attenuated out. better op amps here would only remove about 60% of the noise if we used an OP27, the negative reference would not even see a 1% change.
edit2: U8 is an inverting amplifier, so I had to correct the noise graphs, the negative reference ends up much lower noise. left wondering if a better design could be with 2 inverting amplifiers so both have essentially no high frequency noise due to the roll off towards 0 gain, this would reduce the total noise of the positive reference 98% over the full 1MHz bandwidth,
The goal is it would not just attenuate the internal noise, but any coupled or external noise as well
-
As low a noise as you get out of the references, the integrator AC gain at low frequencies is the real killer, this is just the references contribution to the integrator output, I have not yet summed it in with the integrator op amp and resistor noise or input buffer noise yet.
at 50Hz BW, you can expect 50uV RMS for Ref- during rundown, 100uV RMS for Ref- during modulation, and 60/121uV for Ref+ during these times, During rundown you end up with 20% less noise over 1MHz, during modulation you end up with about 60% more. this is all with 25K input resistors,
The input resistors noise swamp out the reference noise, reducing the full bandwidth contribution of the positive references noise to just 11% more noise at the integrator for that reference.
-
The relevant reference point for the noise is usually the input. For the calculation it may be easier to follow the signal to the output and than divide by the transfer function from the input. When taking it relative to the input, the low frequency gain of the integrator is not a problem - it is more that the gain going down with frequency is a big help against higher frequency noise. So for the part going through the integrator the relevant noise is the low frequency part.
The input resistors to the integrator can be one of the larger noise sources. It is not only the resistor at the input, but equally important the other 2 resistors together. These noise sources set a good mark so see if other noise sources are really that relevant. It is kind of a good sign if the resistors are the largest noise source - with 50 K resistors, the 3 resistors together give the noise of a 100 K resistor and thus some 40 nV/Sqrt(Hz). This is a very good noise level. The 3458 is supposed to be at some 80-150 nV/sqrt(Hz).
The other point of orientation is the noise of the reference - this can be a significant noise source, if the signal is near null.
For the reference amplification one has to be careful replacing the OP07 with an OP27: I did that the other way around, because of the relatively high current noise of the OP27.
-
Yeah, flipping it to 2 inverting op amps would be a much better option than the OP27, was just investigating the contribution of each effect.
I am actually calculating both the input and output noise, in this case the input noise to the integrator just ends up the same shape as the reference outputs graph with a vector sum of 20.1nV/rootHz,
I prefer the output graphs as that is the noise I am trying to work out, and for the references really makes it clear how much of an influence each parameter changes, but I will agree the integrator one is not very useful right now without the other noise sources summed in, but it does show that essentially all the noise voltage will be very low in frequency,
the 3458's noise, where specifically and at what bandwidth is that measured, If it is the integrator input, I still have to sum in the noise from U2, U11, the resistors between, and the input buffers, this will raise it, equally I have yet to sum in the power supply noise, which may push this higher, still in the world of sums of squares, we have a good head start, if you can give me that bandwidth, I will work out how much we can sum in and remain under
-
The noise of the 7V buffered signal, atleast to the buffers input is attached, it is barely anything, and will be completely swamped by the input resistor. this is in large part to them being nice enough to list the LM399's output impedance, without that it would have been a real pain to calculate. the drop at around 100KHz is when some pole inside the reference significantly begins increasing its output impedance.
the current noise from the OP07's for all of the resistors in the reference really don't contribute in any significant way, a few hundred femptoamp * 5000 or 10000 ohms is still only 0.95-1.8nV/rootHz, only 1.6% of the influence of the voltage noise. but yes running through the math would put the OP27 out of running from current noise (did not update that part when I was comparing to it), and actual better alternative would be OP227 but flipping to inverting is still a more significant reduction,
The other big current noise issue point is the integrator inputs, when your measuring the ADC with all the inputs disconnected, the effective DC resistance of the integrator is near infinite, so the drift stops, but the influence of the current noise skyrockets, This is what I suspect C17 and C37's actual role are for, to cut that down to a reasonable level for mid frequencies
I would suspect from all this that the ferrites are only to deal with the crosstalk from the digital inputs of the mux, as nothing I have modeled so far would even begin to get into there attenuating range.
-
Ok, Think I found the graphs your referencing for the 3458, 50Hz bandwidth, If that is referenced to the input of the integrator, all is well,
The white noise portion of the 2 references are 20.1nV/RootHz for the negative reference, and 22.5nV/RootHz
We will beat the 10V range by a mile, has a headroom of about 160nV/Hz, the 22K input resistors would consume most of that, but as that is compared to an 8.5 digit multimeter, so I'm not too worried. and would not be hard to knock that down even further, and still leaves headroom for the buffers. on the direct input mux channel there is just a silly amount of noise margin, I'm going though adding PSRR noise now, this will hurt some things, but I doubt it will even touch that margin
-
Ok, PSRR really does hurt the current positive reference, it doesn't touch the margin, but it starts drastically increasing reference noise above 500Hz, in order to not be noticeable means ensuring the power supply noise to that op amp is below 40uV RMS
Edit: well crud, looks like I don't get a free lunch with inverting vs non inverting, means the negative reference gets a but noisier
-
How is the multislope adc doing? Summerbreak or board already in production?
-branadic-
-
Still playing with math, adding up error sources, and testing assumptions of various parts, Here is where it is currently, essentially only power supply left, These are KiCad design files, and your free to do with them as you please, right now no pins have been swapped so it will still support Klein's original software.
Learning all the fun little effects is taking me some time, as not all of them are the easiest thing to wrap my head around. and want to check that before I pack it up tightly.
-
This has to be one of the most ambitious hobby electronics projects ever?
Any chance of some straight PCB art work in a pdf, or some Gerber+drill files?
-
In the other thread about my ADC version, there should be some PCB pictures. As a first test there are a few changes needed (though not too many to be done with bodges - so usable for me), so I would no recommend a straight 1:1 copy. Also the combination of THT and SMD parts is a little unusual (but it helps with routing and bodges).
Just building a multi slope ADC around an µC or FPGA (whatever one is more comfortable with) is not that ambitious - it just has the combination of critical analog and a little slightly advanced programming.
The tricky part comes if one wants to aim for really high performance. Some of the thoughts in the layout are likely overkill, but it helps of one can exclude some known possible error sources. At the sub ppm level, there are enough small effects we likely have overlooked so far.
-
[...] The tricky part comes if one wants to aim for really high performance. [...]
Eight digits or bust! :)
-
As I saw the topic on the new Microchip's :) atmega4809 (28-40pin PDIP, 6kB ram, 48kB flash) the first thing which came to my mind was Kleinstein will certainly go for it with his next MS ADC revision:
..
- Event System for CPU independent and predictable inter-peripheral signaling
– Configurable Custom Logic (CCL) with up to four programmable Look-up Tables (LUT)
– One Analog Comparator (AC) with a scalable reference input
– One 10-bit 150 ksps Analog-to-Digital Converter (ADC)
– Five selectable internal voltage references: 0.55V, 1.1V, 1.5V, 2.5V, and 4.3
..
-
Respawning this old thread to share news in a development which are not worthy new topic yet, but fits this topic.
Since the original ADC I showed before in [1] and subsequently [2] and [3] is too old for me, I played with DIY ADC some more and put together different ADC implementation with residual integrator reading, kind of similar to HP34401 ADC. The integrator is never reset to any state, just continues integration where it left off before in previous reading.
This ADC is going to be a part of another project to be released soon (including full schematics and source codes, of course), so as a teaser I'm attaching a photo of my prototype (there is a few unneeded parts to be removed for final version) and quick INL test against Solartron 7081. Above 4V the linearity is quite repeatable (under 0,1ppm), below that it's getting significantly worse to around 0,3ppm - this is probably caused by variable voltage on integration capacitor, as a function of input voltage. I'll investigate this some more and try to fix it.
[1] https://www.eevblog.com/forum/projects/multislope-design/msg2378133/#msg2378133 (https://www.eevblog.com/forum/projects/multislope-design/msg2378133/#msg2378133)
[2] https://www.eevblog.com/forum/metrology/diy-6-5-digit-voltmeter/ (https://www.eevblog.com/forum/metrology/diy-6-5-digit-voltmeter/)
[3] https://www.eevblog.com/forum/metrology/diy-6-digit-handheld-volohmmeter/ (https://www.eevblog.com/forum/metrology/diy-6-digit-handheld-volohmmeter/)
-
jaromir I'm waiting to be surprised >:D :-+
-
The project I'm working on - and containing this ADC - progressed some more and I went from ADC prototype to final board. While doing this I made some minor touches to the ADC schematics and reworked the PCB layout. The 0,3ppm Himalaya below 4V went away, now I feel like I'm limited by noise of the setup - both ADC and Solartron 7081 I'm comparing against. Attached is typical INL result - just quick scan taking few minutes, to get more precise result I'd need to do multiple longer scans and average results. For now I'm OK-ish with this.
Attached is also photo of the work in progress project - ADC is the middle board. More updates will follow.
-
I came across the LD111A chip - the analog front end - (I found one in my junkbox, date code 83') and I started to read the DS (attached).
Is that a kind of the multislope adc? It does not seem to me a dual slope one - at the first glance..
I shortly was thinking an mcu attached could go to 5digits, perhaps.. ??? ::)
-
The LD111A is only the analog part of the converter. Together with the LD110 logic part the converter is a kind of low end multi-slope converter. However only with a multi-slope run-up and than with a simple and fast 1 speed rundown. With a difference control logic the analog part could likely also run in a dual slope mode.
The part with the AZ capacitor is unusual and can limit the maximum integration time. I am a bit confused that they suggest an integration capacitor scaling with the integration time - this is normally not needed for a MS ADC, but more like a point with a dual slope ADC.
Especially with the relatively low clock suggested for the LD110 the resolution is a bit limited. With the suggest relative high 8.2 V reference (should also work with 7 V) chances are the noise level is OK for higher resolution. There are still a few uncertainties about the amplifier's noise (especially 1/f noise part). It is also not clear how fast / accurate the comparator is.
The switching is before buffer amplifiers and thus possibly quite some settling time needed. So the speed of the run-up part could is limited.
AT first glance the ADC looks like it could be low noise and good linearity. Not so sure about the actual performance - they had an older version (non A) with seemingly some problems with linearity.
The quality of the input buffer could limit the linearity.
0.1 LSB of peak to peak noise suggests that with more timing resolution a higher overall resolution could be possibly, though not sure about 5.5 digits (still possible).
Reasonable performance even with a 20 mV Fs range suggests that the chip can be low noise, especially with a high FS range.
As a positive thing it looks like it did read the input for a relative large fraction of the time ( ~ 2/3), compared to the classic 7106 that only reads the input for 1/4 of the time.
I still would not use the old hard to get chip, but prefer seprate swiches and OP-amps. After all the LD111A is only the analog part with a few CMOS switches and OP-amps. It does not take that much analog parts to create a multi-slope ADC with µC control. Many µCs already include a comparator. With a µC and low offset OP-amps one can usually get way without an analog auto zero phase and do digital auto zero, like the AZ mode in higher end DMMs.
-
@Kleinstein: thanks, yeah, not suggesting the chip for new designs, nope.. Btw., in meantime I've double checked an old dmm here and I've found the chip - the 111 without "A" version - in one of my old dmms I still use as an ammeter only (the M-3001 made in Hungary, around 1980) and my 111A is a direct replacement, so it is a spare one :)
My first idea has been to play with the 111A analog part while bit banging the 2 control signals out of an fpga or mcu with a "better algorithm", thus getting a better resolution. The 111A allows 10uV resolution with 20.00mV setting DS says, so the chances really are it could work with more digits.. :D
-
The analog side should be OK for higher resolution. So in theory an upgrade to the LD110 for a 4.5 digit or similar version would likely have been viable. Not really attractive today with cheap ADC chips for the low end 5 digit range.
-
The analog side should be OK for higher resolution. So in theory an upgrade to the LD110 for a 4.5 digit or similar version would likely have been viable. Not really attractive today with cheap ADC chips for the low end 5 digit range.
Here you are - the LD120/121A combo with 4.5 digits (DS attached). The analog chip is identical with the LD111A (my bet the silicon is the same) and the digital chip does 4.5digits with more clocks per charge bucket. Also the DS reads better in the operation section. They wired the AZ cap (in series with a resistor) against GND there (I saw it with 111A as well). Pretty popular ADC chipset around 1980, indeed.
I still do not understand fully how they do the fast rundown, on the other hand you could do the measurement of the residual int cap charge with an ADC in the mcu, as Jaromir does above.. :D
-
The rundown is done essentially the same as the run-up, just with a 0 V input signal and stopping at zero crossing. Ideally there would be an extra phase to make sure that the final stop is always from the same direction. Not sure if the is implemented in the LD120.
By nature this rundown is very fast, like 2 runup-steps at most (e.g. 100 µs range) and thus only some 16 counts max. With external timing one could get higher resolution of this time - the LD120 uses a rather low clock (e.g. 168 kHz) by todays standards for a µC.
Not having a stop option makes it a bit tricky to use an auxiliary ADC for the residual charge.
-
PS: I've been digging more and more into it - here is the Siliconix 1982 Analog Switch and IC Product Data Book (https://usermanual.wiki/Document/1982SiliconixAnalogSwitchandICProductDataBook.761749618/help) with a lot of detailed info on it (from the page 263 up), incl. app notes and those DS above, ie. there is the LD122 with an external input buffer for low noise app and the DS there claims 1uV resolution with 20mV range, they use OP07 as the input buffer and LM399 for a 4.5digit meter..
Btw 260 pages with zillion of analog switches, in 1982 :)
-
there is the LD122 with an external input buffer for low noise app and the DS there claims 1uV resolution with 20mV range, they use OP07 as the input buffer and LM399 for a 4.5digit meter..
I became very familiar with the Siliconix LD series because Tektronix used them in their bench multimeters in the 1970s. The external buffer version was introduced to correct a defect in the original design; the integrated CMOS buffer has typical terrible CMOS common mode rejection which severely limits linearity of the converter. An external JFET precision operational amplifier corrects this somewhat.
Intersil avoided this problem entirely by performing the automatic zero cycle with the input to the buffer set to the input signal level, so the automatic zero corrects the offset at the common mode input voltage.