Multislope Design

[iMo]

Order a small ferrite toroid (ie smallest dia amidon 43 material), wind 10 windings for the oscope probe, cut the trace and go with a piece of wire through the toroid.

[Kleinstein]

The 74LV4053 works really well: considerably less EMI problems - this supports my suspicion the 4053 was the source, as the LV version has much smaller supply current peaks and is still a little faster.  The noise also went down a little compared to the HC4053 or HEF4053 versions. It's now at some 750 nV RMS and no longer much higher than what I know noise sources for (some 600 - 650 nV) with the current OPs in the circuit. 
After changing the critical OP I will likely also test the max4053, but I think the LV4053 has the advantage of not having the extra level shift stage,as it has no extra negative supply pin and using lower voltage FETs.

@IMO I may try the current probe suggesting in a few days. It looks a plausible way to check for current peaks, when one is anyway using bodge wires or THT ferrites for the supply. However the ferrite does have some effect. So chances are, I would not use a scope probe, but more like 50 Ohms termination at the scope.

[iMo]

Sure the secondary winding feeding a coax w/ 50ohm termination is the right way to do it. It transforms the 50ohm down to a fraction of an ohm of the bodge wire.

I've acquired today 3 various 4053 versions, ordered another 2 incl Maxim. A pity it is a mix of PDIPs, SOICs and TSSOPs.

While reading 4053 DSs - the 74LV.. versions usually work with 0-5V only..
Nexperia LV:

..the analog inputs/outputs (nY0, nY1 and nZ) can swing between VCC as a positive limit and VEE as a negative limit. VCC-VEE may not exceed 6 V. For operation as a digital multiplexer/demultiplexer, VEE is connected to GND (typically ground). VEE and VSS are the supply voltage connections for the switch..

The only versions with >10V working area are the CD/HEF/MAX4053 and 74HC4053 afaik..

[Kleinstein]

..
While reading 4053 DSs - the 74LV.. versions usually work with 0-5V only..

I know the LV version is for 0 and up to 5 V only. The 74HC and HEF4053 were also only powered from 0 and 5 V.  I tried some -0.7 V, but it did not really help, though from some typical curves the charge injection could be lower.
Die switches in the 34401 and my ADC are used in a kind of current steering way near zero voltage. So the actual voltage at the switches is about in the +-50 mV range - this is OK with a 0 and 5 V supply. If really needed I could shift the voltage to some +100 mV, but it would make things a little more complicated.

The main difference between the LV and HC version is that there is no separate negative supply, that could go up to some -5 V, and thus no internal level shifter circuit.  This and the likely smaller structure FETs for only some 6 V allows for less (about 1/7 ) current consumption and thus less current at the supply.

[iMo]

I think it is not about powering the chip's logic (all are 0-5V Vcc except the old CDs) but the voltage at the switches. The voltages at the switches with LV have to stay within 0..Vcc, with the others they could go from say -7V to +7V (while their logic is powered 0..5Vcc only).

[Kleinstein]

I think it is not about powering the chip's logic (all are 0-5V Vcc except the old CDs) but the voltage at the switches. The voltages at the switches with LV have to stay within 0..Vcc, with the others they could go from say -7V to +7V (while their logic is powered 0..5Vcc only).

The voltage at the switches has to stay within about -200 mV to Vcc+200 mV. A little more than the supply is allowed, more would cause extra leakage. Only with a large current (some 100 mA for the LV) beyond some 600 mV could cause real trouble (e.g. latch up). So the maybe -50 mV in peaks are not a problem to cause significant leakage. The worst case current is limited to some 300 µA and thus also safe.

The 74HC4053 in the 34401 is also only powered from 0 and 5 V, even with a ferrite at pin7 and thus possible positive peaks of some 50 mV there, so that the input can be even more negative relative to pin7. The HC4053 can tolerate a negative voltage only to a little below the level at pin 7. With pin 7 tied to ground the limits are about the same as with the LV version.

[Andreas]

The only versions with >10V working area are the CD/HEF/MAX4053 and 74HC4053 afaik..

And the MAX4053A is the only one with integrated level shifters.
On the other devices you have to add external ones if working outside +/-5V in a 5V logic system.

with best regards

Andreas

[Kleinstein]

I changes the "low frequency" OP in the integrator from the not so good TLE2021 to an OPA1641. It did some improvement in the noise and the settling of the integrator also got faster as expected from a faster OP.
Noise went down to the 700 nV RMS range for the simple difference of 2 readings (simple RMS). Still a little high than hoped for and the noise source I know off would cause, but I consider this good enough for the time being.

The MAX4053 did not give an improvement, at least not with an extra ferrite at pin 7. It even looks like charge injection seen as the difference between the slow and fast modulation mode is a little higher. For the current circuit the I got the best results from the 74LV4053 Next best was the  CD74HC4053 from Ti, HEF4053, max4053 and 74HC4053 from ST with a ferrite were about same level  and the worst  HC4053 (ST) without a ferrite was worst. As the LV4053 works good - I see no need for a further search.

It still looks like the fast modulation gives more noise, so I might test a slower modulation. The downsides of slow modulation are a stronger DA effect (should be OK down to some 20 kHz), a little longer rundown and more noise from reading the residual charge due to the larger integration cap - this would lead to more noise for short integration (e.g. < 5 ms). So one might have to find a compromise between good performance at >= 20 ms integration and 0.1-1 ms integration, which would be about the lower limit.

After noise, now comes the tricky part in building a high resolution ADC: that is linearity. My earlier version had a DNL problem just in the middle of the range, but I found a solution for this. So far it looks like the DNL is good. My crude test is looking at a slow discharge/charging of a large capacitor. Even if not a perfect exponential it should give a smooth curve and the deviation from a local fit is a first indication for local linearity.

A funny side note: The 5 V regulator use is an ET7805 (ESTEK)- it looks like this regulator is surprising low noise, but rather poor TC. So its a nice test source for a slowly drifting voltage  .

Attached is a plot of the 5 V supply drifting. RMS noise is about 2 µV RMS for the difference to a straight line (about 0.01 to 25 Hz). This includes noise of the LM329 reference of the ADC circuit.

[iMo]

@Jaromir: While comparing recent posts w/ DIY designs the way you have done it - MCU+CPLD/FPGA - is the way..

I've been thinking on an MCU embedded into the FPGA (ie. my iCE40UP5k with embedded Forth+SDADC), but using a cheapo popular 32bitter - like the BPill's stm32f103, and a small CPLD/FPGA (where the bitstream could be stored in the MCU's memory) is something I would highly consider.

For example stm32f103 (or a clone) + iCE40LP384, the combo for <$4.

Except the low cost and much higher performance (than atmegaxx or msp430) the important point is the C and Verilog are easy to read and write (unlike the Forth or ASM) by a vast majority of DIY community.. And for the above combo there are open source dev tools available as well.

The analog part - I've been pretty curious about which solution from the recent DIY postings (Jaromir vs. Kleinstein) gives a better results at the lowest digits..

PS: I've thrown your verilog as-is into the IceCube2 and with iCE40LP384 32pin qfn $2 FPGA:

Code: [Select]

Final Design Statistics
    Number of LUTs      : 283
    Number of DFFs      : 151
    Number of DFFs packed to IO : 0
    Number of Carrys    : 66
    Number of RAMs      : 0
    Number of ROMs      : 0
    Number of IOs        : 11
    Number of GBIOs      : 1
    Number of GBs        : 3
    Number of WarmBoot  : 0
Device Utilization Summary
    LogicCells                  : 301/384
    PLBs                        : 48/48
    BRAMs                       : 0/0
    IOs and GBIOs               : 12/21
#####################################################################
                     Clock Summary
=====================================================================
Number of clocks: 1
Clock: adc_3|mclk | Frequency: 84.81 MHz | Target: 83.13 MHz
=====================================================================
The iCE40LP384 bitstream is 8kB large, and it fits as a C source into the 128kB stm32f103 memory easily, thus you do not need the hw bitstream flash memory. Moreover, you may reprogram the FPGA logic "on the fly" off the MCU. MCU+FPGA on the inguard pcb.
And as a bonus - you do not need an FPGA programmer hw (as you do not need a hw programmer for the stm32 provided you run an usb bootloader)

[jaromir]

Yes, my hardware could be optimized in many ways. I realize MSP430 isn't the most popular choice among hobbyists, after all, it isn't even the most popular choice of my own. I've chosen it just for higher fun factor (what was the point of the project).
Should I rework the kit for mass appeal, I'd probably end up with STM32, plus the ICE40 looks like sensible choice for programmable logic - I think we agree on this.

Also, your mention of inguard MCU along with PLD is really reasonable. During the design and development I had to make a few compromises because of not having a lot of "intelligence" in inguard part. Not much of power or fancy features needed, low power 8-bit MCU would be more than enough here.
I wonder if choosing low-end 8-bitter over slowly clocked ARM would make sense here, especially from EMC standpoint.

Thank you for recompiling the Verilog implementation. For EPM240 it takes a bit over 200 of 240 available logic cells. I didn't expect as much as 301 cells on ICE40.

[iMo]

@Jaromir - your design is great and I wish I could order a kit from you for 99Euro 

Instead of my regular afternoon nap I took your verilog and replaced the uart output with reading the 32bit result reg via spi (sclk, miso, ss). It builds with 50LUTs less (251). A simple flag is needed to tell mcu (ie rising edge interrupt) the result is valid, so add 1LUT.
PS: it took me 10minutes inclusive compile time - to demonstrate the flexibility of your verilog.

I think 20-50MHz crystal clocked stm32 together with a small fpga (ie the LP384) in the inguard can easily be used, the 8bitter is not cheaper, and you get a pretty higher flexibility and performance. And you get a decent 12bit ADC for measuring the residuals and 20kB of ram for some simple DSP or faster measurements. As you have seen the FLUKE 8588A is using a Blackfin on the inguard board as well

PS: and the stm32f103 is arduino compatible..

[Kleinstein]

...
The analog part - I've been pretty curious about which solution from the recent DIY postings (Jaromir vs. Kleinstein) gives a better results at the lowest digits..
...

Jaromir's design in the current form likely has a slight advantage with gain stability, but it has definitely higher noise. The comparison is a little difficult though because of the slightly different ranges (+-14 V versus +-11 V). For the linearity it is hard to tell, as the measurement is not that easy -  I see a slight problem with a variable current through the resistors that set the reference current. So it really needs the tight thermal coupling of the LT5400.

For the design, I would not care too much which languish is more common. The bigger hurdle is more like having the knowledge about the parts (µC or CPLD) and the required tools. It tends to be easier to go from C to ASM on an AVR than to change to something like STM32 in C. With FPGAs the ability to solder the case (especially BGA type) can also be a deal breaker for DIY.  My design can work with DIP only parts, even on a bread board - my first tests were with only the µC and UART on an Aruduino like board and the rest on a bread-board.

I agree that CPLD + µC could make things easier, but it needs 2 environments / development tools. So it is attractive to get away with just a CPLD or µC.

PS. A faster µC could help with faster conversion rates and possibly doing digital RMS. Even a 12 Bit ADC of good speed could give a reasonable solution for digital RMS  (e.g. comparable to the analog AD637 or like solution in many respects).

[iMo]

My current understanding of the problems around the Multislope Precision ADC DIY design and its feasibility is as follows:

1. the real know-how and expertise is in the analog part and in the processes of handling the analog part such you will get the best results

2. the digital part - inguard and outguard - is the simple part. Any modern cheapo 32bitter can do, any cheapo CPLD/FPGA can do, it does not matter. I would be happy to have an MCU with good built in ADC (ie with an external Vref).

The other stuff like display, buttons, power source, usb/232/wifi/ethernet is just a business as usual.

I worked with 8080 asm, Z80 asm, 8051 asm, 68k asm, atmel's asm, pic's asm, but the acceptance of an asm based firmware is pretty low today. Not talking manageability of such a source. People do not work with asm today.

With FPGA/Verilog you do not care on how what asm instruction work, and how many clocks it is long, and how many nops you have to insert to compensate a loop, or how to shift a 24bit word 7bits left, or how to set the portB pin3 and 6.

DIY hw community is C/C++ positive, with more and more emphasis towards programmable logic (because most the tools are free, easy to handle and the small chips are cheap). Verilog/VHDL - ok, that is something people discuss from time to time. Thus the languages are pretty clear.

I would be happy to have a chance to buy a 10x10cm large ADC inguard board, for say XXEuro, with 6.5+digits capability +/-20V input ADC on it, with >1G input impedance, with the 399 on it, with a 10pin connector for +/-25V +/-15V and +5V external floating power sources, a 4pin connector which communicates via opto-isolated UART with "something".

I can flash the board through a 3pin SWD connector (both MCU and FPGA) with a $2 dongle, where the FPGA and MCU there are "standard"  C/C++/Verilog supported things. In addition a small I2C flash for calibration params wired to the MCU would be handy on the board.

The FPGA/CPLD bitstream bianary could be put into a C const array easily, and flashed together with the FW into the MCU. Upon reset the MCU loads the FPGA and that's it.

You may have several bitstreams stored in the MCU's memory and you may reconfigure the entire FPGA on the fly within a few milliseconds.

With that $4 combo you may measure every even ADC sample with Jaromir's algorithm, and every odd ADC sample with Kleinstein's algorithm, 25 samples per second (provided the analog part supports such an switch ).

You may put a simple CLI in the MCU, and talk to the board via set of "commands".
That all is easy today. People play with it every day. People run FreeRtos with CLI on the $2 BluePill.

What is not easy is the analog part and the processes around it, imho..

[jaromir]

Jaromir's design in the current form likely has a slight advantage with gain stability, but it has definitely higher noise.

You are right with the noise. Your measurements indeed show lower noise than what I achieved. I tried to decrease the noise level, but it was fruitless.
At first I had OPA134 in integrator, changing it to OPA140 did bring just tiny bit of an improvement.
I thought that noise may be contributed by voltage approaching comparator switchover point too slow, so I tried to include slope amplifier after the integrator, in noninverting configuration with gain 10, but I didn't see much of a change. Opamp in amplifier was LT1115 because that was what I had on hand.
Perhaps you may point me to other possible sources of noise.

[Kleinstein]

It makes sense to look at the noise source. One way to look at noise is to separate the frequency ranges. It is mainly to ranges that really matter: one is the rather low frequency noise (e.g. some 10-100 Hz), that 'happens' during run-up. This is acting kind of as an error in the charge going into the integrator.

The other part is measuring the noise in the integrator, which is done during rundown or with the auxiliary ADC. This is more higher frequency noise (e.g. > 10 kHz up to maybe the MHz range with the comparator). There is not much noise from the intermediate frequency range, as this has to little BW to matter for the charge measuring and is averages out by the integrator to matter for the actual charge.
So it is mainly these 2 noise types:  low frequency for the run-up and high frequency for the rundown. These can be looked at quite separate. The shorter the integration time gets, the more important high frequency noise gets. Quite often (if no big mistake / weakness) at a few PLC and more the high frequency noise is not the main problem - this gets important for something like 5 ms integration and faster. A main way to fight the higher frequency noise is using a smaller integration cap and faster modulation. So for now I look at the low frequency part first:

With the common relatively high resistor values (e.g. 50 K or 100 K) to avoid self heating problems the resistors are a major noise source. The reference paths are essentially current sources, so high resistance here is good: so a higher reference voltage and larger resistors have some advantage, as it's a lower noise current source. So using some +-14 V for the references is already good compared to the often only 10-12 V in meters like the 34401 or 3458.

For the switches it is kind of natural to have the same resistance for the input and the reference paths, as it allows for some compensation. So this is my reference case. In this case the noise from the resistor at the input and the reference paths is the same size. So for the noise, one gets the noise, as if one would have twice the resistance as voltage noise source. If the resistors at the reference are chosen smaller (e.g. half) than the input side, the current noise goes up. At half the resistor values the noise referred back to the input is as if the resistor from the input goes up by the ratio. So the 200K in and 100K reference case already gives the noise of some 200 K + 400K = 600K. This is some 100 nV/sqrt(Hz) to start with. So to get really low noise, one may have to start with a smaller resistor at the input.

The twice higher resistor at the input also gives a noise gain of 3 to the voltage noise of the integrator. For the equal resistor case the noise gain is only at 2. Still with the OPA140 and a short integration (e.g. 1-5 PLC) the voltage noise is not that high. Going much slower will add 1/f noise of the OPs.
Another noise source is noise from the reference inverter this adds with a gain of 2 or 1 with the 2:1 or 1:1 resistor case.
Another, odd noise source is higher frequency (around the modulation frequency) noise from the reference, that is demodulated by the run-up modulation. This noise might contribute a little, but it should be easy to filter - at the very low noise level the RC filter at the LM399 makes some sense, even of only effecting > 1 kHz noise.

For the higher frequency noise, one may have to find a good balance of speed and noise bandwidth for the integrator. A faster integrator has more BW and thus more noise. So ideally one may have to accept that the last fine slope step is limited by the comparator / slope amplifier speed and may not give the full timing resolution. It can be difficult to find a good balance here (I avoid this problem by using the relatively low BW ADC). A fast comparator is not always better. A slope amplifier may have lower noise - though noise specs for comparators are rare, so hard to tell how good they are.  A smaller integrator cap and thus more run-up steps also help with the high frequency  noise. However the DG211 switches may not be suitable for really fast switching, as they have quite some charge injection. Also switching the voltage from 0 to Uref can additionally add some "charge" from parasitic capacitance - switching the unused references to ground has some advantages.  The switches also tend to produce quite some higher frequency glitches, that could lead to noise or linearity errors - though slow these can be a problem with the DG211. I had to really care about supply spikes / glitches - just massive decoupling at the chips was not working well. It was more like adding ferrites / resistors in the supply, at both the sensitive parts and the possible trouble sources.

The simple rundown with only one slow slope, that is not that slow likely has a limited resolution and thus some quantization noise. More resolution (e.g. smaller slow slope) could avoid the quantization noise. The ratio of 1:6 is more suitable for very fast conversions. It could well make sense to have a lower reference level like 1:16 or 1:30 - it still does not take that long.

From the experimental side one could check the higher frequency noise from very short conversions, like a run_up without feedback (e.g. some 10-100 µs). Here the higher frequency noise would be measurable on it's own - not much integrated low frequency noise at this speed. Another point is comparing 2 speeds of the modulation: this gives a hint if the extra noise is switching related or not. Switching related sources could be something like jitter or supply voltage noise, that effects the charge injection. Also some DNL problems may look like noise.

@jaromir: What are the integration times and modulation frequency during run-up ?

[jaromir]

Thank you much for detailed and valuable analysis. Your responses are goldmine of information.

In my case integration time is 20ms, with 200 runup cycles, ie. 100us per integration cycle.
DG211B is specified to have 1pC of charge injection by Visahy datasheet. I tried to select switches with charge injection as low as possible while withstanding +-15V on open switch.
I can try to experiment with both runup modulation speed as well as rundown speed. Slower rundown slope is not a major problem for me, as I'm not aiming at very fast acquisition, rather than slower and more precise measurement.
Also, I can easily try to filter the reference noise to some degree. There is even footprint for RC lowpass filter on the PCB, though the resistor is currently zero ohm link, but capacitor is fitted.
I guess the R17-C20 network in your design is added to cut down switching spikes from '4053. Is that correct? What kind of problem did the ADC exhibit without it?

Another thing I find intriguing is composite opamp in integrators of some ADCs, for example your design. This kind of composite circuit is not often used. What was your approach for selecting opamps (OPA1641/TLE2071) and resistor divider in between those?

[Kleinstein]

R17 and C20 are kind of part of the compensation of the composite integrator. There is little need for these if a single OP integrator is used. Without these two the input voltage to the integrator and output of the OPA1641 showed quite some ringing. This required the short (fixed) phases in the modulation to be longer.

The idea of the compound integrator is to keep the input voltage to the integrator close to zero. With just a single OP, there would be some rectangular form residual voltage somewhere in the mV range, due to the limited GBW of the OP. If the resistors for the reference paths are not perfectly matched this can give a contribution to nonlinearity - by it's own the voltage is not a real problem.
The second OP reduces the residual voltage to some peak that decays after some 0.2-1 µs, depending on the speed used. The divider between the OPs is needed to adjust the stability / compensation. The 5:1 ratio is about right for same speed OPs. The choice of TLE2071 and OPA1641 is in part to the parts available at the time. When starting I used only a single OP integrator with a TLE2071 - at that time I had ordered parts from TME.eu and the TLE2071 was one they had at a reasonable price. In the compound integrator (and especially in my case with the ADC) the noise of the "fast" OP is not that critical - it is mainly speed. In the classical form the OP's noise may be more critical, as the comparator also reacts to higher frequency noise.

The OPA1641 is not that different from the OPA140 - just cheaper and slightly higher bias and offset. My other option here is an OPA145, the slower brother of the OPA140. For the test chose the fast OPA1641 to get a little more signal at the test point at the OPs ouput.

The 2 OP integrator is used in the HP34401, 34411, Keithley 2000, 2010, 2182, 2001 (some versions) - so it is not that exotic. the Keithley 2002 and 3458 even use 3 OPs - today one should get away with 2 OPs as the OPA140 is fast and precise. Besides the residual input voltage, the lack of high precision JFET OPs could have been a reason for the compound integrator. So just a single OPA140 may not be such a bad solution, if the resistors are well matched. The compound integrator is more like a thing for lower INL - it may even add some noise in the classical form.

With the charge injection the DG211 in deed does look good. One has to be a little careful with the front page numbers, as the charge injection depends on the voltage level.  Another point is that the circuit impedance also effects the charge injection. In the circuit with just single switches the capacitance of the loose end of the resistors acts as an additional  charge pulse. This extra charge pulse could upset the integrator quite a bit. It also take some time to get back to a stable off state (e.g. some 10 pF *100 K) - this could give an effect with very short off phases.

The reference noise is more like a small contribution. AFAIK some 100 nV/Sqrt(Hz) for the LM399 at some 10 KHz. So not that much filtering needed to reduce the 10 kHz by something like a factor of 5. It's a small noise contribution but avoidable.

Initially I also used the 4 phase modulation (to variable phases) during run-up. However for some reason the 2 sides/ positions in the cycle were not exactly equal and this can lead to quite some INL error just in the center of the range. This is because there is a chance from  pos / neg / pos / neg to  neg / pos / neg /pos over a very small range with changing many times between the 2 sub-phases nearly at once.

A simple test for the effect of higher frequency noise would be just doubling the integrator capacitor. This cuts the voltage at the comparator  in halve and about doubles the effect of higher frequency noise. So one could see if the higher frequency noise is that relevant at 1 PLC.  It helps to know which type of noise to fight.
Besides reducing the integration cap (which needs faster modulation) one could also increase the integration to 2 PLC. This reduces the effect of higher frequency noise by a factor of 2, and at 2 PLC the 1/f noise of the OPA140 is still very low. With older classical MS ADCs the optimum may very well be at more than 1 PLC - possibly even 10 PLC.

[iMo]

Here is a simulation of the Kleinstein's DIY MS ADC, the analog part.
You may use different opamps (with some models the simulation speed is low).
Timing is just a simple runup toggling, different from original.

Update: re-indexed relevant parts

[chickenHeadKnob]

R17 and C20 are kind of part of the compensation of the composite integrator.

 I hope this isn't a stupid question. Did you mean R20 and C17 ?  Enjoying your commentary, some of the aspects are counter-intuitive to me.

[Kleinstein]

R17 and C20 are kind of part of the compensation of the composite integrator.

 I hope this isn't a stupid question. Did you mean R20 and C17 ?  Enjoying your commentary, some of the aspects are counter-intuitive to me.

Of cause it is R20 and C17.

For the OPs choice the second OP (with the capacitor in feedback) mainly needs to be fast. If at all higher frequency noise matters. The 1st OP in the compound integrator (with divider at the output) does not need to be so fast (though more than 1/5 the GBW of the other OP would be nice - faster OPs are effectively slowed down by the divider) and here low frequency noise and DC precision matters. Old Keithley meters used something like OPA177 (a little on the slow side) as a precision OP and AD711 for the fast part.

For the very fast switching spikes from the 4053 the HP34401 (and quite some other meters) and my ADC circuit use ferrite beads. I don't know exactly how they help, but they do improve the noise and settling of the integrator a little. The high speed of the HC4053 is a 2 sided thing: it keeps jitter low, but can also causes EMI issues from RF components not visible on the scope. However for the supply lines I more turned away from ferrites towards just resistors - they are just more predictable to me.

[iMo]

With ferrite beads (smd 75ohm). Found a MCP600x which works.

[splin]

I'm guessing you probably chose the LT1028A just for the purpose of the simulation, but for a real implementation the input current noise, 4.7pA @ 10Hz, is much too high for this application - the noise due to the current noise exceeds the voltage noise for source impedance > approx 200 ohms. And you have 2 of them so the current noise will be 1.4X

The 40nA input bias current will cause a fair bit of offset, but so long as it stays constant, autozeroing will take care of that.

The 34401A op amp choice is a bit surprising (to me at least). The OP27 was a goto precison amp at the time so probably a reasonable choice, apart from the relatively high current noise. But why use an AD711? Its slower (4MHz GBW) and much noisier (2uVpp 0.1 to 10Hz) compared to the OP27 (8MHz, 90nVpp). Its a JFET so the bias current and current noise are much lower than the OP27 but that is pretty much irrelevant given they are already using an OP27. So why not use another OP27 or a faster non-precision, low noise amp? The AD711's full power bandwidth is only 200kHz; it does have a much higher slew rate of 20V/us compared to 2.8V/us for the OP27, but even that should be enough for the 34401A with a max dVc/dt of around 1V/us.

Of course it works well enough so perhaps it was a cost question - except that as a precision JFET I doubt it would have been particularly cheap either.

[Kleinstein]

The OP choice in the 34401 surprises me too. The current noise of the OP27 can be a real problem at 10 PLC. The 2 nd OP may not need to be so low noise, but higher GBW would have definitely been an advantage. The µC internal  ADC used in the 34401 is not that fast, and thus does not react to the very high frequency noise.  At problem at the time could have well been that there where not many fast precision OPs.
The is another reason a don't like a BJT based OP at the integrator and thus prefer something like OPA140 and similar: the input can see small spike from switching that may exceed some 25 mV and at this point there can be additional input current for a BJT based input stage. At least one leaves the linear range.
The 34401 has another oddity with the resistors at the input, using an additional resistor to ground to effectively divide down the signal at the input.  The ASIC they build for it was probably the reason HP used it so much.



@IMO The MCP600x I use in my version before the µC internal ADC is not critical - its used with quite some delay. The MCP600x are just simple and common 5 V rail to rail OPs.  To speed up the simulation one can use the universal OP model from LTspice for non critical OPs.

[iMo]

Yes, the opamps in the above simulation are the "placeholders" only. With some opamps the simulation is slow or even not converging (ie OPA140).

Yes, it could be interesting to use the LTSpice "universal opamp" model and specify those several parameters it offers.

See below the LTspice model levels (from the LTspice library):

[iMo]

Could we somehow summarize what type of opapms are shortlisted for the specific ADC stages?

Input buffer:
---------------
1. OPA140
2. OPA145
3. OPA189

Integrator:
---------------
1. OPA140
2. OPA1641+TLE2071

Slope amplifier:
--------------------
1. NE5534

LM399 buffer/inverter:
--------------------------
1. OP07
2. AD8676
3. TL072

Comparator:
---------------
1. LT1116
2. LT1016
3. LM311

??