Author Topic: Multislope Design  (Read 25305 times)

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Offline new299

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Multislope Design
« on: December 17, 2017, 06:53:39 am »
Perhaps this should really be in the beginners section, if so, perhaps some kind mod would move it.

I'm interested in trying to design a basic multislope ADC. As a first pass, I'd like to understand if something like the attached design might work, or if there's anything I've woefully misunderstood.

The design would use a microcontroller to control a DG411 switch, this would switch in the positive/negative references. LT1013s are being used to buffer the reference, and as the integrator, comparator. Later the design could be expanded adding more slopes etc. At present, I'm just trying to understand if the basic architecture is sane.

Any comments are most welcome!
 

Offline Kleinstein

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Re: Multislope Design
« Reply #1 on: December 17, 2017, 10:24:10 am »
The inverter for the reference does not work this way - it should be obvious, unless this should really go the the beginners section.

The way the reference current is switched is not the best choice: the switched current is a rather dynamic load to the reference - this is especially a problem for the rather slow "buffers". When switched off, it takes a relatively long time to discharge the switch side of the resistor - thus short off times are not working well. There are other more suitable configurations, like having only one resistor for the positive and negative reference current and switch between those two.

The LT1013 is not working well as a comparator. Many µCs have a much better comparator inside.

The LT1013 OP might not be the best choice for the integrator: it has rather high noise and bias current and also is rather slow. So the ADC would not give a really low noise and work well only at low speed, with a relatively large integrating capacitor. The more normal choice for the integrator would be a JFET based OP, like TL071, LF411 or better (e.g. AD711).

Most simple integrating ADC use an additional switch to reset the ADC to a well defined start.  There are ways to do without it, but this is the more difficult way.
 
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Offline new299

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Re: Multislope Design
« Reply #2 on: December 17, 2017, 02:11:24 pm »
Many thanks for your suggestions. I've modified the schematic as attached.

I assume reset would be implemented as a switch across the integrating capacitor?

Using a single resistor for both positive and negative references would imply a dual-slope configuration? I was planning to use a multislope run-up configuration, but also try dual slope (layout the circuit so I can use a single resistor for both references too).

Are there alternatives/switches schemes I am missing?
 

Offline Kleinstein

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Re: Multislope Design
« Reply #3 on: December 17, 2017, 03:06:37 pm »
One would be limited to dual slop, if only one resistor is used for the signal and both signs of the reference level.  Using one resistor for both signs of the reference still allows applying the input signal and reference. Using just one resistor would be having both switches connected before the resistor. The only case no longer allowed is having both references active at the same time. To avoid this problem (e.g. during transients) one might add separate small series resistors.

The other common switching scheme is using a SPDT switch connected at the integrator side on the resistor. Here the reference current is either send to the integrator or to ground. As the switch only sees low voltage, one can use a simple 74HC4053 for this: one for the input and one each for the two polarities. This scheme has the advantage that the current drawn from the reference is constant. Also the power dissipation in the reference path resistors is constant.

The true dual slope conversion uses the same resistor for the signal and the reference. So this would need a different circuit. I have seen such a combination: here the signal and reference signal are added in the input amplifier by using a switched capacitor for the reference. So as a side effect they also don't need an extra negative reference.  So the signal applied is either just the input or input +/- reference.

For the reference part and maybe the input amplifier, it is still good to use the LT1013 OP. The AD711 is only a good choice for the integrator. So it usually takes different.
 
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Offline David Hess

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Re: Multislope Design
« Reply #4 on: December 17, 2017, 03:29:42 pm »
Use another analog switch before the input signal buffer so that the autozero cycle can remove its offset voltage as well.  This is how fully integrated slope converters were able to achieve microvolt accuracy using low precision CMOS processes.

Study old designs like the Fairchild 3814 and Siliconix LD120/LD121A and LD111A/LD110.  Siliconix used a run-up design which extends the range of the integrator for less non-linearity error due to dielectric absorption so it is potentially better than the more common ICL7104 implementations.  By fixing the number of switching cycles, charge injection errors may be calibrated out; HP did this in their high resolution meters like the HP 3456A through HP 3458A.

https://xdevs.com/doc/HP_Agilent_Keysight/journals/1989-04_HP3458A.pdf

The simplest design I would attempt is to combine the run-up of the Siliconix parts (HP called this Multislope Runup) with the charge injection cancellation of the HP designs.  If that did not yield 10 times better linearity than the 40,000 count ICL7104 design, then I would be disappointed.
 
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Offline CopperCone

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Re: Multislope Design
« Reply #5 on: December 17, 2017, 03:45:05 pm »
how does charge cancellation of these switches work? I thought it was dependent on the voltage the switch is facing. At least the LTC1043 datasheet lead me to believe this.

I am interested in lockin amplifiers. I think the optical optimos devices have basically no injection.
« Last Edit: December 17, 2017, 03:47:30 pm by CopperCone »
 

Offline David Hess

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Re: Multislope Design
« Reply #6 on: December 17, 2017, 03:53:47 pm »
how does charge cancellation of these switches work? I thought it was dependent on the voltage the switch is facing. At least the LTC1043 datasheet lead me to believe this.

I am interested in lockin amplifiers. I think the optical optimos devices have basically no injection.

This is different from minimizing the amount of charge.  Instead during the run-up cycle of the integrating converter, there are a constant number of switch cycles whether they are needed or not so the injected charge is constant and calibrated out during the zero calibration.  From the HP Journal that I linked:

An important requirement for any ADC is that it be linear. With the algorithm described above, multislope runup would not be linear. This is because each switch transition transfers an unpredictable amount of charge into the integrator during the rise and fall times. Fig. 6 shows two waveforms that should result in the same amount of charge transferred to the integrator, but because of the different number of switch transitions, do not.

This problem can be overcome if each switch is operated a constant number of times for each reading, regardless of the input signal. If this is done, the charge transferred during the transitions will result in an offset in all readings. Offsets can be easily removed by applying a zero input periodically and subtracting the result from all subsequent readings. The zero measurement must be repeated periodically because the rise and fall times of the switches drift with temperature and thus the offset will drift.

 
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Offline new299

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Re: Multislope Design
« Reply #7 on: December 18, 2017, 03:54:43 am »
Thanks David and Kleinstein for your helpful comments.

I've moved to using a single resistor for both references in the attached schematic. If I can get this design working, I'm wondering about modifying it to create a multi-slope run-down design. In this configuration, I could use the 74HC4053 to switch in the resistor on the integrator side, or switch to ground is that correct? Could I also use a DG419 here, though not strictly required?

I've also added in a autozero switch, using a DG419. I've reverted to the LT1013 for the reference buffers. Is there a better part to use for the input output buffers (I've currently left these as AD711s). I feel I don't have a strong grasp of the required specifications, and will try and read more about this.

Thanks again for your help.
 

Offline David Hess

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Re: Multislope Design
« Reply #8 on: December 18, 2017, 05:15:30 am »
Is there a better part to use for the input output buffers (I've currently left these as AD711s). I feel I don't have a strong grasp of the required specifications, and will try and read more about this.

The input buffer is usually a low input bias current part to present a high input impedance to the source but the AD711 covers that.  This is needed if a high input impedance attenuator is used and it also makes overload protection easier.

One thing I do not quite understand in these designs is that the common mode rejection of the input buffer should limit the linearity yet in the past, they got by with truly terrible integrated CMOS input buffers.  The implication is that the input buffer should be a precision JFET or CMOS part with high common mode rejection like the currently available LT1793/LT1055/LT1056/LT1122/LT1022 or if you are adventuresome, the much higher precision LT1012 low input bias current *bipolar* part.  The AD711 is not bad in this respect either.  I seem to recall doing the calculations and concluding that integrated chipsets were limited to less than 4-1/2 digits of accuracy because of this and it might explain why some old multimeters bypassed the built in integrated CMOS input buffer and replaced it with a part like the AD542.  Or maybe most of the error contributed by the common mode rejection shows up as gain error instead of non-linearity.

I am not sure why the output buffer would be needed.  The integrator has a pretty low output impedance and should not have a problem driving the comparator.  Maybe isolation is needed?

I would start off using a less expensive part in place of the AD711 or any of the others above like the TL051.
 
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Offline new299

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Re: Multislope Design
« Reply #9 on: December 18, 2017, 07:23:50 am »
Thanks again! I maybe getting ahead of myself, but... for this kind of layout is there any reason to prefer through-hole parts over SMD (ICs)? I’ve read in reference circuits people sometimes worry about SMD parts being under additional mechanical tress, and this introducing error somehow? (I’ve seen this mentioned with respect to reference circuits mostly).

A normal ground fill would be acceptable? Are there any particular points I should take into consideration?
 

Offline Kleinstein

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Re: Multislope Design
« Reply #10 on: December 18, 2017, 09:36:34 am »
It should be Ok to use SMD parts. With a MUX at the input to do an automatic zero adjustment, there are no parts that are really critical with respect to DC performance. For very high accuracy THT parts may have a slight advantage of less leakage and less stress sensitivity for the resistors, but this is if you go for more than 7 digits. One advantage with THT parts is the option to have sockets and change the OPs later on. So one can first test with TL071 and later upgrade to something like OPA140 if needed.  For a hand soldered board one can mix SMD and THT.

The integrator should be a good quality JFET OP. The AD711 is just one such OP, there are other's. I mentioned it because it is was used in some older DMMs. However there are other choices - likely better ones too. For a first test a TL071 or LF411 should also be OK. It helps to have a good BW and low noise both in the LF and MHz range.

For a precision circuit a ground fill is not a good idea. Usually the better way is having a dedicated ground star point. Also decoupling can be important, it should be made the right way. Another important point can be the choice of the integrating capacitor. It should be a low loss (DA) type, like PP film or a good quality NP0 ceramic.

For good linearity the TC of the resistor for the input signal is also important: self heating could otherwise cause nonlinearity. Also having a higher power rating can help.  It is less important with the reference resistor(s), as here the current is constant.

Especially if a slower rundown slope is also used, it helps to have another amplifier following the integrator. Not just a buffer, but an amplifier with well defined saturation to help the comparator.

I don't think the last circuit diagram was updated. For the switching there are mainly two options:
1) 1 reference resistor and switching between +ref,-ref and maybe GND
2) 2 separate reference resistors (+ref and -ref) and switching at the integrator side with something like DG419 / 4053.
One should use the same type of switching for both the input and the reference. It also helps to have the same or at least similar resistance.
 
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Offline new299

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Re: Multislope Design
« Reply #11 on: December 18, 2017, 12:55:10 pm »
I don't think the last circuit diagram was updated. For the switching there are mainly two options:
1) 1 reference resistor and switching between +ref,-ref and maybe GND
2) 2 separate reference resistors (+ref and -ref) and switching at the integrator side with something like DG419 / 4053.
One should use the same type of switching for both the input and the reference. It also helps to have the same or at least similar resistance.

Thanks again, regarding the above. Does the attached schematic now correctly reflect option 1? Regarding "maybe GND", what would the purpose of grounding the reference resistor be. Would this be for use when reseting the integrator?

Thank you also for your layout suggestions. As suggested, it sounds like a good idea to use through-hole parts so I have the option of using socketed opamps and experimenting.

Regarding the output amplifier, I'm wondering what to do here. In particular I've been wondering if it might be interesting to try implementing the control logic with an FPGA at some point (or is this just wasted effort?). If I want to leave the FPGA option open, might having an onboard comparator simplify things? Otherwise I will likely use an AVR for the initial design, and assume its comparator is suitable.
 

Offline Kleinstein

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Re: Multislope Design
« Reply #12 on: December 18, 2017, 01:22:21 pm »
Grounding the reference current not used would keep the current through the resistor constant. Otherwise one would get a modulation in temperature too. In addition there is parasitic capacitance that would also change charge. Usually the break before make time of the switch (e.g. 4053) is so short that the integrator / GND side of the resistors would not change voltage very much due to the parasitic capacitance.

It is a good idea to have a similar switch also in series with the resistor used for the signal current. So there should be an additional DG419 after the input buffer. The switch resistance usually has a high TC, but if balanced for signal and reference this would no have that much of an effect.

One can implement the control logic in an AVR µC However for getting exact, prdictable timing it might need ASM programming , but this is possible. The only really time critical part would be the rundown phase, to stop the coarse rundown.
Unless you need a very fast converter, there is little advantage of using an FPGA instead - it's just more expensive and difficult to program.
Using the µC internal comparator just makes the HW simpler, an external LM311 would be about as good, likely even lower noise. However with an extra amplifier stage comparator noise does not matter much. With the AVR one could even use the µC internal ADC for an additional fine step for the residual charge after rundown.
 
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Offline David Hess

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Re: Multislope Design
« Reply #13 on: December 18, 2017, 02:57:09 pm »
I would use sockets for the operational amplifiers just so that I could start out with cheap TL051s until everything works and then change them to the much more expensive precision types.  It would be interesting to see how the accuracy is affected by different operational amplifiers.
 
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Offline new299

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Re: Multislope Design
« Reply #14 on: December 18, 2017, 04:33:56 pm »
Grounding the reference current not used would keep the current through the resistor constant. Otherwise one would get a modulation in temperature too. In addition there is parasitic capacitance that would also change charge. Usually the break before make time of the switch (e.g. 4053) is so short that the integrator / GND side of the resistors would not change voltage very much due to the parasitic capacitance.

It is a good idea to have a similar switch also in series with the resistor used for the signal current. So there should be an additional DG419 after the input buffer. The switch resistance usually has a high TC, but if balanced for signal and reference this would no have that much of an effect.

Thanks. If I've understood correctly the configuration I currently have is a multi-slope run up converter [1]? With a shared resistor for the positive and negative references. In this configuration, this resistor will therefore always have the same current flowing through it, is that correct? However if I were to move to a multi-slope run-down configuration [2], it would be valuable to switch the resistors to ground when not in use, to ensure that they are kept at the same temperature.

The purpose of the additional switch on the input signal is also for use in the multi-slope rundown configuration, and is used when removing the input signal current at the start of the run-down phase.

Perhaps the next stage is to modify the schematic so it represents a full multislope rundown configuration.

[1] https://upload.wikimedia.org/wikipedia/en/thumb/3/30/Multislope_runup.svg/500px-Multislope_runup.svg.png
[2] https://upload.wikimedia.org/wikipedia/en/thumb/f/f3/Multislope_rundown.svg/510px-Multislope_rundown.svg.png
 

Offline Kleinstein

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Re: Multislope Design
« Reply #15 on: December 18, 2017, 05:32:39 pm »
The question of mulit-slope run-up is more a question of the software / control: it needs (there is a way around that too) separate resistors for the input and reference, so that input and reference can be active at the same time. Using some feedback already during the integration of the input signal is usually the more important improvement over the dual slope mode.

For a multi-slope rundown it can help to have the configuration with switches at the integrator, as the resistors can keep there constant current, when not active to the integrator. This also helps to avoid a highly dynamic load to the reference amplifiers.
Unless the rundown needs to be super fast there is not that much need to use many slower slopes for the rundown. Especially when done with the µC to control, there will be some delay on switching and thus only 1 slower slope is likely enough. A suitable offset to the comparator could compensate the delay. The slower slope also needs extra adjustment measurements - so having more makes thinks rather complicated at a rather small gain in speed. To get the slower rundown reference one could in theory use both the positive and negative reference together, if they are intentionally slightly (e.g. 2-10%) different.

The pictures from Wikipedia are still only the very basic concept, so they don't care about the details of how the switches are made.

The switch for the signal current is needed for the rundown phase, so that integration of the input stops. The other purpose of the switch is usually compensation of the switch resistance. As the switch resistance is rather temperature dependent, it really helps. to have the same type of switch for both the signal and reference currents. It also helps to have the same resistance for signal and reference currents, so that the contribution of the switch will be the same.
 
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Offline new299

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Re: Multislope Design
« Reply #16 on: December 19, 2017, 12:25:33 pm »
Thanks again!

In the attached schematic (multislope_r5), I've modified the configuration to match that shown in the 3458a document previously linked.

Practically, I might just want to use a single large resistor in the same configuration as +/-S1024 if I've understood your suggestion correctly? (as multislope_r5a).

In the path from the input signal, I have one switch. In the reference paths two. Should I have the same number of switches in the reference and signal paths?
 

Offline Kleinstein

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Re: Multislope Design
« Reply #17 on: December 19, 2017, 02:09:13 pm »
It helps to have the same number of switches for the reference and the signal path. It would help to have a second switch for the signal two, even if this is just for compensation. It could be used to switching between the input and maybe 0.  The scheme as drawn with 2 switches is unusual, but still possible and it has some advantage too. The simple (and common, e.g. 34401, 3458, K2000,K2002)  solution is to use separate resistors for the + and - reference. It adds the need for two matched resistors, but there is a pair of resistors to make -ref anyway. So there is not that much added possible temperature drift. It helps if the switches are well matched.

The slower slope reference currents can use more switches as the resistance is higher anyway and they are used only for a small fraction.  So this could be just one large resistor and than switching the voltage if needed (e.g. full and - 1/8 of the reference).  The 3458 uses this scheme, even with just a 74HC14 as a switch (R2R like DAC ?). Due to the higher resistance self heating is not that important and the requited stability is also much lower.
 
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Offline new299

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Re: Multislope Design
« Reply #18 on: December 21, 2017, 01:36:16 am »
Thanks, I have made changes based on your suggestions.

I'm trying to understand which resistors are critical now.

If I've understood correctly, in the 3458a all the slope resistors (and the input resistor?) are part of the same network (which is part of U180?). This means the TCR tracking of all these resistors is good? [1].

Obviously, I don't have the option of having all resistors in the same network. However it might be possible to try having some of the resistors in the same network. It seems useful for example to have the input resistor and the largest slope resistor as part of the same network (well essentially on the same substrate/in same package?). Same would go for the negative reference resistors perhaps?

The output amplifier seems less critical.

Regarding what kind of resistor, I was thinking of doing the layout such that I could optionally try using foil resistors. Do you think this could help, or is it likely that the TCR of other parts of the circuit would make this pointless. There seem to be some nice networks containing 2 47K foil resistors which I could potentially use for the input/largest slope resistors [2].

I'd be interested in hearing thoughts on this, and if I've seriously misunderstood anything.

[1] Vishay Advantages of Precision Resistance Networks for Use in Sensitive Applications Technical Note: http://www.vishaypg.com/docs/63512/VFR_TN109.pdf
[2] https://www.ebay.com/itm/1x-300198-47K-4K7-4K7-47K-High-Precision-Custom-Networks-2-3-or-4-Resistors/121930640926
 

Offline Kleinstein

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Re: Multislope Design
« Reply #19 on: December 21, 2017, 09:56:52 am »
The multi-slope converter does not have that many critical resistors.  To keep it relatively simple I would definitely not use that many different slopes for the rundown as the 3458 does. The many steps are mainly for high speed - if you have enough time (e.g. another 50-100 µs) one slower slope should be all it takes. This is how the Keithley 2002 does it. Having only one fine slopes means there is only one resistor ratio to adjust or with a modern design to measure. The extra steps used in the 3458 allow for a faster conversion, but it is not helping with accuracy - more to the opposite.

Drift in the resistors has 3 effects:
1) a shift in the offset. This is not that critical, as one will most likely have a kind of auto-zero measurement anyway. Thus alternate signal and zero. There are other source of an DC offset (OPs, input amplifier) and 1/f noise is also reduced by the alternating measurements.  So this kind of drift is easy to compensate for.

2) Drift can also cause the gain of the ADC to change. For long term, there usually is a direct path from the input to the raw (e.g. 7 V) reference to adjust the gain. This takes some time and adds noise and thus is usually not done that often. So compensation is possible, but good stability is an advantage.

3) If the ratio of the fine a coarse slope changes, this effects the linearity. Old meters like the 3456 used very stable ratios, adjusted to the exact numbers wanted to simplify math. Not sure about the ratios in the 3458 - they might be fixed and critical, but a self calibration of those rations is also possible, so that ratio drift can be compensated for. Especially with just one slow slope a periodic adjustment is possible, at least to get rid of long term drift. However this adjustment will take some time, though the adjustment for just a single fine slope might not be so bad.

The resistors at the reference amplifier (e.g. +-10 V) part will effect the gain and especially the zero drift. The gain usually scales a little slower than linear with the resistors. Depending on the circuit it takes 3 or 4 resistors.

If 2 separate resistors (as with switching at the integrator) are used for the + and - reference path, these two resistors also effect the zero drift, just like the inverter. So good TCR matching (like R1*R2 = R3*R4) of these 4 resistors might help.  In a set of 4 one could try swapping two to get the better matching. The resistors also effects the gain. In theory the LT5400 network might be an option - but hard to solder and limited values. Also capacitive coupling might not be that much desirable.

If a single resistor and thus switching at the +-ref voltage side is used, the resistor is mainly for the gain and TCR matching to the input resistor would be good. The fine slope resistor (if a separate one is used) has only minor effect - more like effecting DNL, and not very much.
 
The resistor for the input path effects the gain. In addition this resistor can have an effect on INL due to self heating. So here a low TC / low voltage coefficient is also a good idea, not just TCR tracking.

The switches are in series to the resistors and thus there is a limited use in using extremely good resistors, if the switches are not coupled as well. AFAIK the switch resistance has an TCR of about 6000 ppm/K so with 100K in series to a 100 Ohms switch, there will be an effective TCR of about 6 ppm/K, though with reasonably good matching. However tracking of the switches will be less accurate if one is at +ref and one at -ref in the one ref resistor scheme.

There is no need to have the negative and positive ref at exactly the same magnitude. So there is no need for accurate value matching. In the scheme of switching at the integrator slightly (e.g. 5%) different voltages could even be an advantage, as they would also make up a fine slope (using both refs together). I would consider this a rather clever idea, as it comes at essentially no cost and there is no problem with having a higher impedance switch for the fine slope. At first using + and - reference together to get the small difference sounds like a bad idea, but this is only used for a very short time (e.g. 10 µs) and thus has little effect and the two sources are used anyway alternating, so the difference already matters.

For the 3458 the input and coarse slope resistors are part of the same network. Not sure about the very fine ones, but these are not critical and done with a reduced voltage anyway. The same network also contains the resistors for the reference scaling to go from 7 V to a +-12 V.
The TCR tracking will be very good. It also provides a large substrate for the input resistor to get low self heating to effect INL.

As one can relatively easy do adjustment measurements for the drift, I don't think one will need such super stable resistors for the first test. One could still get stable readings, if one uses not just a zero adjustment, but also a gain adjustment more often. It would just reduce the speed to maybe half.  With same value / same batch resistors, there is still a chance to get reasonable matching, even if not on the same substrate.

Due to the higher demand on the input resistor, one might use a better one here, even if this means not having matching to the reference resistor(s).  Having the option to change to a different form factor can be a good idea. My guess is the first board could start with something like 15 or 25 ppm/K (e.g. thin film) resistors - there are still chances the first layout might not work that well.  The first version is likely also much about getting the software right and finding those nasty points that don't work as supposed.

For me the really unknown is the stability of the charge injection of the switches and also jitter caused by the switches. So hard to tell how suitable the DG419 or 74HC5043 are.

The amplifier behind the integrator is not that critical - so no special resistors needed there.

Another point to look at can be the integrator itself. Most better DMMs use a kind of compound amplifier made from 2 OPs for the integrator. This can help to have a more ideal behavior. However it can also be tricky to get stable without too much ringing. I think that today there should be better OP available as for the old days DMMs where we have schematics from. Some of the choices found in the old plans look odd from todays perspective.  Chances are there are better alternatives today.
 
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Offline new299

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Re: Multislope Design
« Reply #20 on: December 29, 2017, 08:37:34 am »
Thanks again for your detailed observations. I will work with thin film resistors at first, but try and do the layout such that I can try foil resistors/networks are the suggested points later if everything comes up correctly.

Based on your note regarding using multiple opamps in the integrator, I've been reviewing the Keithley 2000,2001 and 2002 schematics. As far as I can tell these all use off the shelf parts, and the design should be instructive. I've attached copies of the integrator sections of various (reverse engineered) schematics I've found online (thanks to TiN and others).

Based on the schematics, I've made note of the opamps used below. However, I don't fully understand how they are being combined, and what benefit this provides. Is there any good reference on this?

In the Keithley 2000, there's a OPA177 which provides some kind of offset, to the second opamp which is a AD711. But I'm not clear as to why. Any pointers you can give me would be most welcome.

Below are my notes on which parts are being used in the integrators, as I understand it:

Keithley 2000
Integrator opamps: OPA177GS AD711JR
Gain opamp: NE5534D
Integrator cap: 222...
Switches: VN0605T SD5400

Keithley 2001
Integrator opamps: OPA177GS OPA602AP
Gain opamp: NE5534D
Integrator cap: 10nF Polypropylene 10%
Switches: ??

Keithley 2002
Integrator opamps: OP177G AD711JR AD744JR
Gain opamp: ?
Integrator cap: 100nF? 2.2nF np0?
Switches: SD5400C
« Last Edit: December 29, 2017, 08:39:07 am by new299 »
 

Offline Kleinstein

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Re: Multislope Design
« Reply #21 on: December 29, 2017, 11:59:27 am »
I also though about building an integrating ADC and thus had looked at some points before.
In my understanding, using 2 OPs for the integrator serves 2 purposes:

For sufficient BW without excessive input bias and current noise one essentially needs a FET based amplifier for the Integrator. However the DC 7 low frequency specs of those OPs are usually not that good. The 2 OP circuit can kind of split the low frequency and high frequency part. With something like the OP177 for the low frequency / DC part and an AD711 for the fast part.

The 2nd effect of the 2nd OP is  that the input voltage is low even if a small capacitor is used. Otherwise one has a input voltage of about 1/ GBW / C_int. In a first approximation this isn't even that bad, as it is still linear, but GBW is not that stable and there can be second order effects. To reduce the input voltage it is a good idea to have the low frequency OP to be reasonably fast too. However for stability reasons the additional OP for the DC offset  should not be faster than the 1st. OP.  From the frequency response, I like the combination used by HP in the 34401: an AD711 as the fast part and an OP27 with a divider at the output for the "slow" part. The divider effectively reduces the GBW of the OP and in addition reduces the higher frequency noise contribution - though it won't be a big deal with the OP27, but it can be worth it for the OP177 or similar. However the OP27 has too much input current noise to be considered a good choice.

My personal favorite would be a combination with two OPA141 or similar OPs. These modern JFET OPs are in the higher frequency part better than the AD711.  The low frequency noise is surprisingly good - not much higher voltage noise than the OPA177 and essentially no current noise. A lower cost alternative would be an OPA134. There is a higher DC drift, but for good DC precision one would use a kind of AZ mode anyway.  A divider at the output of the additional OP (e.g. 1:10) should set a reasonable speed ratio with two equal OPs to get a stable and fast response.

The extra Gain stage before the comparator seems to be OK with the NE5534 used in many versions: It's low noise, fast and low cost.

Anyway the OP's usually use the same pinout. So one can change this later if needed.
 

Offline saturnin

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Re: Multislope Design
« Reply #22 on: December 29, 2017, 06:23:05 pm »
I replaced OP177 with ADA4077-1 (0.25 ?V p-p noise, lower input bias current) in my KEI2010. It helped to reduce the ADC noise. Reading Kleinstein's post I am now curious whether OPA140 (or cheaper OPA141) would be even better choice. It also has 0.25uV p-p noise, but lower bias current and its noise.

I am looking for better solution instead of AD744 too (used as the integrator). I am thinking about ADA4627-1. It has three times less p-p noise (typ.) than AD744. If the integrator can't benefit from high slew rate of ADA4627-1 then again OPA140 may be a better option.

This brings me to DMM7510. Why? I think it uses a very similar configuration as Kleinstein suggested, i.e. 2xOPA140 (see attached picture).

 
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Offline Kleinstein

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Re: Multislope Design
« Reply #23 on: December 29, 2017, 08:20:54 pm »
The ADA4077 looks really good from the datasheet. In most aspects a step forward from the OP177/OPA177.  The 2nd OP in the integrator is mainly important for the low frequency noise. I would expect especially the 1 Hz-25 Hz range to be important - lower frequencies are likely handled by the AZ mode and input switching anyway. With BJT based OPs the current noise is especially a problem, as the 1/f cross over for the current noise is usually relatively high - thus the noise matching impedance (voltage noise / current noise) gets lower at low frequencies. So a 0.2-0.3 pA /Sqrt(Hz) at 10 Hz is really good for the ADA4077 (compared to about 1 pA/Sqrt(Hz) for the OP177). Changing the OP to a faster type might also cause trouble, as too fast an OP here could make the compound integrator unstable. When comparing the voltage and current noise, the usual circuit should have an effective source impedance of the signal and 1 reference resistor in parallel. So with something like 50 K each a 0.2 pA noise would correspond to about 5 nV and thus less than the voltage noise. So I would not expect a big difference with the OPA140.

For the integrator OP, the important noise should be higher frequency noise, like the 1 MHz range. Low frequency errors would be compensated by the 2nd OP. A higher speed is only of limited use. As the OP is operated in it's linear range only, the slew rate parameter is usually not important, it is more like the GBW that matters.  Even with a small integrator cap, the slew rate would normally be still rather low, more like in the 1V/µs range. The advantage of a faster OP at the integrator would be faster settling and thus the possibility to use a faster modulation scheme and thus a smaller capacitor. This could be an advantage if high resolution is wanted at high speed. However a higher GBW would not help much if the modulation and cap stay the same. Keep in mind that the AD744 uses external compensation - this might be different from unity gain compensation. So it is hard to tell how fast the AD744 is actually in that circuit.

Both OPA141 and ADA4627 would give a significant improvement in higher frequency noise over an AD744.
For the higher frequency noise it is the combination of the integrator and the following gain stage (slope amplifier) that matters. The often used NE5534 is still not that bad and changing that OP might influence the timing.  A lower noise might help with the noise, if limited by the rundown phase.  However the resolution might be limited by the timing resolution or similar. So the advantage of a lower noise OP in an existing circuit might be limited. The effect would be most visible at short integration times (e.g. 1 ms).

Interesting note on the DMM7510. I already was quite sure the ADC is not under the second box - that is most likely the input amplifier.
 
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Offline saturnin

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Re: Multislope Design
« Reply #24 on: December 30, 2017, 12:30:36 am »
@Kleinstein, thank you for your inputs. 

I will probably stay with ADA4077 as further improvement wouldn't be that big to justify risk of damaging the PCB during repeated desoldering.

I am still tempted to replace AD744 though. I need to perform new search since I overrated significance of slew rate parameter as you confirmed. Maybe ADA4625 would be even better than ADA4627...

As concerns the slope amplifier (NE5534), I tried to replace it with LT1037, but it was little bit worse then, so I put NE5534 back.

I agree it is probably the input amplifier instead of the ADC under the grey shield in DMM7510. The same approach is used in KEI2182 and KEI2010 (where the input buffer and MUX are shielded too).
 


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