Author Topic: Multislope Design  (Read 85601 times)

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Offline iMo

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Re: Multislope Design
« Reply #100 on: January 13, 2019, 02:04:38 pm »
It's only a small detail and may not effect the simulation: the switch for the input signal should be wired like the reference channels.
Ok, thanks, fixed. Same results.

Code: [Select]
Vinput[V]         VrefP     Vresidual[mV]
-----------------------------------------
 14               60        -84.724598 
 10.001           100      -111.18542         
 10               100       -65.6633
 9.999            100       -20.195641
 5                150       -41.385211        5VDC+2Vpp_500Hz
 5                150       -41.934181
 1                190       -22.446172
 0.1              199       -18.161997
 0.01             200      -457.83404
 0.001            200       -49.337398
 0                200       -1.#INDV          (-580.12284µV closest)
-0.001            200        28.80118
-0.01             200       437.25276
-0.1              201        -2.7407967       << simul slow down
-1                210         2.2517985
-5                250        22.25494
-5                250        22.35401         5VDC+2Vpp_500Hz
-9.999            300         2.6997826
-10               300        48.327059
-10.001           300        93.820557
-14               340        69.571078
Values taken from the plot.
VrefP + VrefN = 400
« Last Edit: January 13, 2019, 07:19:28 pm by imo »
 

Offline iMo

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Re: Multislope Design
« Reply #101 on: January 13, 2019, 07:31:53 pm »
@Jaromir: While reading the metrology section it seems to me even the vacuum filled caps are crap when used in the integrating ADC. Did you try with different types/materials in your prototype design?
 

Online Kleinstein

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Re: Multislope Design
« Reply #102 on: January 13, 2019, 08:22:16 pm »
A good point of the multi-slope run-up it that it reduces the effect of the capacitor quality.  The usual candidates for good caps are PP (polypropylene), PS caps and NP0/C0G ceramic.  With sufficient fast modulation during the run-up, these caps should be well good enough.  There is a thread about the ADCMT6581 DMM. Even for 8.5 digits it gets away with a PP capacitor and only some 5 kHz of modulation and thus a 20 nF integration cap. I would consider this about the limit where you have to start worry about DA.

In my test setup I also tried polyester caps: it still kind of worked with some limitations. The effect of dielectric absorption gets clearly visible on the scope as quite some drift after the run-down. However the tolerance in my case could be in part due to the special way of operation, that is more tolerant to DA than the normal run-down. This was for test purpose to get an idea how the DA caused error would look like.

So I see no real need to look for better caps. In the   < 20 nF range all 3 types of good capacitors are readily available.

DA would be a problem only if very slow modulation (e.g. < 5 kHz) is aimed for. Even than there would be the option to use an accurate feedback algorithm to keep the average voltage about constant. This should suppress much of the DA effect (at least the slow part). Anyway a large integration cap has a disadvantage when it comes to noise and is thus not that attractive.
 

Offline jaromir

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Re: Multislope Design
« Reply #103 on: January 13, 2019, 11:39:54 pm »
I was curious about DA, so I made simple DA checker, or perhaps more DA experimenting tool.
It consists of two low leakage JFET switches, amplifier with low leakage opamp, plus MCU to switch the JFETs on and off; in order to charge the capacitor to 10V, then briefly discharge it to zero and then leave floating. Opamp amplifier allows observing the capacitor voltage during all phases, especially at the floating one. I abused MAX232 as JFET gate driver.
Attached are pictures of my setup, along with two measurement scope screenshots - one is grey PP capacitor, another one is soviet teflon type. Yellow trace is voltage on capacitor, blue trace is the same, with 10x amplification (plus notice different vertical scale). The voltage rise after discharge is effect of DA, very obvious on PP type, not much significant on PTFE type.

The differences are quite obvious; I tried a few more capacitors, the best were (in this order) teflon, polyester, polypropylene, polyphenylene-sulphide, NP0 ceramic. Worst were electrolytic, high capacitance ceramic were not much better.
Also, I tried different capacitors in my ADC setup. Capacitors with worse DA appeared to provide worse INL; but I have to recheck this again after I finish second version of my ADC.
 
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Offline orin

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Re: Multislope Design
« Reply #104 on: January 14, 2019, 12:35:53 am »
 

Offline new299Topic starter

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Re: Multislope Design
« Reply #105 on: January 14, 2019, 07:39:59 am »
Hi all,

In order to improve my understanding I've been reading over the Keithley 2002 ADC schematics (originally from TiN). I've written up my notes here:

http://41j.com/blog/2019/01/notes-on-the-keithley-2002-adc

Most grateful for any further insights, or corrections. From what I can tell the 2002 uses current sources of ~+/- 450uA derived from the 7V reference. These are switched through the SD5400 into the integrator. This appears to be a dual slope ADC (rather than multislope).

The SD5400 in the 2002 seems to be driven by TTL input (5V). This limits it's range somewhat, but I guess this doesn't matter with 450uA and what I assume presents as a relatively low impedance load?
 

Online Kleinstein

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Re: Multislope Design
« Reply #106 on: January 14, 2019, 11:58:24 am »
The Keithley 2002 uses current source, but it still it a multi-slope ADC. The current sources instead of simple resistors are just an attempt to reduce errors from not so ideal switches and the integrator input voltage. The second advantage is that the the switch resistance has little to no effect.

In addition to the 450 µA current sources there is another smaller current source of some 5 µA. It is always active, but can still be used as a single slower slope  for the rundown and only adds a small offset for the rest of the time. In this respect the ADC is rather similar to the K2000, that also uses a single fixed current.
So the ADC is multislope, though only with a single rather slow slope. So it is not that fast.

The switches are at the integrator input and thus only see a small voltage, e.g. from non ideal transient behavior of the integrator.
As the on Resistance does not matter with current sources, there is no need to use a higher gate voltage.
 
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Offline new299Topic starter

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Re: Multislope Design
« Reply #107 on: January 14, 2019, 02:25:31 pm »
In addition to the 450 µA current sources there is another smaller current source of some 5 µA. It is always active, but can still be used as a single slower slope  for the rundown and only adds a small offset for the rest of the time.

Thank you for the clarification! I guess this is U815/Q807 I hadn't previously understood the purpose of this. Makes a lot more sense to me now!
 

Offline jaromir

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Re: Multislope Design
« Reply #108 on: April 30, 2019, 09:09:45 am »
Follow-up to my post from january 13th:
I made some more progress - respin the ADC PCBs, designed input amplifier (for now just follower/signal buffer, with autozero capability), digital board with MSP430 MCU, display/keyboard with MC9S08 MCU*, power supply with a few floating rails to achieve full isolation between "earthed" logic portion**  and floating ADC/input amp. Floating part is enclosed in separate metal box.
It is designed as six and half digit DVM, though it displays seven and half digits just to see how stable it is. I'll truncate it to six and half digits later.
The wiring is still quite messy, it's work in progress. I need to perform proper calibration and characterization.

* I deliberately chose MSP430 and MC9S08, because I never made any real projects with those. It was fun to discover peculiarities of those.
** There is  USB and RS232 connection options, plus bluetooth module - it is not used by now, not sure if it was good idea, after all.
« Last Edit: April 30, 2019, 09:12:44 am by jaromir »
 
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Offline iMo

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Re: Multislope Design
« Reply #109 on: April 30, 2019, 10:48:14 am »
What is that metal can in the input amp?
Isn't cutting off last few digits a difficult task? :)
« Last Edit: April 30, 2019, 11:11:56 am by imo »
 

Offline jaromir

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Re: Multislope Design
« Reply #110 on: April 30, 2019, 11:46:48 am »
The metal can part is just 78M05 to generate local 5V for VL pin of CMOS switch.
Normal 78L05 or million of other ways of creating 5V bias would do the job too, but I have a lot of 78M05 in TO39.

Cutting of last digit can be done in may ways. In case software solution isn't available or desirable, strategically placed piece of duct tape will do the job just fine.
 
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Offline iMo

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Re: Multislope Design
« Reply #111 on: April 30, 2019, 05:08:26 pm »
Ah, Metrology grade 78M05   :P
I've been using the duct tape too, currently covered last 5 digits on my DMM..
 

Online Kleinstein

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Re: Multislope Design
« Reply #112 on: May 17, 2019, 04:11:49 pm »
I finally got a board made for the ADC already shown in response #48 (breadboard version).  The circuit has not changes that much - slightly different OPs are used (not all better) and an oscillator instead of just a crystal. So the hardware is a little similar to the 34401, with HC4053 switches, the normal 2 OP integrator and using the µC internal ADC for the residual charge instead of a reset. The main differences to the 34401 are that I added a rundown phase, the µC internal ADC is used with the integrator in hold mode and the references are a little asymmetric. The control is via the µC and thus no ASIC (2 OPs instead).

The board also includes a MUX and buffer (place on the board, but currently still external with 4 wires going there) for the input to get zero and reference readings to compensate for zero-point and gain drift.

The board is a slightly odd mixture of THT and SMD parts, and some optional / alternative parts not used.
Some of the bodged in parts  (the high value resistors and the large yellow cap) at the bottom are for measuring the average integrator voltage to check for DA contributions to INL - so not part of the normal ADC.  With suitable caps there is not much DA effect visible. At least for this circuit I see no need very very special caps: just PS or the NP0 caps I tested were well good enough.

The software is working so far (for most parts). For some reason the PCB version is still a little more noisy than the bread board version was. This could be in part due to a not that optimal OP (TLE2021) that sets the integrator noise, but I suspect some switching related noise too.
Due to a changed software most of the earlier linearity problems are gone.
 
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Offline iMo

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Re: Multislope Design
« Reply #113 on: May 18, 2019, 02:00:58 pm »
@ Jaromir and Kleinstein: Hopefully you will soon share your experience, results and designs such we may help with improvements.
"6 digits ADC for everyone" could be an interesting and feasible project  :)
 

Online Kleinstein

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Re: Multislope Design
« Reply #114 on: May 18, 2019, 02:15:15 pm »
I will share the design soon.

Currently I still have a few minor problems (trouble with the UART, noise that is 2-3 times higher than it should be and some dependence on the load to the 5 V). Currently the noise is at about 1.5 µV RMS for the auto zero measurement - so already not that bad.
 
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Online Kleinstein

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Re: Multislope Design
« Reply #115 on: May 19, 2019, 02:00:44 pm »
I found out that not all HC4053 behave the same. The 74HC4053 (2 samples) from ST I initially used caused higher noise than CD74HC4053 from TI and an old HEF4053.  Nominally specs are very close for the HC4053 parts - so it may need some testing there. My guess is things like the break before make time or charge injection could be different. However I am not sure other batches will behave similar.

With the CD74HC4053 the noise is now down to a little below 1 µV RMS.
 

Offline branadic

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Re: Multislope Design
« Reply #116 on: May 19, 2019, 03:07:50 pm »
Have you tested MAX4053 for comparison?

-branadic-
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Online Kleinstein

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Re: Multislope Design
« Reply #117 on: May 19, 2019, 04:09:14 pm »
I have so far only tested 74HC4053 (2 units) from ST, CD74HC4053 from Ti (1x, the one I used ) and HEF4053 from Phillips. I will probably also order an max4053 and 74LVC4053. However I am not sure which parameter is really important. The main advantage of the max4053 is the better leakage specs - however leakage likely is not an important parameter. The lower speed (still faster than HEF4053) could be more important than lower leakage. It is more like charge injection and the supply current peaks I am worried about. The HEF4053 / CD4053 might be a little on the slow and high on resistance side this could effect jitter and the gain stability.

For some reason HP in the 34401 schematics has a ferrite bead at the VSS pin (negative supply). To me this looks odd as the voltage at this pin should not go much higher than some 200 mV even in peaks. I have tried this in combination with a capacitor to the VDD pin but it did not have much effect. The next try would be without the capacitor.

The noise is still a little higher with the faster modulation. So there is a chance things can get better with an even slower modulation (needs a larger integration cap). However I would prefer to understand and solve the root cause.
 
 

Offline splin

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Re: Multislope Design
« Reply #118 on: May 20, 2019, 02:28:54 pm »
According to AoEv3 HP uses the NXP version of the 74HC4053 in the 34401A. It may or may not perform any better than the other manufacturer's versions but it would be a good starting point. It's possible that the ferrite beads in the 34401A may be matched specifically to the NXP HC4053's characteristics.

Any idea why HP included the 42.2K R440 to pull down the 100K Vin signal just before the switches but didn't bother with the 30K +/- reference signals? The 100K/42.2K node is at virtual ground when the switch is operated so the only impact of R440 would be due to the input offset voltage of the integrator, but I would have thought that would be negligable?

 

Online Kleinstein

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Re: Multislope Design
« Reply #119 on: May 20, 2019, 06:04:50 pm »
100 K in parallel with 42.2k gives 30 K impedance. It helps to have the same resistance at the inputs to the 4053 as in this case the TC of the external resistance plus the switch resistance is matched. The same resistance is also important for the effect of residual input voltage at the integrator. This is not only the offset, but there is also a dynamic component.  Some of the errors only contribute if the impedance changes with reference setting. So resistance matching can help with linearity.

They could have started with 30 K and a smaller (e.g. 3.5 V) range  - possibly the design started with this. The 34401 was designed to follow the 3457. It is just the time when going from 3 V full scale to 10 V fulls scale. In my opinion using this combination at the input is one of the weaker points and adds to the noise.

The way the 34401 ADC works with continuous integration and no rundown it needs a rather high resolution from the run-up
and thus the fast modulation (essentially the same as in the 3458). However due to the slower integrator settling it requires relatively long fixed phases and thus a reduced voltage range. 

Using 100 K for the signal input helps to keep the self heating low and thus helps with linearity.

A looked the datasheets for the switches and found that there seem to be quite some internal capacitance inside the HC4053 - the power dissipation capacitance is quite high (some 38 pF). This suggests quite some current peak on switching. In this respect the 74LV4053 looks quite promising (only 5.3 pF). Though not in the specs I found, changes are charge injection and supply spikes could be quite good. Anyway my idea is to get the needed extra resolution from an extra rundown phase so that I can use a considerably slower (e.g. a factor of about 10) modulation, so that the switches should be less critical.

I think L401 and L402 are there to reduce charge injection by getting a higher impedance at the 4053. They also keep the very sharp peak from the integrator and ground.
L403 is a little odd: it's at the negative supply. Normally one would prefer a well decoupled supply for a chip. The extra impedance at the negative supply pin could effect the charge injection and switching speed. I would expect a slightly slower switching and possibly less charge injection.
 

Online Andreas

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Re: Multislope Design
« Reply #120 on: May 20, 2019, 07:36:23 pm »
Have you tested MAX4053 for comparison?
Hello,

I would use the MAX4053A (lower leakage current).
Besides this the MAX4053A showed lowest INL against CD4051 and 74HC4051 in a 32 Bit resolution PWM-Divider.

With best regards

Andreas

« Last Edit: May 20, 2019, 07:45:12 pm by Andreas »
 

Offline splin

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Re: Multislope Design
« Reply #121 on: May 21, 2019, 01:19:52 am »
100 K in parallel with 42.2k gives 30 K impedance. It helps to have the same resistance at the inputs to the 4053 as in this case the TC of the external resistance plus the switch resistance is matched.

The 42.2K is grounded at both ends when the switch is closed. If the integrator is perfect, there will be no offset, static or dynamic, so no current will flow in the 42.2K thus its TC and resistance will be irrelevant.

A good spot that the 100K//42.2K is 30K - which surely is to match the switching time of all three switches - since they will all have nearly identical capacitance (and inductance).

Quote
The same resistance is also important for the effect of residual input voltage at the integrator. This is not only the offset, but there is also a dynamic component.  Some of the errors only contribute if the impedance changes with reference setting. So resistance matching can help with linearity.

Sorry don't get why the source impedance seen by the integrator is relevant so long as the integrator is operating within its limits. I agree that any offset voltage, so long as it remains constant, will cause an offset to the output which will be calibrated out. As far as I am aware, the 3458A ADC integrator doesn't see constant input resistance during its operation.

Quote
They could have started with 30 K and a smaller (e.g. 3.5 V) range  - possibly the design started with this. The 34401 was designed to follow the 3457. It is just the time when going from 3 V full scale to 10 V fulls scale. In my opinion using this combination at the input is one of the weaker points and adds to the noise.

Noiser because of the higher thermal noise of the 100k resistor compared to 30k?  It's an interesting thought that they simply scaled the 3457 design; it would be interesting to understand how the ratio of the reference currents to the Vin current affects the linearity.
 
Quote
The way the 34401 ADC works with continuous integration and no rundown it needs a rather high resolution from the run-up and thus the fast modulation (essentially the same as in the 3458). However due to the slower integrator settling it requires relatively long fixed phases and thus a reduced voltage range. 

It doesn't have a rundown because it uses an ADC to measure the residual integrator charge, getting approx 3 digits from the run up (@ 1 NPLC) and 3 digits from the residual. From the service manual page 101:

Quote
Each analog-to-digital conversion begins when the multimeter is
triggered. The ADC starts by clearing the integrator slope count in U501.
At the end of the integration period, the slope count is latched.
The slope count provides the most significant bits of the input voltage
conversion. The least significant bits are converted by the on chip ADC
of CPU U500.

Quote
Anyway my idea is to get the needed extra resolution from an extra rundown phase so that I can use a considerably slower (e.g. a factor of about 10) modulation, so that the switches should be less critical.

A rundown will be slower than using an ADC to get the residual, but the linearity may be slightly better as the linearity of the integrator capacitor's voltage/residual charge relationship may be affected by dielectric absorbtion. Always returning the charge to zero should largely eliminate DA errors.
 

Online Kleinstein

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Re: Multislope Design
« Reply #122 on: May 21, 2019, 01:20:57 pm »
The same impedance for all 3 inputs is importance mainly because of the switch resistance (some 70 Ohms for the HC4053) and the related high TC. So this is essentially the reason for the 42 K.
The 3458 uses different switches for the signal and references and thus could use different resistors for the input and the reference. The way it is used there (40 K for the references and 50 K for the input) is still not a solution I like - using also 50 K for the references and 25% higher reference level would have given lower noise.

The other point is the same resistance for the positive and negative reference. This helps that an non ideal zero voltage at the input of the integrator will produce the same offset. An non ideal input can come from the integrator offset (less critical as constant), but also from the settling after the references change.  A simple 1 OP integrator would have some kind of square wave of a few mV (depending on the OPs GBW and the integration cap). With the 2 OP integrator like used in the 34401 and most modern designs, reference switching causes a peak (some 10 mV range) that recovers to near zero after some 0.2 to 2 µS (depending on the  speed of the OPs). The problem is if these peaks have a slower contribution (that may not be visible on the scope) that extends to possibly the next phase.  The peaks are OK if the integrator is at always the same impedance at the input.  The constant impedance is only important in the run-up phase - the rundown phase has relatively few transitions in a fixed sequence (but variable timing) is thus less critical.

I don't think the 34401 ADC is more like an upscaled 3457. It is quite different in many points - the 3457 ADC actually works with 10 V full scale and the amplifier adds gain.  It only looks a little like they may had a 3 V full scale range in mind.  Changing the 100 K at the input to 30 K would make the ADC from the 34401 a perfectly good ADC for a 3 V full scale range, like it was common in the old days.
Using 100 K to a 10 V full scale range and 42 K to me looks like an after-though to make the ADC work with 10 V full scale, at the price of more noise. The resistors can actually be a major noise source for a good ADC. For the integrator with it's current input it may help to look at it as current noise. In this view the 42 K does not contribute to the signal but adds current noise. The 30 K resistors from the reference also add quite some current noise.

Using the auxiliary ADC to measure the voltage at the integrator output is fast, but it also has a limited resolution. The scale of the ADC depends on the integrator resistors and the capacitor. Especially the capacitor tends to be not that stable, so that a frequent check of the scale would be needed. So getting 3 digits from the residual charge is already on the optimistic side - it's more like 4 digits from the run-up and 2.5 digits from the µC internal ADC. The resolution from the run-up part is limited by the speed of the modulation. The very fast modulation of the 34401 has 2 negative consequences:
1) the fixed phases in the run-up patterns reduce the input range. In the 34401 only some +-3.5 V (if they would use 30 K from the input)  of the +-10 V reference range are actually used. Slower modulation (like in the 3457, K2000) could have allowed some +-8 V or so.
2) It needs a fast integrator. For the 34401 they choose the OP27 for the precision OP in the integrator, probably for speed reasons. For the noise performance the OP27 is a poor choice here, because of the current noise. Other older precision OPs (e.g. LT1001, OP177) are likely too slow.

A rundown phase needs some time, but not necessarily that much. The 3457 needs some 150 µs, my solution currently uses some 200 µs (120 µs with a single ADC conversion), with a possible speed up to the 50 µs range. So for a 20 ms conversion the time lost is not that relevant. For best precision one would likely anyway alternate between a zero and a signal reading anyway. So some time is anyway lost for the input switching and the continuous integrating version needs extra settling to start with.

The rundown, especially in the classical form does not help much with DA. It avoids possible nonlinearity of the capacitor - however most capacitors tend to be very linear (e.g. better than many resistors). The DA of the capacitors usually has 2 contributions: a fast one from dipole orientation, that happens on the 1-10µs scale and a slow one more from internal surface charges on the 1-10 seconds scale. The fast DA part can be a slight problem with the classical rundown with a comparator to stop the slope. However already a slower slope phase would reduce the fast effect as the last 10 µs before stop don't vary that much. An additional waiting time (some 10 µs) can further reduce this fast effect.
The slow DA mainly hides some charge proportional to the average integrator voltage and gives it back later. This effect does not depend much on the details of the ADC. It can be effected by the way the references a controlled during run-up, as this effects the average voltage. The nice point is that the expected DA related error would follow that average voltage curve, so one has a clear signature to look for. Attached is a curve for the average integrator voltage measured for an input voltage range around  the center (horizontal units about 42 µV).

A fast modulation and thus less charge stored in the capacitor is very effective suppressing DA. With a reasonable good capacitor DA should not be an issue for a modulation faster than about 20 kHz. The ADT6581 DMM (8 digits) even gets away with only 5 kHz and not very good feedback during run-up.
« Last Edit: May 21, 2019, 01:23:39 pm by Kleinstein »
 

Offline iMo

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Re: Multislope Design
« Reply #123 on: May 21, 2019, 11:35:21 pm »
Quote
I think L401 and L402 are there to reduce charge injection by getting a higher impedance at the 4053. They also keep the very sharp peak from the integrator and ground.
L403 is a little odd: it's at the negative supply. Normally one would prefer a well decoupled supply for a chip.
The ferrite beads - sometimes it is enough to place a ferrite bead (or a small ferrite bar) close to a pcb track and watch the signal on the oscope's screen. You may see the noise or peaks lowers. Then you may insert the bead into the track in the final design.
 
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Online Kleinstein

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Re: Multislope Design
« Reply #124 on: May 22, 2019, 07:42:33 am »
Quote
I think L401 and L402 are there to reduce charge injection by getting a higher impedance at the 4053. They also keep the very sharp peak from the integrator and ground.
L403 is a little odd: it's at the negative supply. Normally one would prefer a well decoupled supply for a chip.
The ferrite beads - sometimes it is enough to place a ferrite bead (or a small ferrite bar) close to a pcb track and watch the signal on the oscope's screen. You may see the noise or peaks lowers. Then you may insert the bead into the track in the final design.
The spikes the ferrite beads are working on are still quite small. In addition they a superimposed by the "normal" charge injection and integrator input settling. So there is quite some normal background and and a little very fast bit (e.g. the rising edge) the ferrite beads are likely supposed to improve on. At least with my analog scope I see no chance to watch the effect live. If at all it would need a good DSO and averaging over many cycles (high resolution, box integration mode) in a special test mode of the circuit (for a stable signal). So far for me the ferrites are something like trying different version on pure chance and compare the outcome.
As the circuit is not very fast, I don't think just a ferrite on a trace would have enough effect. Anyway, there is not much trace to work on anyway.

My current problem are odd (likely high frequency) signals that cause odd EMI like effects. E.g. the reading changes quite a bit with a wire attached to the 5 V supply of the µC or ground at different points of the circuit. The problem is that the RF junk is likely to small to see on the scope.  Likely the xx4053 emits some RF spikes that cause funny effects from resonances somewhere in the circuit or attached wires.  I think the 4053 is the source, as the effects get much better with the slower HEF4053 version. I have some new xx4053, ferrites and better OPs ordered.
 


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