Multislope Design

[Kleinstein]

The OPA189 or similar makes sense for the input buffer, only if one needs low drift without auto zero. Normally the OPA140 should be still lower drift than the integrator. Here it could be about the accuracy: The OPA140 OPA1641 has very high gain, but linearity may be limited by the still good CMRR. The OPA1641 OPA140has better CMRR, but less gain. Bootstrapping the OPA145 improves on the CMRR, but in the current form is a bit on the slow side.

For the Integrator OPA1641+TLE2071 is what I currently have, but other combinations are possible too. I don't even consider the TLE2071 a very good choice. Chances are OPA145+OPA1641 may work slightly better, as the OPA1641 has lower output impedance.
Just the single OPA140 may be good too. It can have some advantage in faster settling than the compound integrator, but would like very well matched resistors for the references. So it depends on the rest of the circuit.

The slope amplifier is relatively uncritical. It should be fast and low noise (e.g. less than the integrator), so the NE5534 is often kind of good enough and cheap. If a very fast comparator response is needed something like OPA209 (20 MHz GBW) could be an upgrade.

For the reference amplification it depends: in my form the amplification and load is static, so the OP07 is good enough. It contributes a little to the noise and drift, but not much. The AD8676 can be better and this may be needed for a rather dynamic loading to the reference.

In my circuit I use the µC internal comparator. With a slope amplifier the comparator noise should be no longer that critical and often the slope amplifier also sets the effective bandwidth. So the LM311 can be good enough in quite a few cases.

Quite often the OPs are not the really critical parts. The switches and the resistors can contribute quite a bit: quite some offset drift is due to a change in the ratio of positive to negative reference due to resistor drift. For this reason AZ OPs are of limited use there.

Quite often there is also a good enough: e.g. the OP07 are usually better than the LM399 reference when it comes to drift and noise. With only 20 ms (and up to some 100ms) integration the OPA140 or OPA145 for the integrator are lower noise than the usual 50-100 K resistors at the integrator: so there is limited use of even lower noise OPs here.

The integrator speed determines how fast the modulation can be.  A very fast modulation is mainly needed to allow a very small integration cap and this way reduce the higher frequency noise, that is relevant for very short integration (e.g. 1 ms).  As charge injection may also contribute, a very fast modulation is not good per se. Some 10-20 kHz should be fast enough to avoid DA related errors (at least the slow part), even without super fancy caps.

[iMo]

While reading the service manual of the 3478A (the Mutlislope detailed description chapters) I find myself asking why the meter is just 5.5digits, when Jaromir's and Kleinstein's meters are attacking 7digits with ease.

The 3478A's MS algorithm and the hw around (ok, the opamps are rather oldish and the switches inside the hybrids have unknown parameters) is much more complex than the 2 designs above.

For example more complex phases, variable rundown currents, 6bit DAC for integrator's offset compensation, etc.

Does the additional 78's DMM circuitry limit the "achievable" resolution (like dividers, etc) while the MS ADC itself can do more?

How would the 78's MS ADC perform with modern parts?

[Kleinstein]

The ADC inside the 3478 is more like a reduced version of the 3457 (near 7 digit performance). AFAIK it uses slower control buy a CPU but possibly the same hybrid (though possibly lower grade ones). The 3478 is also one of the better 5.5. digit ones.
The old Multi-slope II ADC still has a few weak points:  The modulation is relatively slow and the integration cap relatively large this results in some noise contribution from the comparator / slope amplifier. This is especially important for relatively short integration.

The integrator has one reference path always connected and is only switching one side - this increases the noise gain for the integrator OP and adds extra noise from the resistors. Using the difference of positive and negative current also adds to drift / uncertainty.
With relatively slow control the theoretical resolution is also limited. The CPU used is considerably slower than the modern single chip µC or FPGA.
The 3457 with an ASIC for faster control is considerably better resolution.
I don't think the ADC solution is especially good, as it is quite some effort. But this was about the state of the art by that time.

My design is more like an improvement from the HP34401 on. It is also made with a simple circuit in mind, making it even simpler than the ADC in the 34401, despite of better performance. It also uses quite a few function inside the µC (ADC and comparator). With parts from the 1980s the circuit would not be that simple either.  Better OPs also help as there is no more need for analog offset compensation.

[jaromir]

Though Kleinstein gave his answer, here are my two cents:

While reading the service manual of the 3478A (the Mutlislope detailed description chapters) I find myself asking why the meter is just 5.5digits, when Jaromir's and Kleinstein's meters are attacking 7digits with ease.

I'm aiming at 6,5 digits with my design. My design is simpler than comparable designs from 30-40 years ago because:
1, I keep feet on the ground: I do not shoot for high acquisition rates and have realistic 6,5 digit resolution in mind. Having high throughput of meaningful data is difficult and I'm not doing it.
2, New analog components. With better analog components, one can sometimes do less compromises, omit compensations, corrective circuits, cherry-picked components. That makes overall circuit much simpler and less laborious to build and setup.
3, FPGA/CPLD - this is expansion of point 2: in older TE there is often quite bit of circuitry to workaround that they didn't want to roll new ASIC for each meter. With FPGA and CPLD for a few bucks I can make he digital circuitry as needed and save five+ digit USD stash for ASIC. Alternatively - as Kleinstein demonstrated - MCU with appropriate peripheral set can do great job for fast digital circuitry, unthinkable in i8049 era.
4, Standing on shoulders of giants. I can take inspiration from patents, repair manuals and technical notes written by a lot of clever folks, sharing their hard earned knowledge.

All those points are doing the ADC design much simpler, less time consuming and therefore cheaper; available within reach of average hobbyist within limited time frame during lunch hours or evenings when kids are sleeping.

[Rerouter]

It seems most of the current multislope designs in the wold can trade resolution off for aquisition rate, could either of your designs do the same, or is there some fundamental limit that would prevent say 50x the sample rate but only resolving to 3.5 digits (and similar steps in between)

[Kleinstein]

The ability to trade in resolution for speed is a general feature of the multi-slope ADC (and also the sigma delta ADC).
There are several effects that limit the range and how a shorter conversion effects the resolution/noise:

Towards very short conversions the resolution goes down proportional to the integration time. It depends on the design wether this limit is more due to the theoretical resolution (e.g. time steps for the last rundown) or from the higher frequency noise that can limit the useful resolution for the final charge reading. So there is a practical limit on how good a timing resolution helps.
Towards very short conversions there is also the time lost for the rundown, that limits the useful maximum sampling rate. It does not make much sense to have integration much shorter than the rundown time.

The other effect that can limit the effective resolution is low frequency noise. This noise (if not dominated by 1/f noise) goes down with the square root of the integration time only. So it takes 4 times the integration time to reduce this noise by a factor of 2.  In the 1/f noise dominated range longer integration does not help any more. This extra 1/f noise limit can often be circumvented by using averaging of shorter integrations.
Often the real integration is only up to some 10 PLC and slower conversions are averaging with a zero reading in between.

So there are usually 2 ranges: resolution (theoretical resolution and noise) going up proportional to integration time T at short times.  At long times the resolution (noise limited) goes up with the square root only. This also applies to averaging of shorter conversions to circumvent the 1/f noise.   

Where the cross over between the two ranges is depends on the design - older designs with not so high timing resolution or relatively slow modulation tend to have the proportional to T regime up to some 10 PLC or so. For a good design it helps if the cross over to low frequency limitation is well below the 1/f noise range.

[jaromir]

...is there some fundamental limit that would prevent say 50x the sample rate but only resolving to 3.5 digits (and similar steps in between)

You can go as fast as you wish.
Integrating ADCs do have great feature - you can have fixed integration time in multiplies of power line period (20, 40, 60, 80... etc. ms for 50Hz) and thus suppressing the power line noise right at the ADC level, with no need for digital filtering.
Having shorter integration times is indeed possible, but you are losing this advantage, so if you are into higher acquisition rates and you don't need much of resolution, there is nothing that keeps you from using other ADC types, like SAR. There is plenty of ADCs with 10-12bits of resolution running up to few MSPS, often even inside modern MCUs.

[Rerouter]

In the meanwhile, Any chance I could see the Mux / Integrator parts of your original PCB layout, Having a crack at re-spinning Klenstein's as a bit of a personal learning experience on high precision layout, but the 4053 does not make it easy to escape route the positive supply rail, and would like to see what the other side of the fence looks like with yours Jaromir. Equally the analog ground run to the integrator is a bit weird to me, its low impedance essentially, but has to be treated as a very high impedance signal best I can tell, having the input and analog ground treated almost like a differential pair.

[iMo]

Now, what about the 3 resistors at the integrator's input - Jaromir's 200k+100k+100k, vs Kleinstein's 50k+50k+50k.

There is the resistor's thermal noise, TC, ratio matching TC, the switches On resistance and self-heating to consider.

I've been thinking to use the LT5400 there - either 4x100k or 4x10k version (there is none other suitable version there available, afaik). Perhaps the 4th resistor as a heater with 4x10k version (the 100k creates only 9mW at 30V, not sure it is enough).

What would be the right optimal choice, considering the OPA140 as the integrator and LV4053 or DG switches??

PS: It is my current understanding nobody here considers to build a high speed MS ADC here.
A few/couple measurements per second max would be great with 6.5digits, or less for 7digits with longer integration..

[Rerouter]

Kleinsteins is 25K+25K+25K, he paralleled the resistors. there is a FB resistor on both paths that I'm not quite sure of the value of, which would increase the reference resistance,

[jaromir]

...would like to see what the other side of the fence looks like with yours Jaromir.

There is dedicated thread about my design here https://www.eevblog.com/forum/metrology/diy-6-5-digit-voltmeter/ all with complete schematics, PCB layout, source files and stuff.
That being said, I'm not claiming this is the best possible design. In the meantime I found a few flaws with the PCBs and will do respin. I released all files to public, so anyone is invited to discuss, study and improve it. When I do respin, I'll surely update the uploaded files or start public repository, so it doesn't get too messy.

[Kleinstein]

The resistors at the integrator are kind of a balance between noise from the resistors and errors due to self heating and the switch resistance.
In my configuration with 3 equal resistors the resistor contribution to the noise is as if 2 of the resistors are in series, contributing there voltage noise. So with 3 x 50 K one get the noise from 100 K which is about 40 nV per square root Hertz. The OP in the integrator contributes about twice its voltage noise. So for an OPA140 and 25 Hz  (assuming a 20ms signal / 20 ms zero cycle) this would be some 8 nV/sqrt(Hz). So the resistor is actually more important for the noise than this OP.
I know a few more other noise sources, as the reference amplification, the buffer, but these should be small (e.g. 10 nV range).
For the difference of 2 readings (signal and zero) one effectively has a noise bandwidth of 100 Hz. So the measured noise of some 700 nV RMS corresponds to some 70 nV/Sqrt(Hz) for the single conversion. So there is still some noise not accounted for.
With 25 K resistors the noise goes down to some 550-600 nV.  It looks like I have some 1/f type noise, as the noise gets worse at 2 PLC and 4 PLC. For the time being I consider the noise low enough.

With 100 K resistors for the integrator one would be at some 60 nV from the resistors. If the specified -<45 dB noise level for the LT5400 is true, the excess noise should still be not too bad. So the overall noise could still be good. With very stable resistors like the LT5400 one could get away without the extra 7 V reading in between.

Using a 4 th resistor as a heater is possibly. The 2 reference resistors see a constant power. The maximum signal voltage is at about 12 V. So a voltage up to 12 V would be enough for compensation. As there is usually alternating zero and signal reading the heater could get away with some 8.5 V or so as the maximum.  Due to the good TC matching in the LT5400 I see no real need for heating though.  Power compensation would be more a thing for something like NOMCA type resistors with less perfect TC matching.

Attached are the PCB files for the TOP and bottom.  The bottom needs an additional connection drawn in red, as there was a mistake. With SMD type ferrites and without the initial error the layout may even get simpler. The board is an odd mixture of SMD and THT. The 4053 is the DIP16 below the center of the board.  I had used resistor symbols in the circuit for the ferrite beads - these should have very little DC resistance. These are kind of a copy from the HP34401 configuration.

I consider the placement of 4053, integrator and resistors good - the position of the buffer amplifier and LM399 so close to the DG408 is more of a problem. The supply to the 4053 should still have some filtering. That is currently done with a bodge and cut.

[jaromir]

...Perhaps the 4th resistor as a heater...

LT5400 does have exposed pad, and manufacturer suggests to connect it to quiet analog ground, to decrease resistor-resistor capacitance; groundplane helps to decrease self-heating, too.

[iMo]

I wanted to use the exposed pad as the contact place where to measure the temperature of the package while heated. But it seems it is not required with the 5400 (see above).
4x10k is too low then?

[Kleinstein]

With 10 K resistors and some 14 V reference (twice the raw 7 V from LM399 / LTZ1000) there would be quite some power: some 20 mW for 2 of the resistors and up to about 10 mW for the 3 rd resistor. Even with the thermal pad the temperature rises by some 40 K/W. So 10 mW of variable heat would result in 0.4 K temperature variations.

The second problem it that the switch resistance gets more important.

A third problem is that the integrator would need to cope with larger current jumps. The usual OPs (like OPA140, OPA172) have an open loop output impedance in the 100 Ohms range and a 2.8 mA current jump would thus cause spikes up to 280 mV. This could well exceed the linear range even of JFET based OPs. A two step transition could halve the step, but it is still quite a lot.

So the 10 K array is  on the low side,  likely causing higher INL errors.  A 100 K array (like Jaromir uses) may be a little on the high noise side. Still some 60 nV (compared to some 40 nV with 50 K) from the resistors is not that bad, especially for a first test. Though a little tricky from the layout, there could be the option to have a second array in parallel, if really lower noise is needed.
At least for a 1st test there are also MORN resistor arrays. These are same size as the LT5400, but cheaper and also available as 50 K and 20 K.
For comparison the HP3458 uses 40 K and 50 K resistors and +-12 V reference. Noise wise this is slightly worse than 3x50 K and +-14 V reference. They use some 10 K für the high speed modes - so using 10 K resistors (though with only 12 V reference) is not totally out of question.

The integrator resistors are important for the ADC gain stability and the one for the input can effect INL due to self heating. The critical parameter is TC matching if the resistors are coupled - so the LT5400 is really good quality.
The gain stability is also effected from the resistors used to amplify the reference. Here 4x10 K resistors is a suitable value.

[Rerouter]

Kleinstein might I ask what the value of R102 and R35 are, It seems to me that these should be very close to 0 ohms to prevent the references and bufffered input from effecting each other,
Equally I'm suprised you have not needed a negative supply on the 4053, as the internal switch resistance in the chip should mean the negative references input should be some small negative voltage.

[Kleinstein]

R35 and R102 are ferrite beads. So likely something like 0.1 Ohms of ohmic resistance and some lossy inductance.  Currently there are 300 Ohms nominal (at 100 MHz) - I am not sure if this is right.
The CMOS switches actually also work a little (like 200 mV) outside the supply range. So up to about -200 mV are OK without a negative supply.  For highest performance a slight negative supply may be good, as for the 74 HC4053 charge injection is supposed to be minimal with some -0.5 to -1 V supply, at least for some manufacturers that show a curve.  I have tried it with a negative supply, but at least the way I had it (with just a diode to get some -0.6 V) did not help.
With some 50-100 Ohms of switch resistance and some 200-500 µA of maximum current, the voltage should only reach some -20 to -50 mV.
However it is an argument against using much higher reference currents with 4053 switches.

The switching part I use is to a large part similar to the HP34401. This also includes the ferrites. I don't fully understand why, but they did some improvement.

[Rerouter]

Still working on the routing, It breaks a lot of conventions I'm used to, everything has to be planned as a differential current loop to prevent any kind of cross talk or interference with the measurement, meaning there are vastly different requirements for how quiet the ground should be for a given area, e.g. R35 seems like you would just connect it to the same ground as the analog filter, but that is not quite correct, the ferrite beads ground needs to be well away from it as its switching significant currents compared to the sensitivity of the system and its performance does not effect the measurement at all, its just giving that current somewhere to flow, and how the input filter needs to be almost directly at the input of U11, as that is the only place it forms a current loop with ground,

As far as I can see, the analog ground used for the integrator needs to be treated like a differential return all the way back to J2, with the references referenced off that point. but leaving something having to be done about all the current from the zener... I', slowly unwrapping it all, but I can see why people say laying out these boards can be harder than designing them. I suppose once its built up into a well planned block it will be a reusable module, but wow does this strain the brain.

In these type of circuits, how much effort is generally put to having ground planes on the reverse side of the board overlap the chips, as that could increase power supply noise coupling in, but I would imagine the shielding being a bigger benefit.

Or have I accidentally started trying to design far better than is actually required?

[Kleinstein]

I also think keeping the analog / signal ground separate is a good idea. I just consider it as a separate, e.g. analog signal, though I have a connection (via a wire) at one point. In theory the connection could later be external too, e.g. at the output therminal or the voltage sense wire of a shunt. One could even consider to have the signal ground at a level of something like +300 mV to essentially get a negative supply to the 4053.

For the current to the zener reference, there is a resistor to provide most of the negative side current from the -13.5 V reference and not through ground. Anyway the residual current is constant and thus less critical. The really critical one is variable current.

For low frequency DC a ground plane is usually not the right thing to do - it is more like star ground. In may layout I did a few compromises on this, where there should be not much current (e.g. input to the NE5534), especially not much variation in current.

The digital part may like a ground plane. One point that worked well for me is to no only isolate those parts that are sensitive to RF interference (e.g. analog VCC of the µC), but also have the same resistor or ferrite type insulation for those parts that produce interference. It may be a good idea to add even a few more such resistors, e.g. in the supply to the OPs for the reference amplification. Ideally one would a void to have a low impedance supply trace to both side of the decoupling caps. Just a cap is not a good filter - a cap and resistor is much better.

The layout may be tricky, but it looks like other meters (e.g. the ADV6581) get away with some really odd choices in the layout / placement. So one may not have to overdo it in the first try.
I see some odd effects around the DG408 MUX, like different inputs behaving a little different. It may be a good think to keep the reference with it's heat a little more away from the DG408. Another thermal to observe is that the buffer amplifier is a variable heat source and should thus be not to close to sensitive resistors. This may be a little less critical with really good resistors as an LT54000 array. From my circuit, there is one more idea: the filter capacitor for the reference can be from the -14 V instead of GND. This gives effectively 1/3 the filter frequency.

[iMo]

I would not put the voltage regulators on the ADC board as they are a large source of heat. I think Jaromir had recognized that too as he moved the regulators off his ADC board (compared to his prototype).

[jaromir]

That is correct observation.
It's always advisable to have little thermal gradients on sensitive PCBs.

[Rerouter]

Kleinstein for your design, It looks like by trimming R77 to a slightly lower resistance (about 14.3K) it reduces the references ground current to almost 0, is there a particular reason behind it being 15K flat, or could it be trimmed like this so ground is just a null point. Just trying to rework things to have there be a very quite signal ground shared by the references and integrator, so the less current I dump on it the cleaner things should get.

I'm also not quite sure how to manage the power rails, as it ends up that the integator charge current is looping through the supply rails, not the signal ground, meaning I need to make a very quiet connection between the integrator op amps supply rails and the buffer op amps rails, as that is where that half of the current loop is flowing

[Kleinstein]

The ground current compensation with R77 can be tuned for better compensation if needed. I originally had 2 resistors in parallel to get fine steps if needed - though one turned out unusable.
For the current to the integrator, one has to separate the AC an DC part. The integrator itself can only sink AC current, as the current has to go through the cap. The other current path is from the reference currents either to ground or the integrator.
For the current to the integrator, I have the relatively large resistors (150 Ohms) in the supply and the AC current going through 2 x 2.2 µF (C6 and C14) to the ground to join with the current from the switches.  150 Ohms * 2.2 µF is large compared to the modulation period (some 25 µs) - so not much of the AC current flows through the global supply.

The 5534 and the integrator share the same supply island with 150 ohms for separation, as there can be quite some current flowing between them, through R12. Originally I planed with a lower value for R12 to reduce it's noise (it could be important with a larger integration cap). Currently the 5 K from R12 give more noise than the NE5534 - though this higher frequency noise is still low and would be an issue only for very short integration (e.g. < 1 ms).

The DC path is from the supplies via the buffer amplifier through the integrator resistor (R3) towards and than through the 4053  directly to ground or kind of mirrored at the integrator and reference sources through the 4053 to the same ground point. I would not worry that much about the DC part flowing through the supplies - thats what the supplies are good for.

[jaromir]

I studied design of 34401 once more and one thing caught my eye:
The third switch (pins 3,4,5 and 9 of 4053), controlling input current from ADC input to integrator is constantly open *. In Kleinstein's design - which I considered to be similar to 34401 - this switch is operated by MCU. I have to admit his approach is easier to grasp for me.
If ADC input is never disconnected from integrator, how is integration time defined?
How do they perform residual integrator charge readout? I guess it's better to have integrator output voltage stable during readout, no matter how it's performed, that suggests turning the input off during that phase.

---------------------------------------------------------------------
* pin 9 is grounded, so that pin 4 is switched to pin 5 and pin 3 is never used.

[Kleinstein]

The 3rd switch of the 4053 always fixed and thus the input always connected also looks odd to me. For the normal operation this is not a problem: the ADC in the µC is relatively fast and reads the charge in the integrator on the fly, at some point in time. This time is effectively the start of the integration. A second later reading sets the end.
However there are a few difficulties, odd points still unclear to me:
1) the modulation is very fast, especially for the integrator used. This seems to limit the input range and require the large resistor for the input signal - noise wise a poor decision.
2) reading on the fly it is not clear on how much of the current phase / reference setting is effecting the reading.
   The last run-up step has likely only partial effect, but it is not clear how much.
3) the resolution is rather limited, as the ADC must cope with a relatively large voltage range of a full run-up step.
  This could kind of explain the limited resolution of the 34401.

Even if not needed for the measurement, I would very much like to have the option to turn off the input do do the internal calibration of the auxiliary ADC scale. They may get away with switching at the very input to ground.

When switching between the input signal and zero reading, one still has to wait for the input amplifier to settle. So the continuous integration is not such a big advantage, as the non AZ mode is quite noisy from the OP27 anyway.

Some of the Solartron DMMs also have the input signal continuously connected, though they do not use an extra ADC, but the comparator timing.

I also see my design as based on the 34401, at least its a good point to compare: the 2OP integrator, 4053 switch, no integrator reset and using the µC internal ADC for residual charge reading. The improvement is mainly from the added rundown phase (so mainly a 'software' point), that adds to the resolution and from using better OPs in the integrator.