Multislope Design

[Kleinstein]

It is interesting that the amplifier is still very close to the old 3458 design, even including the somewhat problematic inductor.
For the amplifier simulations the models often don't include variations between units and thus assume perfect matching between equal part. This can lead to a bit optimistic simulations. The measured performance is still impressive (in parts limited by the test system), though odd that the TL071 version outperformed the OPA1655 version.

With modern, relative fast precision OP-amps one should get away with 2 OP-amps in the integrator. It would mainly be with an AZ amplifier that the 3rd amplifier really makes sense. The version from J. Pickering should likely be OK without the AZ amplifier part. The OPA828 is also pretty good precision.  The AZ amplifier at the integrator could be effected by the switching transients, despite of the filtering. The resistors in the filter add quite some noise.

[MiDi]

True8DIGIT - Towards a true 8‐digit digitiser: https://true8digit.eu/
The Project flyer gives an overview of the project.
Project Progress Presentation at EURAMET TC-EM SCs Joint Meetings at IPQ
Publications: https://zenodo.org/communities/22rpt02

New exciting publication: Composite Operational Amplifiers for front-end and integrator

Project Final Workshop 15th May 2026

[MiDi]

I have a crude spread sheet for the noise calculation, that is attached. It may be a bit hard to read though.

Just played around with the numbers to see where the (theoretical) noise limit might be... 

[Kleinstein]

Combining multiple BJT based OP-amps at the integrator would increase the current noise. I may still not be as bad with the lower resistance.
It would need some extra circuitry to combine them in parallel. Not sure how this would work, as they don't have a local DC feedback.
One may just have to look for an alternative lower voltage noise OP-amp. e.g. the OPA210 is roughly comparable to 15 x OPA205 in parallel (2 nV/sqrt(Hz) and 400 fA/sqrt(Hz)). It is a bit on the low impedance side, but still not bad.

With a 2nd order feedback for the run-up one can likely get away with slower modulation / switching and this way get less noise from jitter and the switch capacitance. AFAIR the 2.2 nF integration capacitor is already relatively large and has reserves to go lower in the frequency. So one may not have to increase the capacitor as much.

The question with a lower resistance (about 2 x the current) is if the INL gets worse. The limiting point may well be the INL and not so much the noise.

One problem with uning 10 K for the input and 40 K for the reference and thus a lower range like 6 V FS for the ADC is that one could not directly measure a 7 V reference. The trick with measuring +1/2 and -1/2 for both sides of the input only works with an external voltage, where the low side can be moved. The internal reference would need an extra step to get +-3.5 or +-5 V from the 7 V reference.
There is a way around this, that I have planed for my next version: there are 2 prallallel input paths with separate switches. So one has effectively 2 inputs and gets a 12 V range when using 1 input at a time and gets 6 V with lower noise with both inputs in parallel.
One would measure the ADC gain with one input path at a time and than assume that the input currents / ADC gains should add to get the nominal gain of 2.

With 10 K for the input and 40 K for the references one would need 4 switches in parallel for the input and 1 switch for the reference to get the same resistor to switch resistance ratio. So no extra switch capacitance where it hurts.