Yep, the math makes it nice and clear, a trade of between pattern speed, capacitor size, modulation frequency and input range, with you pattern at about 45.45KHz, your original pattern would be 83.3KHz, and IMO's a flat 50KHz, have added in the drift, and resistor mismatch to the calc to put some actual numbers to the effect, main remaining quirk is working out the charge injection influence as the model of mux doesn't actually specify it, and there will always be some degree of charge mismatch as every time the fixed part changes polarity you end up with an extra transition, and that part is variable, vs input voltage,

Not accounting for capacitor DA, the rundown period for your method Klein should only be 40uS at most assuming single ref rundown. however knowing what the general way to model this would be ideal on these time scales,

Also still trying to understand exactly where your extracting the number of raw bits from, e.g. for 0V input, I would expect ~15216 Timer clocks for positive cycles, and ~16800 Timer clocks for negative cycles with a residue of -1.20545V

Have not yet fixed the math to get the counts at the exact comparator crossing, but this may help me to understand the specifics.