Multislope Design

[iMo]

doesn't make any sense for the analog lines, as they are inputs, and there sources have resistances of a few kilo-ohm, the digital outputs already have footprints for series resistors, I just ball parked 220 ohm to knock things down to under about 1MHz but it can be reduced further,

All atmega's pins radiate (the resistors are not there only because of fast edges), thus the resistors should be placed as close to the atmega's pins as possible (what is not the case in your latest design, imho).

PS: the usage of chopper opamps with different chopping freqs is not recommended (IMD products).
I would avoid that with an 8.5+ design..

[Kleinstein]

I have tried both an external oscillator and just a crystal at the mega48. Both versions work, with not much difference.
The external clock may be a little more stable, but the extra oscillator also tends to use more power and give a possible path for RF injected to ground. At least the old style large oscillators are quite power hungry.

The version with the slow slope can also run at a lower clock speed. So the µC does not have to run at 5 V. It may be OK to run the µC at some 8 MHz and maybe 3.5 V. The MCP6002 is still OK with 3.5 V or similar. If the 4053 still runs from 5 V, there are  HCT / LVT versions that can accept 3 V drive signals. Compared to the old µCs with external ROM (e.g. 80196 in the 34401) the modern ones with internal flash reduce emissions quite a bit. Good decoupling of the µC supply is still needed - this includes a resistor/ferrite bead not only for the analog side VCC, but also for the digital side VCC.  Just the usual capacitor at the supply and than direct (low impedance) connection to supply and ground is tricky, as there may be several low impedance caps at the supply and thus possibly currents oscillating between the caps.
Such a separation may even also be used with the OP07 at the reference - though these OPs are slow.

The current design does not use an AZ-OP in the actual ADC part. The amplifier before the MUX should be some kind of AZ amplifier or buffer - the different type discussed so far are more like alternative solutions. Even then 2 different AZ OPs usually work with quite different chopper frequency.

[iMo]

As an example how Fluke does it with resistors at the pins - here 22ohm (the source - xdevs.com).
External oscillator - a small smd 16-20MHz one adds 20mA worst case, imo.
The atmega328p works fine at 16MHz/3.3V.
PS: The atmega328p includes a "stable" 1.1V reference on the chip, thus you may use it for the ADC instead of the Vcc.
There is an on-chip thermal sensor you may read out as well.

[Rerouter]

I have them on the output pins for now, are you saying those are not close enough? I have been maintaining rule of thumb spacing to make sure average joe with tweezers can solder the things to the pcb, so these had to be a bit further away to fit a soldering iron tip next to potentially a socketed micro.

as for on inputs, I can add them, but I would like some rational behind how inputs with there input buffers disabled could be a significant noise source,

[David Hess]

I have always wondered if it is worth phase locking the conversion cycle to the power line frequency to maximize normal and common mode rejection or if variation in the power line frequency just makes things worse.

[splin]

I have always wondered if it is worth phase locking the conversion cycle to the power line frequency to maximize normal and common mode rejection or if variation in the power line frequency just makes things worse.

Datron did this starting with the 1051. I'd expect that many 6.5 or better meters will do this as it's relatively easy to do.

[Rerouter]

I suppose the question can be respun as. Are there any timing specific differences between starting on 2 diffent parts of the cycle while still integrating over an entire mains cycle.

If the non linearities are reduced below what the meter can determine. I do not think it would change anything. Mains frequency can shift. But it is not easy to measure that with low jitter if there are other harmonics on the mains.

[David Hess]

I suppose the question can be respun as. Are there any timing specific differences between starting on 2 diffent parts of the cycle while still integrating over an entire mains cycle.

No, the problem is not when to start during the mains cycle.  We know integration over a whole number of main cycles will cancel out power line interference and that this is necessary for good performance.

The question is whether the integration time needs to be frequency locked to follow the variation in power line frequency over time.  How much mismatch is acceptable and does the natural variation in power line frequency exceed it?  Or does having a slightly variable integration time cause even greater errors?

All of the precision integrating converters I have played with used a fixed integration time which did not track the power line frequency.  They rejected 50 or 60 Hz interference or both but relied on an independent fixed oscillator for timing.

[Rerouter]

The HP3458a manual gives an idea on how much influence a mismatch in frequency gives,
Edit: Tek DMM4050 gives similar numbers aswell,

[iMo]

50/60Hz sync: 34401A does it simply such it takes the voltage off the bridge (+/-15V inguard), limits it with a 6.2V zener and feeds it directly into a "high speed input" pin of the inguard 80C196.

[Rerouter]

It may measure it, but it doesn't look to actively compensate for it.

[iMo]

It may measure it, but it doesn't look to actively compensate for it.

Good point, I've been just thinking how they do it.. You may phase lock the master oscillator to the mains freq (they do not), or lock the process on the rising/falling edge of that L[ine]SENSE "signal".

[jaromir]

All of the precision integrating converters I have played with used a fixed integration time which did not track the power line frequency.  They rejected 50 or 60 Hz interference or both but relied on an independent fixed oscillator for timing.

In my design there is no frequency locking to mains. Integration time is fixed to 20ms (1PLC) from local quartz oscillator (cheap +-30ppm one), giving me some degree of power line frequency suppression, but given the fact it floats in range of few tenths of Hz around 50Hz*, suppression probably is far from perfect and drifts a bit. That being said, I have yet to find a situation where it really matters.

Locking to power line frequency isn't trivial excercise.
Some older meters had PLLs locked to power line frequency (Datron and perhaps some Solartrons had it too), but I read a few maintenance/repair reports where PLL was disabled and meter was fed with fixed frequency instead in order to decrease noise in readout.
Modern-ish meters usually don't have PLL. Many of them seem to have no provision to sense line frequency to adjust integration time, though there is option to manually switch between 50/60Hz PLC base. Some instruments do seem to sense line frequency from power transformer, but I don't believe they are doing anything else than just automatic switching 50/60Hz PLC base, as seen in Fluke 884x **.
No idea about really new meters, since service manuals don't contain schematics anymore.

* https://www.swissgrid.ch/en/home/operation/regulation/grid-stability.html
** https://www.eevblog.com/forum/repair/fluke-8840a-faulty-cpu/

[Kleinstein]

Really locking the integration time to the line frequency is tricky. The line frequency is not 100 % stable - thus the possibly need to adjust. The later solartron DMMs did a PLL lock to the mains frequency and this was a constant possible cause of failure. They are kind of special however using a very long integration. Other meters offer some kind of line synchronous start, likely with the idea to have any line related error more as a offset than getting some low beat frequency.
With a multi-slope ADC with rundown, there is however the problem that the extra rundown time would require quite some waiting after each conversion - so I don't think it is normally worth it.

For realizing mains look there are two possibilities:
1) use PLL and really adjust the µC/ADC clock. This can be tricky to get low jitter, as the mains signal may have some jitter too.
  So this would need to be PLL with rather slow reaction and thus difficult to build analog.
2) keep the clock constant and adjust the integration time by adjusting the number of µC cycles in run-up. Some adjustment is possible in software. I would normally not change that in real times as a different integration time could effect the ADC gain and offset a little. Doing the frequency measurement could be done in the ground referenced part.
If at all I would go for the 2 nd option.
For very short time (e.g. less than minutes) fluctuations it can be rather difficult to follow the true main frequency and not get upset by distortion, so it's not an easy thing to do in either way. Just a good measurement of the mains frequency is a tricky thing.

Mains frequency variation are rarely more than 0.05 Hz or 0.1 %. More typical seem to be some 0.01 Hz. So mains suppression should normally be better than some 0.1% 60 dB (single chunk integration).

With a fast running ADC (1 PLC) and using averaging instead of long integration at a piece, there may be an effect to make the exact length less critical: If the integration time is too long, there would short extra parts in excess of the full cycle that are extra integrated. As the total conversion takes a little (e.g. 0.2 ms) longer than a cycle, the  extra portions start at different times on the cycle, on the long run (e.g. 100 PLC) more or less evenly distributed over the cycle. With the other extreme of a single long integration the extra times would be as one chunk and thus possibly more sensitive to mains disturbance. The larger number of short extra chunks should give better suppression around the nominal mains frequency at the price of more sensitivity to higher frequency (e.g. kHz range) components. These higher frequency components should be relatively easy to filter out analog.  Averaging enough short integrations to get about evenly distribute the short extra (or missing) extra chunks should give extra suppression - ideally up to another factor of the frequency deviation. So mains suppression can get better for a certain number of averages (so that the total run-down time makes up 1 PLC, e.g. 50 Az cycles).

[Rerouter]

If it was pursued, I would say a software controlled integration time would be the easiest to implement as timer 0 is presently not used, pin swap PD4, hook up a mains to digital circuit of your choosing to give a clean signal,

For 60db of rejection, does require an average match of about 0.1% this is the harder point, 0.05Hz, but luckily the average mains is really slow to change in frequency compared to the sample rate, so it could be every minute or so, after the conversion, it compares timer0's delta to timer1's delta and uses that to calculate the average mains frequency and offset the integration time,

the amount of noise rejection is respectable, as that is the attenuation factor of the power line pickup noise which would already be attenuated by most measurement setups, I suspect the need for it is minimal,

edit: yes this is a very lazy and lower accuracy method, however it means that for the entire period, the ADC can be pumping out readings with no overhead, no interrupts, etc, and makes it very immune to any jitter on the detector circuit.

[Kleinstein]

I would give the mains measurement job to another µC. At the low frequency there are already not that many zero transitions to measure, which makes a good mains look a really demanding task. Just doing a simple timing on the start and end of a longer gate interval is rather sensitive to noise / mains distortion, even with some analog filtering. Averaging over too long would give the result late - there is not that much sense in adjusting the integration time to the frequency to the average frequency of the last 10 minutes. How the mains varies depends on the grid one is in - some weak grids (e.g. Russia) may drop more and over longer time, while some forms of wind energy can cause quite some frequency noise on the shorter run.

The ADC would than only get send a correction value to adjust the integration a little in software. At the start of conversion there can be an adjustable integrate only phase of a few 10 µs, that could be used for fine adjust, still leaving the modulation part at the same length. This phase could be just long enough to compensate the normal mains variation. When off by more it may need to drop a modulation cycle.

The roughly 60 dB number would be for fast conversions (without time adjustment and a more bad case frequency). With enough averaging the number should improve as the extra/missing time is not as a single chunk. One could even consider adding a little extra delay to the rundown so that suppression could get better already at some 10 PLC. Without an extra delay it's about 50 PLC signal +50 PLC zero when the rundown times make up another PLC and should give extra suppression, even with only the nominal frequency.

[Rerouter]

ok, separate micro, so SPI and a chip select, easy enough to accomodate, the other micro is fully task specific, work out the mains frequency right now, and when the chip select is triggered, be read by the ADC micro to do the adjustments, easy enough,

for just about any micro, you would technically have the resources to just sample the mains and DFT it, But I would probably prefer a rolling average reciprocal frequency, (then converted to an 8 or 16 bit correction value)

Edit: Unless something specific is in mind, I will likely just expose some dedicated 0.1" header for the option.

[iMo]

Here is an example of "possible" mains phase shift against the 34401A clock.
The measurement started at 14:18 afternoon, and you may see aprox 5000secs long periods, which slowly disappeared towards the evening, which I cannot explain other than with the mains 50Hz phase shifts..
PS: the X axis is in seconds..

[iMo]

PS: The atmega328p includes a "stable" 1.1V reference on the chip, thus you may use it for the ADC instead of the Vcc.

The internal bandgap Vref=1.1V is for the newer atmegas (like 48,88,328) with the classic atmega8 it is 2.56V internal Vref. You may use your own external Vref as well.

[Kleinstein]

5000 seconds would be a rather slow time scale to adjust the PLC lenght. It depends on the grid, but variations can be quite a bit faster (though a  weak grid on the edge may show a daily drop at power peaks).  The are other possibly internal things going on at such a period. Also external signals are possible like the AC or heating system.

The Ref. for the µC internal ADC is not that critical, as it only contributes a little (hardly 4 bits more than noise). So the µC internal ref may indeed be sufficient, as well as the 5 V supply. A divider from the main reference would also be possible. With a large temperature change one has the option to measure the scale factor - it is not just the reference changing, but also the integration cap and gain of the slope amplifier and final RR OP.

The mains-frequency measuring could be a dedicated µC or just from the ground referenced part at the display.

Adjusting the integration time can cause discontinuities, as the length can effect the gain of the ADC. Combining different length data can be tricky, even of the adjustments are not large.

[iMo]

fyi - an older thread on analyzing 34401A MS:
http://bbs.38hot.net/thread-17335-1-1.html

[Rerouter]

Had a go at doing an excel calculation for your modulation pattern Kleinstein, seems the max input range is about +10 to -11.2 for the current modulation style and the current reference levels.

Atleast based on how you had it described,

1us +ref
1us -ref
10us + or - depending on comparator,

[Kleinstein]

+10 to -11 sound about right for a 1 / 1 / 10 µs pattern. For a little more range, the comparator dependent phase can be slightly longer. I am currently using some 20 µs. This give some 10% more range.

The choice of the pattern is a compromise: less of the fixed phases makes the integrator settling more critical and can result in INL errors.  More of the variable phase makes the rundown phase longer. Worst case one has about 2 of the run-up steps for the fast part of the rundown. A slower modulation also needs a larger integration cap. Errors due to dielectric absorption also limit maximum length of the patterns. With a reasonable good cap there should be no problem below some 100 µs however.

[iMo]

Try with 1us P, 1us N, 18us P_or_N  --> that is 1000 phases in 20ms (50Hz mains).

[Rerouter]

Yep, the math makes it nice and clear, a trade of between pattern speed, capacitor size, modulation frequency and input range, with you pattern at about 45.45KHz, your original pattern would be 83.3KHz, and IMO's a flat 50KHz, have added in the drift, and resistor mismatch to the calc to put some actual numbers to the effect, main remaining quirk is working out the charge injection influence as the model of mux doesn't actually specify it, and there will always be some degree of charge mismatch as every time the fixed part changes polarity you end up with an extra transition, and that part is variable, vs input voltage,

Not accounting for capacitor DA, the rundown period for your method Klein should only be 40uS at most assuming single ref rundown. however knowing what the general way to model this would be ideal on these time scales,

Also still trying to understand exactly where your extracting the number of raw bits from, e.g. for 0V input, I would expect ~15216 Timer clocks for positive cycles, and ~16800 Timer clocks for negative cycles with a residue of -1.20545V
Have not yet fixed the math to get the counts at the exact comparator crossing, but this may help me to understand the specifics.