Multislope Design

[Rerouter]

And for the buffer, Q4 and the op amp handling the upper half of the bootstrap would be the variable heating? just figuring out how to best shift things about

[jaromir]

a raw value of 27 bits is exceptional, places it in the ballpark of 7-8 digits

I'm sorry to be 'that guy', but bear in mind that having reasonable 7 or 8 digits of result needs more than resolution. I think it's perfectly OK to aim for 5 or 6 digits for starters, learn the limitations and problems along the way, measure the real outputs, then look for better performance. From 5 digits on, each additional digit brings exponential growth of expenses, both material and development time.  And we are talking just ADC itself, you need some frontend too and finally results verification. There is a long way from ADC to finished instrument.
Proper verifying INL - for example - of "just" 6 digit voltmeter is not simple task unless you have real 8 digit voltmeter with proven parameters and appropriate calibrator at hand.

If all you need is ADC for your instrument, you may also take a look at recent single-chip ADCs, like AD7177, ADS1262 or LTC2380, develop/verificate it at the same time as this multislope ADC and compare the results. I believe it will not bring you much of time penalty and you'll gain a lot valuable experience.

[iMo]

Yea, managing the expectation of "diy makers" is important as many projects, even after a large effort spent, finished abandoned.. From my experience prototypes always work nice, until you start to mess with a final "production". As I wrote earlier, 6.5digits with 399 and the AVR firmware people could "enhance and cultivate" easily would be one giant leap for mankind

[Rerouter]

My only real requirements are about 5.5 digits repeatability over an hour period, and an integrator stage under my own control, so any more above that is nice. Even if I where to use those all in one ADC chips, most of the layout knowledge over laps significantly. and there datasheets imply I would likely have to use an external reference anyway, putting it in a similar pricing window, So a nice learning experience if nothing else.

The main thing is the way of thinking about how 1 part of the circuit can influence others on a scale I have not had to visualize before, e.g. thermal gradient EMF and how small variances are enough to upset things at distances of multiple centimeters due to differential heating causing offsets,

[Kleinstein]

At the 5.5 to low 6 digit level thermal effects are not yet that critical, unless something goes really wrong. The LM399 should be relatively simple to use and is not really sensitive.

Those ready made ADC chips also have there downsides and tricky points. For high performance one has to care about the termals and RF interference too. Another difficulty is the need to start with a 2.5-5 V reference. These tend to be more drifty than the LM399. Those ready made chips are quite good up to the 5.5 digit level and for very fast conversions (e.g. more than 1 kSPS) there is little chance to get it better with a DIY mutislope or similar solution. However for the slower conversions a DIY multi-slope converter can be competative, and the 6 digit range does not need magic. For the noise level even the 8 digit range is not that difficult.

The difficult part is more with the INL due to those effects like thermal interaction, nonlinearity in resistors, secondary effects on charge injection and so one. But this is more like the fun part to learn about.  INL testing is also a really difficult topic, but at least a partial test is possible. A full test at every possibly reading is not possibly anyway for a slow high resolution converter - it just takes too much time. For the tests it helps a lot if the noise is low. So it's nearly required to aim for a noise level considerably lower than the expected INL errors. To avoid the quantization noise it also help to have a numerical resolution better than the noise level.
The numerical resolution (quantization limit) is one of the least important properties, as long as it's good enough. The very high resolution (e.g. some 2-3 bits more than the noise limit) is more like an easy way to avoid the quantization noise, not a important property by itself. In the combination of rundown and residual ADC, high numerical resolution comes essentially automatic and with very little effort.

An ADC with numerical resolution higher than the noise limit and more INL error than the noise limit is kind of normal for high resolution ADCs. The numerical resolution and noise part are relatively easy. The main uncertainty is how good the INL will turn out. It is possible to calculate / estimate some effects up-front, but there is a chance to miss some.
The limit for a DIY solution is the INL test that can be done without even higher grade gear.  Some such tests, like the turn over test and the simple sum of 2 voltages can be done relatively easy, down to about 1 ppm level, possibly even better with many repetitions.

[Rerouter]

The are some parts of the ADC that change with input value, that may cause INL errors, e.g. the integration capacitor voltage (DA, leakage / offset causing drift), and the Input resistor self heating (which we now have a method to try and compensate for) below are my thoughts on how me might be able to try and reduce the influence of each, but happy to hear how you where planning it.

I suppose as a silly thought, we could use the DAC heater to instead measure how changes in heating create offsets while using ground as an input to remove any heating

For charge injection, we could likely measure it, have the input mux grounded, so the net current flow is rather low, switch the input, and measure the amount of charge by the known amount of capacitance on one side, and the resistance on the other (essentially an RC to ground) as the 4053 always operates at roughly 0V, this should be fairly consistent for all 3 channels. you then measure the other injection by switching the input off, and then back on, complete the same measurement but subtract the first measurement.

The error current from the op amp - inputs can be directly measured by disconnecting all inputs from the integrator and measuring with the ADC for the direction and magnitude of the offset, you could also perform a normal conversion and measure it that way if the amount was significant enough,  this would give the error current that would have to be subtracted from all inputs, You may be able to isolate what factors are causing what by also measuring it by the offset voltage caused over the input resistor with the input grounded. (e.g. 4pA * 100K = 0.4uV), which arguably puts it well under the effects of the op amps input offset, so I guess he will be the dominating factor... guess that becomes a direct measurement of the offset voltage then, convert to a charge per unit time and subtract.

The linearity over the entire integrator range Is fun, technically the EMF effects of U2 from getting warm when the clipping begins should be cancelled by U11, which I assume is an unintended bonus, C11 being a COG really should be as ideal as things get, most spec sheets show almost no difference with temperature or voltage, I suspect there is on this scale, as at this point input resistor heating and the bias of the integrator are taken in to concideration, I suppose a ramp up / ramp down set of tests could be used to try and find any kind of non linearity with the capacitor, going up for X time, then down for Y time crossing the comparitor line should be equal to going up for half X, down for Y and up for half X, I suppose by flipping around the ratio you could determine where any voltage based deviations may sneak in,

The slope amplifier, with as high a Gain as it has, I'm not sure how much of an influence self heating causes, it would be easy enough to measure, just leave it clipped for variable amounts of time to heat the diodes more or less, R12 gets warm and will be changing value unless we spec him low PPM it will offset the low level gain of the slope amp, R13 really only gets heated by the diodes

U13, nothing really gets hot, and the power of all the parts remains pretty stable,, cant speak for how your using the other half currently, but if it was unused, should not be an error source.

I suppose a fun thing about the test points is you could technically measure the ADC's own performance,

Power supply rejection should be OK for all op amps included, but possibly bad on the MUX,

Crosstalk from the digital signals should not be an issue as they are shielded to ground and have resistors to limit there slope.

I would ask what other sources of INL where you thinking?

[Kleinstein]

A good think of the multi-slope ADC is that many off the non ideal effects just produce an offset or gain error. So charge injection by itself only causes an offset current, that is essentially constant and this represents an offset. It would only be the changes in charge injection that really matter, especially those not linear dependent on the input. It still helps to have a constant number of switching events and even the same switching sequence for the 4053 - it is only the timing that changes, not the sequence.

Similar the input offsets and input bias of the OPs just add a slight additional current and thus result in an offset.

U2 doing all the work and getting signal dependent heating while U11 sets the precision is a nice side effect and could be now one of the main reasons to keep U11.

Input offset of U11 would not matter as it's one a general offset and corrected with a zero reading. One without an AZ mode the offset drift of U11 would matter. However the non AZ case is likely not that important for us, as it's only a thing for very fast measurements.

The capacitor C11 does not even have to be very linear. Most of the resolution is from balancing charge going in an out. So it's more about leakage and DA that do really matter. Only the last fre bits from the C internal ADC need linearity of the capacitor to maybe an 8 bit level. I have no doubt the cap linearity is good enough. Also G0C caps have a relatively low TC, so the scale factor for the ADC does not change much with temperature. C0G in this respect is better than PP, PS and maybe even PTFE.

The DA usually is composed of 2 contributions, a slow one with a time scale of some 1-10 seconds and a fast one with a time constant in the 1-10 µs range.
The effect of slow DA can be estimated quite well theoretical and it should be low, if the modulation is faster than some 5 kHz (I currently use some 40 kHz).  Such a slow modulation is not attractive anyway, as is would cause a slow rundown. The slow DA effect should correlate with the average integrator output voltage and I have measured this as an additional test signal. I could not see a correlation down to a really low level. Due to the extra waiting time before the final µC internal ADC reading, the fast time scale DA should not have an effect in my AC version. With MKS type caps it's visible on the scope but still not much effect on the result. Still no reason to use anything else then C0G for the cap - at some 1-3 nF  these are cheap anyway.

The heating of the 5534 OP should not be that critical. AFAIR 1 LSB of the µC internal ADC corresponds to some 5 µV (changes a little with resistors and integration capacitance used) at the integrator output. A more critical point could be heating of the diodes. In an early version with a higher values for R23 the diode temperature had a noticeable effect on the gain of the slope amplifier. Still not relevant for the result, but visible in the scale factor for the µC internal ADC. With 47 K I see no more effect.
If power consumption is an issue on could also use a different OP (e.g. OPA197) for U4. The noise is still low enough.

The other half of U13 is currently used as a buffer for an auxiliary signal, reading the average integrator output voltage to another channel of the µC internal ADC. The alternative use is for a temperature sensor via the µC internal ADC.

Other INL sources I thought of are:
The residual voltage at the integrator input combined with a resistor mismatch between R1, R2. This could be an issue with the 1 OP integrator.
Nonlinearity in the settling of the integrator input voltage - possibly an issue if switching comes before the input is settled. Changing the minimum delay should effect this.
A effect of input signal on the temperature of the 4053 or the supply to the 4053. Settling of the 4053 supply after a switching.
Capacitive coupling from the input buffer to the integrator, so that switching the MUX effects the rundown just in progress. No such effect is visible. Charge injection at the MUX and input current of the buffer effecting the 7 V reading. This is a possible reason to have a buffer for the 7 V to the MUX.
Capacitive coupling from U4 output to the integrator - this could effect the settling of the integrator depending on the current slope amplifiers gain. I test this with additional capacitance and the effect was minimal even with a lot of coupling.

So there are a lot of possible paths for small errors. Many of those I though of turned out to give no significant error.

Measuring the ADCs own performance is indeed a tricky part. For a first self test I did the comparison of two slightly different run-up versions with different modulation frequency. Ideally these two should give exactly the same result, but quite a few of the errors related to the run-up phase (like capacitive coupling, integrator settling, ...) should be different and also DNL errors from combining the parts should be different. So the difference of the 2 conversions is good test for much of the conversion. It is easy to do and low noise and thus fast and can thus test a large range.

[Rerouter]

Been calculating the maximum error terms,

E.g. the worst case error current on the integrator assuming u11 was a OPA145 would be (150uV / 25000) 6nA for your earlier design, which means the drift rate for the current cap would be up to 2.73V / second. and that would offset the input charge the same every time, but the slope back to 0, being a variable length will be effected based on how long it took, so it would be an offset/conversion time

The actual input bias / offset currents of both op amps is swamped out by that offset. even with a 100K input resistance, it reduces the maximum drift by 4, but still dominated by that offset voltage.

If you are applying that offset multiplied by the total conversion time, then yes its a simple offset.

Could an OPA189 be a better alternative? most of the specs seem equal or better, the bias current then becomes the dominant factor, but ends up being a lower error current for the circuit in total, around 0.137V / second,

Edit: Ok now I see, that would instead appear as an offset in the +- ref voltages, and can be resolved with a fixed offset there, because the error current effectivly stops in that moment between resistors, a very high input resistance when the integrator is open circuit means a very tiny current for a given offset voltage, getting the hang of this math, still would appear an option

Edit 2: now I partly understand your modulation, now just trying to interprit the assembly for exactly how you approached it.

[Rerouter]

Ok, Iq of the OPA189 would have it running a lot hotter so will give him a miss for now, at present the ADC could be dissipating about half a watt of heat, so I'll be trying to do some shuffling to keep components aligned to the gradients, such as R12, D1, D2 and D10, If they are oriented so there longest side is towards U4, it should remove any EMF there, R12 will be getting warm, the normal spec for an 0805 package is about 120C/W junction to board, so about a 5.4C rise, the diodes do not really generate any significant heat, its R12 that takes the brunt, I would assume a larger value for R12 would add too much noise?

[Kleinstein]

Under normal operation the voltage over R12 is not that large. Usually more like some 2-3 V_RMS. This would be some 2 mW. The high voltage would only be reached at the extreme input voltages. Even than the parts around R12 are not really temperature sensitive. R12 already has higher noise than the NE5534 and the OPA145 in the relevant 50 kHz range. Still this higher frequency noise is not yet critical - it will get important for short conversions like 1 ms. The diodes are also no more that temperature sensitive - if at all one could consider using other diodes than 1N4148 - ideally lower leakage, but still not very slow like many low leakage diodes (e.g. t_rr should be less than some 100 ns, but no need for the 4 ns of the 4148). The slight temperature effect (still more like slightly higher noise) was there with only 2 diodes or to high a value for R23.

I have not measured the total power consumption, but some 0.5 W is a reasonable number and not extra high. Still it depends on the OPs and the specs for some OPs (OP07 and NE5534) have quite some range for the current. If power is critical the OPA197 / OPA202 could be used instead of NE5534 / OP07. One could also run the µC with a slightly lower clock (e.g. 8 MHz, maybe 4 MHz).

There is limited use for an AZ OP for U11. It would help mainly with the non AZ mode. However zero drift is not only from the OP but there would be similar acting effects from leakage currents at the 4053 and drift of the resistors. A 1 ppm drift of the resistors R2,R3 would act like some 12 µV of offset. So even with the LT5400 arrays chances are the resistors would still give more drift than an OPA145. In normal auto-zero mode the offset is compensated by taking the difference. So OPs input bias, most resistor drift, leakage of the 4053, charge injection from the 4053 and similar contributions are corrected.
AZ OPs tend to have higher noise than the OPA145, the low voltage noise ones have quite some current noise.

With the final µC internal ADC reading at a fixed time, even quite some drift of the integrator would not cause a problem. In an earlier version I have tested a BJT based OP (TLE2021 with typical 25 nA bias) for U11, with no real problem. With just the classical comparator based rundown a high drift could causes a little of DNL error, as the time to stop varies.

[jaromir]

In schematics I noticed output of integrator being shielded. There is nothing wrong with it, but shielding/guarding the input of integrator (inverting inputs of U11, U2) makes more sense to me. Output of integrator has fairly low impedance, while input has much higher - so lower leakage and/or coupling can disturb the integration process. Leakages from DC nets will display mostly as offset, while dynamic leakages (control signals or integrator output) could induce INL or noise.
If you are going to shield/guard input of integrator, connect shielding/guarding to analog ground, the same potential as noninverting input of U11.

[Rerouter]

Integrator output was sheilded to ground to prevent it from injecting noise into other parts of the circuit.

The slope amplifier output was also considered and I may go back and sheild that aswell. As they can behave as antennas for the modulation frequency. however the slope amp output is already 20mm away from anything sensitive, So he should be fine without

The integrator input is guarded. To remove any risk of variable leakage. This connects to the non inverting of U11 as he is the precise one of the pair.  The input resistor connection to the mux may benifit from the same. But it was easier to just sheild all the digital and power supply connections to ground.

[jaromir]

OK, makes sense. I was confused by the schematics, your explanation makes it clear.

[Rerouter]

Checking over the input buffer heating, the main 2 parts that need to stay close to cancel out is the bootstrap op amp and Q4,

With a 25K input resistor they would then have a variance of 12mW, with 100K input resistors there is only a variance of 3.5mW,

I'll rearrange things so they are closer together and away from U12, this way we can call the input buffer about as thermally stable as it will get.

It is not the paired transistors vs the second op amp that make the difference, It is more that U12 has to source for positive voltages and sink for negative, with a current that depends on the input voltage
As such I'll nudge U12 around aswell to keep its inputs, and the input resistor as close as possible to being inline with the expected thermal gradient.

I would ask if there are any alternative picks for that OPA172 that may be a little lower supply power. e.g. the OPA171, it has higher noise, but for this case I do not know if that would matter. or is the bandwidth and slew rate critical.

Edit: Total system power consumption is not what I am chasing, more reducing the slope of any thermal gradients now that I have reached thermal emf considerations for layout.

[Kleinstein]

For the auxiliary OP an OPA171 might be Ok, it's just a little slower. I had problems with input current spikes and thus used the OPA172, as it's also a candidate for U2 and I had some at hand. A high slow rate is nice, but I don't really know how important.
Another lower power alternative would be OPA197. I don't think the constant power consumption background should be such a big deal, as it would only cause a constant temperature field. It's only the MUX that could be effected by a constant gradient and produce a small offset from this.
U12 current consumption and noise matter. The OPA145 looks like a good choice in this respect.

[Rerouter]

As you where saying R12 was a large noise source, could we flip the structure a little to reduce it furthur, e.g. relying on our own clipping schottkey diodes for the ADC and AIN, instead of having to use them on U4, or does this cause other issues I am missing,

[Kleinstein]

R12 contributes a little to the noise in reading the residual charge. However at 20 ms conversion and not too large an integration- cap the noise is not yet relevant. It only gets relevant for much shorter conversions (less than about 1 ms) and a little more gain before the µC internal ADC.
The noise from reading the residual charge the noise source are U11 with some 7 nV/sqrt(Hz), R12 (at 5K ) with some 9 nV, the NE5534 with some 4 nV+some 0.5 pA*5K = 2.5 nV. The relevant frequency range is about 50 Hz to 50KHz, so mainly the higher frequency part and not so much 1/f noise. The relatively slow ADC and thus reduced BW also has some good sides.
The shown alternative circuit with the clipping at the OPs output has about the same noise level, with a 5 K resistor in the feedback part.  The easy way to reduce the residual charge noise is to use a smaller integrator cap and faster modulation. The software side could still run a little faster. One could also still reduce the value of R12 a little more, so some 3 K if really needed.
In theory there is the option to use a resistor and 2 JFETs or 1 JFET and 2 resistors/2 diodes to do a kind of current limiting for R12. Noise wise it could help, but I don't thinks it is need and it many result in some gain drift with temperature.

For the 20 ms conversions the relevant noise is more like integrated low frequency noise (e.g. 25 Hz range), like from the resistors R1-R3, noise from U11 - this time with a noise gain of 2, the buffer.  For a 20 ms conversion this noise part is about 10 times higher than the residual charge noise.

[splin]

R12 will be getting warm, the normal spec for an 0805 package is about 120C/W junction to board, so about a 5.4C rise,

Acccording to this paper it's not that bad - 38C/W for an 0805 film to end cap  + a little bit for the solder joint to the PCB (an extra 1 C/W perhaps).

http://www.cetti.ro/v2/download/materiale_bibliografice/Thermal%20Management-SMD-Vishay.pdf

And this one suggests only 23C/W

https://www.vishay.com/docs/53048/pprachp.pdf

Quite a big difference between the two so no calculations to three decimal places please!

[EDIT] Of course you'll need sufficient copper and board area to avoid compromising those numbers significantly.

[Rerouter]

Another day another PCB re-arrangement, moved any variable heat loads away from the input resistor and adc as much as possible, means the ground run is a little longer, but grouped up all the quiet grounds and ran them as a nice 0.8mm thick trace back to the input plug.

Shifted the ADC around U4 a little to make things more ideal for the heat gradients it will be seeing. added some extra guarding because its not easy to shield the slope output and gave each input its own ground pin, The temp diode will end up close to the input array. and the gap on the top left will likely be where the heater dac footprint ends up,

[ali_asadzadeh]

Hi,
Would some one please brief me on the progress on this interesting thread?

[Kleinstein]

The new placement is odd: where is the µC supposed to be, especially when in the relatively large DIP case ? . The old placement looked more logical. If one insists in having the cental ground point at the connector, the connector should not be that far away from the areas where the ground is needed (the integrator and reference part).

The connection from the 4053 to the µC is quite a critical one, as there is quite a bit action.

With likely some space left for optional parts / extensions, it may be good to have some of the spare space more close to the MUX / input side, where some optional parts could be used (e.g. extra buffer/amplifier) before the MUX), possible buffer for the 7 V to the mux.

[jaromir]

ali_asadzadeh:

Both Kleinstein and I designed their versions of MS ADC; results are in two separate threads:
https://www.eevblog.com/forum/metrology/diy-6-5-digit-voltmeter/
https://www.eevblog.com/forum/metrology/diy-high-resolution-multi-slope-converter/
and now Rerouter is trying to redraw Kleinstein's version to KiCad.

Any particular detail you are interested in?

[Rerouter]

Kleinstein mentioned for his design he was suffering in small ways due to iterative changes in his design since he first laid it out, So I felt I would have a crack at it to nail down all the things one has to consider for an ADC of this resolution (not quite accuracy just yet, INL tests have not happened to my knowledge), So I'm refining it down into a Kicad PCB, If you want the design files, Just PM me. once it reaches a near completion state I was planning on just attaching to this thread,

Right now I'm trying to flip around the main analog chunks to make everything nice, with the least chance chance of non linear effects that may hurt its performance, and adding optional / alternative footprints and test points to make it easier to diagnose and expand on.

Placed in crude locations for the micro, UART header and where the power supply will likely end up, also left some room in the buffer area, Again its very easy to slide these blocks around, did not even use Undo from your post.

Edit: For the 7V buffer and secondary input buffer, what op amps would you suggest and I will add them to the schematic with some breakable jumpers (so if you dont use it, it is bridge by default)

Edit2: I can rotate that input mux and buffer stage so the ground is smaller, but that means moving a heat source closer to the input resistor, if that is fine I can pack that in closer.

[ali_asadzadeh]

jaromir Thanks for sharing, Big thumbs up

I wonder if there is good explanation on how the ADC works? Also How to add ohm and current measurements into the design?

[Kleinstein]

There is some description in the other thread on how the ADC work. However it is a bit scattered over several of my posts.

Adding resistance and current measurement is in principle no different than with other ADCs. With the ohms mode one could consider to measure the voltage over the DUT and reference resistor in series to the DUT separately. This would like the old Keithley 19x series DMMs. With not so good resistors at the ADC this could give better results, as it does not rely the gain stability.  Anyway a good voltage measurement and likely the current reading would need an additional amplifier before the MUX.
The MUX at the ADC is mainly meant to provide the AZ modulation for the ADC and gain correction back to the 7 V reference. In DMM, I would prefer to have a separate amplifier in front, as the fast 1 PLC mode causes quite some charge pulses to the inputs. So the MUX inputs are not really suitable for high impedance sources. Already at a few 100 K settling gets noticeably slow and it would need extra delays.

For a buffer to the 7 V reference the OP07 could be still acceptable, for higher performance one could consider something like OP177, OPA202, ADA4077 or maybe LTC2057 - they usually still use the same pin-out and no need to use the offset adjust pins.
For the input buffer (or possibly amplifier) the LTC2057 should be OK. There are not that many AZ OPs for 30 V supply to choose from and others like ADA4522, OPA188, OPA189, MCP6V51 have even higher current noise and input bias.  If the input current is a problem, one could consider compensation (e.g. with a photo-diode across the inputs).