Author Topic: Multislope Design  (Read 85602 times)

0 Members and 1 Guest are viewing this topic.

Online Kleinstein

  • Super Contributor
  • ***
  • Posts: 14475
  • Country: de
Re: Multislope Design
« Reply #50 on: February 10, 2018, 10:13:13 am »
Another update:
I got the multislope mode running - the main problem was a software error, that added noise noise during runup.
Considering the rather low reference voltage (around 3.5 V) and the not so perfect layout (breadboard) I am kind of surprised on how low the noise can get. Currently the standard deviation for a simulated AZ mode (taking the difference of 2 consecutive readings and thus the Allan variation for 1 time step) is around 2.4 µV with a full scale range of around 3 V.  So it is good for 6 digits resolution. The direct readings don't show much extra LF noise and drift.

Chances are it gets better with a larger reference voltage: the resistor noise should go down with the square root of the increase in voltage, the noise contribution (relative to the range) of the OP would even go down linear.

I think it is now really time to make a board. The breadboard experiment still let to a slight change in the circuit (slope amplifier relative to GND and level shifting only after that).
Any idea for test that should be done with the breadboard version, before making a board ?

I am still unsure about the reference: I tend towards having a separate low noise reference with the ADC. For the long term there might be a second reference later (e.g. LM399) that would be used for the scale adjustment. However I am not so sure about what reference to use:
The LM399 is rather noisy (thus the idea of an extra reference).
An LTZ1000 is kind of expensive.
3 or 4  LM329 in series (the higher voltage makes 1 resistor less relevant) might be an option, but they could have a significant TC.
For the compensated zeners like 1N821 the noise data are kind of confusing me.

Any other good ideas for the reference ?
 

Online Kleinstein

  • Super Contributor
  • ***
  • Posts: 14475
  • Country: de
Re: Multislope Design
« Reply #51 on: February 12, 2018, 05:50:36 pm »
Yet another update:

With a small change in circuit and maybe a contribution from SW (better adjustment of the internal ADC scale) I could reduce the noise even further, now at slightly below 1 µV for the difference of two consecutive conversions (to eliminate the 1/f noise, just like an AZ mode would do it).

The possible effect of the SW change make me think about a possible noise contribution: The ADC is kind of free running in a sense that the conversion start with a slightly different charge in the integrator ( the range covered by the µC internal ADC). This could be seen as a kind of natural dithering, when averaging more conversions for longer integration time. If there would be significant DNL errors, especially intervals too small this dithering effect would cause extra noise.  So using the argument the other way around, the relatively low noise - much of it can be accounted for - would also indicate that there should be no large DNL errors, at least not at the small range tested by the dithering.

Another result came from comparing two speeds of modulation during the run-up phase: There was very little difference in the noise. This means the switches (74HC4053) seem to contribute little to the noise - at least more frequent switching does not increase the noise. So chances are good one can get away with the 4053 switch (no need for ADG633 or max4053 - which seem to get hard to get anyway).  Also jitter seem to be not a serious problem with the AVR. So chances are that is could work without the extra flipflops for synchronization.

For the board it is now the question if low costs, low power, linearity or low noise would be more important ?
For the OPs I kind of have the problem that for testing a DIP form factor would be nice, but the good OP options for the most critical OP (OPA141 and ADA4077) are not available in DIP (at least not easy).
 

Offline chickenHeadKnob

  • Super Contributor
  • ***
  • Posts: 1059
  • Country: ca
Re: Multislope Design
« Reply #52 on: February 13, 2018, 03:21:58 am »
Yet another update:

For the board it is now the question if low costs, low power, linearity or low noise would be more important ?
For the OPs I kind of have the problem that for testing a DIP form factor would be nice, but the good OP options for the most critical OP (OPA141 and ADA4077) are not available in DIP (at least not easy).

This is the least of the problems listed, really its a non-problem. Simply order smt parts in soic packages and use dip adapter boards if you want to have a proto socket. They are not hard to solder. People should move to surface mount as it isn't that hard outside of BGA and WCLSP.

Soic to dip:https://www.ebay.ca/itm/20PCS-SOP8-SO8-SOIC8-TO-DIP8-Interposer-board-pcb-Board-Adapter-Plate/310575279861?hash=item484fbaaef5:g:0XkAAOSwtfhYqoh0

I vote for optimizing performance (linearity first then noise) other optimization can come after. Avidly watching your progress. cheers.
 

Online Kleinstein

  • Super Contributor
  • ***
  • Posts: 14475
  • Country: de
Re: Multislope Design
« Reply #53 on: February 13, 2018, 09:34:53 pm »
I did a test to see how much DA in the integration cap would influence the INL. As far as I understood it, one possible effect of DA would be an INL error, depending on how the run-up phase is working.  So see the effect I had the idea of comparing two slightly different runup version with the same HW in an alternativ fashion. So there is one conversion with a slow rundup (24 µs modulation period) and one conversion with a faster run-up modulation (8.2 µs). Ideally those two versions would give the same result - however due to a slightly different integration time the scales are off a little, but not much. The idea is to compare the two methods. To get a better scaling I used he difference of the readings as a function of the reading of the "slow" mode. The idea behind this is that I expected INL errors due to DA to have a different dependence on the voltage for the two modulation methods.

To get a stronger effect, I also tried this measurement with a higher DA polyseter cap instead of the polystyrene cap used for the other tests.
On the scope some fast DA effect is visible (however hard to trigger - so no photo).
For a large part the measured curve looks really smooth. However there is a small wiggle in the curve just at the point when the slow mode passed 50% PWM - thus showing the worst DA effect.  The worst case error is a little more than 0.5 units of the ADC, which corresponds to about 12 µV.  With a range of about +-3 V this would be a +- 4 ppm local INL error. This would be a good number for a using a poor quality cap. 

However now comes the odd thing:  when doing the test with the much better PS type cap, the errors seems to be a nearly perfect copy, despite of a much lower expected (and observed one the scope)  DA.  So the error seems to come from something else than DA in the integration cap. Now these 4 ppm error are kind of a bad thing - though only very local, just a 1 mV range. A more normal DNL test might miss this. It is nor just an external disturbance - the data are from three runs passing the critical range.

The other result from these runs is that the noise seems to be not much worse with the faster modulation. So the switch is not yet critical for the noise. There seem to be some drift between the two modes of measurement. As they use the same HW, this is likely due to a drift in the charge injection, that is about 3 times more important in the fast mode.

Attached are curve for the difference in measured voltage in 2 modulation modes. Units are cycles of positive ref. which correspond to about 22 µV each. The curves a taken with a PS and PET integration cap.
 

Offline floobydust

  • Super Contributor
  • ***
  • Posts: 7200
  • Country: ca
Re: Multislope Design
« Reply #54 on: February 14, 2018, 04:18:04 am »
I'm not sure at what voltage the kink in the ramp occurs or the present schematic, the parts and such but what came to my mind is cross-over distortion. Some op-amps have low output-stage bias current, almost Class B. Maybe try add a pullup or pulldown resistor to the op-amp's output, to force it more into Class A; only a few mA at most for low self-heating.

Most MCU's have a bit of clock-noise on their I/O pins, so I add 50-100R series resistors to roll off. Just don't want MHz getting into the analog section. The 4053 ABC control lines I would see as one path and add resistors there. I find ferrite beads only work if the impedances are similar i.e. 600Z ferrite bead does almost nothing into an op-amp's high-Z input, or a circuit section with high, say >10k impedance.

Audio Precision finding polystrene capacitors having less DA than mica parts. That surprised me, but that was at ppm levels.
 

Offline orin

  • Frequent Contributor
  • **
  • Posts: 445
  • Country: us
Re: Multislope Design
« Reply #55 on: February 14, 2018, 06:22:29 am »
Audio Precision finding polystrene capacitors having less DA than mica parts. That surprised me, but that was at ppm levels.


I thought mica didn't have particularly good DA, but I haven't tested one.  Teflon is an order of magnitude better than any other capacitor I've tested, polystyrene, polypropylene or NP0 ceramic - and I've looked - to replace the integration capacitor in my HP 3455A.  Some Russian teflon capacitors have been the best so far, but to get 80nF, they are _huge_.

One is best off designing the AtoD converter to maintain an average voltage of 0V on the integration capacitor - unlike the 3455A where you can get a 2 to 3 count error due to DA (particularly noticeable with auto-cal on).
 

Online Kleinstein

  • Super Contributor
  • ***
  • Posts: 14475
  • Country: de
Re: Multislope Design
« Reply #56 on: February 14, 2018, 03:43:04 pm »
I will likely use a polystyrene cap, as I have enough old ones to use. These caps are a few of the old parts that may actually be useful. Polystyrene caps are supposed to very good with DA, nearly as good as PTFE.  Mica is not good for DA, more like similar to mylar / PET film caps. The good thing about mica is the long term stability, but this is not an issue here. There is a small effect of the capacitance value (because of the ADC used for residual charge), but something like 1% drift is not a problem and it can be adjusted internally.  Anyway the test with the FKS type (PET) capacitor shows the ADC seems to be not that sensitive to DA. I had expected a much larger effect with some more ripples in the curve using the PET cap - but I could not see any extra errors. I can see the DA effect on the scope - right after the rundown, there is extra relaxation and it takes a few more 10's of µs for the voltage to settle. So maybe I did not see the DA effect as the waiting time before reading the value was long enough. The used SW version was not tuned for a fast rundown. So the good thing is that DA does not seem to be an issue, at least not from the rundown patterns. There might still be a longer time scale effect when switching between voltage levels.


Edit:  The test confirmed the capacitive coupling: it got worse with more wire at the sensitive nodes and got better (though not much) with some improvised shielding.
I think I have a good idea where that trouble might be coming from: There is likely some parasitic coupling from the output of the slope amplifier to the reference inputs to the 4053. If the zero crossings of the integrator get in sync with switching the reference (this is possible at the point where the wiggle is) the errors can add up over nearly 1000 switching events.  A test for this effect will be the next point.

I don't think the output stage of the OP is a problem. The OPA134 is an audio OP with a relatively high current consumption and likely an output stage with low corss-over distortion. In addition it is only the average current to cross zero, due to the modulation the current will be more like a square wave.
« Last Edit: February 14, 2018, 05:05:01 pm by Kleinstein »
 

Online Kleinstein

  • Super Contributor
  • ***
  • Posts: 14475
  • Country: de
Re: Multislope Design
« Reply #57 on: February 17, 2018, 08:53:59 pm »
Today I tried a classical INL test with using a floating reference. As a don't have a good stable reference, I tried it with 2 new alkaline cells.  Not to load the cells too much I added an OP07 as an input buffer. For the larger voltage range 2 green LED are use as a reference, and a slightly larger resistor for the signal input (around15 K for the input and 12.8 K for reference). So full scale is around 4.5 V for the slow modulation mode and around 4 V for the fast modulation mode.
 
It kind of worked, but there is quite a lot of drift, likely from the batteries. So the result is not really useful showing less than about 50 ppm INL in the 1.6 V + 1.6 V vs. 3.2 V test.  There is a chance the switch did some transient shorts to the batteries - like no reliable break before make  :-- .

However there where side result:
1) The green LEDs are a low noise reference:  noise on a short is around 1 µV eff, and with the 3.x V batteries around 1.3 µV. So the LEDs are at least low noise :-+, though quite some TC.

2) with a larger voltage there is some DA effect visible from the average voltage in the integration cap. So the MKT cap did not work anymore - it left the working range of the µC internal ADC. Even with the PS cap there is some relaxation after rundown visible, about proportional to the voltage, and smaller (about half the size) with the faster modulation.

3) with the stationary voltage the slow an fast modulation mode produce slightly different results: the fast mode gives about 12 ppm lower reading. Not sure if this is INL or just a slightly off scale factor. Ideally the scale factor should be the same as the integration time is now identical. Chances are DA is causing this and much of the effect could be linear.

The test on the breadboard uses just one zero crossing comparator and thus a larger DA effect is expected compared to the final version using FB with a look ahead contribution from the signal, like many HP DMMs use.

The noise in the fast modulation mode is significant (about 2.5 times) higher than with the slower modulation. In the initial tests I did not notice the difference, but this was with a slightly slower version and more background.  The much higher noise is kind off odd, as much of the noise in the slow more is expected to be due to the OP and thus only a small part due to switching. With the 3 times faster modulation  (123 kHz compared to 41 kHz) I have expected a little higher noise, but only a factor of 3  (or square root of 3) for only the small part related to switching. So maybe some pulses get to short for the breadboard version.
 

Offline branadic

  • Super Contributor
  • ***
  • Posts: 2411
  • Country: de
  • Sounds like noise
Re: Multislope Design
« Reply #58 on: February 17, 2018, 10:05:41 pm »
Why not skipping the breadboard and doing some free wiring on a copper clad board? This way you can avoid the parasitics and learn about the critical points within the circuit. Thus you learn what to look for when laying out a printed circuit board.

-branadic-
Computers exist to solve problems that we wouldn't have without them. AI exists to answer questions, we wouldn't ask without it.
 

Offline David Hess

  • Super Contributor
  • ***
  • Posts: 16898
  • Country: us
  • DavidH
Re: Multislope Design
« Reply #59 on: February 18, 2018, 07:23:24 pm »
I wonder if an extra low input bias current integrator would allow using a length of Teflon coaxial cable as an integration capacitor.  RG-178 is 29 picofarads per foot so probably not less expensive than an actual Teflon capacitor.
« Last Edit: February 19, 2018, 12:46:12 am by David Hess »
 

Online Kleinstein

  • Super Contributor
  • ***
  • Posts: 14475
  • Country: de
Re: Multislope Design
« Reply #60 on: February 18, 2018, 08:50:09 pm »
One might use a coax cable as a capacitor, but depending on the design of the integrator the needed cap is in the 0.5 to maybe 2 nF range. Thus this would be 5 to 20 meters.  So I don't think it is worth it.

As far as I can see the DA of the capacitor is not such a big problem. PTFE caps are supposed to be not that much better with DA than PS caps. Polystyrene caps are a little difficult to get, but not that much - at least in Germany one can still order them at something like 40 cents.  One problem with DA is that good specs are rare and DA is more than just one number, it also has a time dependence. There are also options to reduce the DA effect with a better feedback during run-up. Currently I have the very simple version with just the zero crossing comparator, which is known to be not that good. I had paned at least to use a second comparator with a mixture of the input signal - this would especially reduce the slow DA effect due to the average voltage during run-up. The next better step would be using a kind of fast, low resolution ADC to get a little more info for a better runup - accuracy would not be critical already 2 or 3 comparators could give better zero finding.
The other way to fight DA is using a fast modulation - however this makes coupling (see below) more critical.

The more tricky part so far is more like  (capacitive and via supply)  coupling from the slope amplifier, comparator and digital control lines to the integrator and reference current sources. With a little shielding it is visible on the breadboard, but not that bad anymore. I would expect only that one point with a 50% PWM during run-up to be really critical - that would be a rather narrow known range (around 0.1% of the range). A few other points are just visible for the breadboard version, but I doubt is would be with a reasonable layout.

Currently I am surprised how good the slower mode works, the faster modulation mode still has some odd points, like working most of the times, but something like one out of 10 readings (not a constant frequency) is off by about 2 ppm in addition to the normal noise. Without those out-layers the noise looks similar. So chances are the switches and digital jitter is not a problem.
 

Offline orin

  • Frequent Contributor
  • **
  • Posts: 445
  • Country: us
Re: Multislope Design
« Reply #61 on: February 19, 2018, 12:44:17 am »
PTFE was definitely better in my tests.  I posted the graphs I got from Bob Pease's DA test circuit here:

https://www.eevblog.com/forum/testgear/hp-3455a-last-digit-jitter-in-hi-res-auto-cal-mode/msg967855/#msg967855

And from later in that thread (my/original capacitor refer to the integration capacitor from my 3455A):

Quote
Now, as far as absorption is concerned, my capacitor is about the same as a good regular polypropylene capacitor.  I did't post the picture, but a pair of WIMA MKP 4 capacitors (33 and 47nF in parallel, http://www.wima.com/EN/mkp4.htm) gave a similar curve to the original capacitor and an 80nF polystyrene capacitor was a little worse.

The MKP capacitor datasheet claimed low DA.

I was running my test with Pease's circuit running with a frequency and duty cycle similar to what the 3455A AtoD converter uses, so it's possible that the teflon cap isn't so much better at a different frequency/duty cycle.

 

Offline David Hess

  • Super Contributor
  • ***
  • Posts: 16898
  • Country: us
  • DavidH
Re: Multislope Design
« Reply #62 on: February 19, 2018, 12:51:16 am »
I always found that qualifying capacitors yielded quite a variation in dielectric absorption and leakage between different types naturally but also between lots of the same capacitor.  I never had Teflon capacitors to test though.

Polystyrene has an annoyingly low maximum temperature.
 

Online Kleinstein

  • Super Contributor
  • ***
  • Posts: 14475
  • Country: de
Re: Multislope Design
« Reply #63 on: February 19, 2018, 06:05:59 pm »
Especially at the low end DA can vary between caps. One factor might be humidity inside the cap. So far I am quite happy with the PS cap. I can see a slight effect of DA even with the low DA PS capacitor, but so far it is more like a small effect and I don't see a really viable option for a lower DA cap than the PS ones.  If I really look fine at the data one can see some "drift" / relaxation after the rundown phase, that is slightly different depending on the runup phase (likely the last pattern) - but so far this is in the 10 ppb range. So this would be something to correct if more than 8 digits are called for.

For the ADC it is more about keeping the charge small, so that less DA can build up.  Worst case I would consider numerical correction of the effect of the last pattern.
 

Offline branadic

  • Super Contributor
  • ***
  • Posts: 2411
  • Country: de
  • Sounds like noise
Re: Multislope Design
« Reply #64 on: February 19, 2018, 06:55:37 pm »
Have you tried compensating dieelctric absorption as shown in "Understand capacitor soakage to optimize analog systems"



-branadic-
Computers exist to solve problems that we wouldn't have without them. AI exists to answer questions, we wouldn't ask without it.
 
The following users thanked this post: Kalvin

Online Kleinstein

  • Super Contributor
  • ***
  • Posts: 14475
  • Country: de
Re: Multislope Design
« Reply #65 on: February 19, 2018, 10:59:42 pm »
I have not tried the DA compensation and will likely not use analog compensation anyway. So far DA is visible, but it is not clear if it will really cause severe INL problems. Chances are that most of the effect of DA will be a slightly modified scale factor and thus not a real issue.  As far as I see there are three parts of DA  effecting the ADC: one is kind of the slow part that comes from the average voltage during one conversion. This to a large part would give a scale error and maybe some after effect when changing between voltages. Here the first step is to make this voltage small, by using a second comparator for the run-up. I am not so sure how good it works, but this should give a pretty good reduction.

The second part would be the change in average charge with feedback pattern. Depending on the voltage the average charge will change a little. Here it helps to make the feedback faster and maybe use a better feedback algorithm, e.g. by using more than one comparator or maybe even an ADC during run-up. I might try 2 comparators later as a kind of 1.5 bit flash ADC.  I did a crude initial test for this effect by comparing the two run-up modes (see earlier post). To my surprise the difference was pretty constant over most of the range, even with a mylar cap. I would expect this DA contribution to change with feedback mode and thus should show up in the difference between the two modes.

The faster mode still shows some odd extra noise (those 10% of points that are off), that i don't understand. This kind of makes the comparison more difficult. In addition there is some drift between the two mode - likely due to charge injection changing with temperature or supply voltage. So I may have to repeat the comparison with two intentionally slower modes - so less background and more DA effects expected.

Finally there is an effect from the very last part of the feedback pattern. It looks like that the very last part of the run-up phase has a minute effect. I read the residual charge after rundown twice with some 100 µs in between and for this time a change in voltage by about 1-4 ADC steps or about 20-80 µV for the capacitor is visible, depending on the run-up pattern, likely from a change in the last part, as i only saw like 2 cases. As the 100 µs waiting time is already more than the runup step size, I would not expect much more change with longer waiting. These 1-4 ADC steps are not very much (still well below noise for the 20 ms conversion) and may be better corrected numerical than in analog HW.
I guess I should somehow record the last part the the feedback for debugging.

DA might be one of the effects limiting the linearity. So it is kind of important. The best choice of modulation frequency depends on the DA and this way it effects the speed needed for the integrator and µC. The current tests are still a bit slower than the HP34401 design.. The 34401 design for some reason uses a very fast modulation and limits the useful range - likely to make this work with the slow integrator. I am not sure the high modulation frequency is because of DA, it could also  be because of the ADC used to measure the residual charge without a rundown.

So despite the possibly fast integrator (higher BW OPs) I would not go for such a fast modulation, unless there really is a problem with DA. I would more like hope to improve on the feedback mode to keep the charge small.  As I don't care very much about the fast conversion modes like < 1 ms, I also don't care very much about the slightly faster rundown that is possible with less charge to start with. For a 20 ms conversion I think some 120 µs for the rundown (without the second ADC conversion currently used) should be fast enough, and some of this is avoidable by reducing the comparator overshoot and a faster µC clock.
 

Offline branadic

  • Super Contributor
  • ***
  • Posts: 2411
  • Country: de
  • Sounds like noise
Re: Multislope Design
« Reply #66 on: May 13, 2018, 07:32:50 pm »
Any news on your topic?

-branadic-
Computers exist to solve problems that we wouldn't have without them. AI exists to answer questions, we wouldn't ask without it.
 

Online Kleinstein

  • Super Contributor
  • ***
  • Posts: 14475
  • Country: de
Re: Multislope Design
« Reply #67 on: May 13, 2018, 08:20:39 pm »
I am still at the project. I had a layout nearly ready - only to find out that I ignored a type of capacitive coupling and had about the worst possible layout for that. To reduce it I had to redo the layout more or less from start.

I am still little unsure about the reference - will use 3 LM329 (in series) for a first test.  I know the LM329 is not that great with TC and not the very lowest noise. It is still possible to use low noise zeners (e.g. 1N825) in the same layout.

With a little luck I get a board ready this week.
 

Offline iMo

  • Super Contributor
  • ***
  • Posts: 4896
  • Country: vc
Re: Multislope Design
« Reply #68 on: July 07, 2018, 09:03:36 am »
@Kleinstein: any new results with your design?
 

Offline new299Topic starter

  • Regular Contributor
  • *
  • Posts: 119
Re: Multislope Design
« Reply #69 on: December 26, 2018, 09:18:10 am »
Hi,

I've restarted work on my design. I have my board working in a basic dual slope configuration currently, and am slowly working my way through various issues. You can find my notes here:

http://41j.com/blog/2018/12/multislope-adc-bring-up-dual-slope/

I'm currently trying to understand why I'm seeing such a big difference between the positive and negative slope speed. Thoughts and suggestions on how I should proceed in testing/evaluating issues are most welcome.
 
The following users thanked this post: iMo

Online Kleinstein

  • Super Contributor
  • ***
  • Posts: 14475
  • Country: de
Re: Multislope Design
« Reply #70 on: December 26, 2018, 10:13:39 am »
The board looks nice - my design is still on the breadboard and using a low supply.

For the circuit I am surprised not to see diodes in the output amplifier to limit the output amplitude. The AVR usually does not like a full +-10 V signal at the comparator. The normal way is to have 2 antiparallel diodes parallel to the feedback resistor. This works even better of the amplifier at the output is inverting.

For the different gains in positive an negative direction I have no good idea. However I am a little surprised with the code. With ARUDINO C++ / C code it would be difficult to get an accurate timing. At least there are chances that delay may change a little if the compiler version changes, as the same C code not always gives the same machine code output.  So it might help to at least have the conversion part in ASM. However this can not explain the rather large difference positive to negative. The separate codes for positive and negative direction cause some discontinuity at zero, just near the zero readings from an AZ mode.

For high resolution it is normally a good idea to do the final integration from one direction only. This avoids different scale factors and an delay / offset of the comparator and slope amplifier would only add an offset.
The way I do it is the following: first always integrate up (at least 1-2µs, until the right sign is reached), than down til zero crossing and than slow up. So it is always the same sequence, just different times. One no longer needs a slow down unless one wants an additional very slow down as a last step.

Of cause one would still need to solve the different slope problem - not sure if this is more like a hardware problem or a software one. One could check the timing in the simulator.

To get the exact ratio of the up and down slope it could be a good idea to use the ADC circuit to also measure the ratio (e.g. in a special test mode).
 
The following users thanked this post: new299

Offline new299Topic starter

  • Regular Contributor
  • *
  • Posts: 119
Re: Multislope Design
« Reply #71 on: December 26, 2018, 01:35:10 pm »
For the circuit I am surprised not to see diodes in the output amplifier to limit the output amplitude. The AVR usually does not like a full +-10 V signal at the comparator.

No, it doesn't like it. I have a couple of dead Arduinos now. :) I'm currently using fractional gain on the output amplifier. I think I might want to move to a bipolar external ADC at some point. It might be useful for debugging if nothing else.

However I am a little surprised with the code. With ARUDINO C++ / C code it would be difficult to get an accurate timing. At least there are chances that delay may change a little if the compiler version changes, as the same C code not always gives the same machine code output.  So it might help to at least have the conversion part in ASM.

I agree. From previously experience, the overhead of even digitalWrite's is reasonably high, so the timing will not be accurate (but should be consistent I think). I will need to rewrite this.

However this can not explain the rather large difference positive to negative. The separate codes for positive and negative direction cause some discontinuity at zero, just near the zero readings from an AZ mode.

I cleaned the board in an ultrasonic cleaner, and then sat it in IPA for 30mins under agitation. This seems to have almost completed cleared up the slope differences. The flux I like (AMTECH NC-559-V2-TF) seems relatively low resistance. I previously had issues on this board with residual flux under the switches throwing measurements off as well. I wonder if I quit using this flux on these kinds of boards...

Anyway the current measurements as attached (and I've updated the blog post).
 

Online Kleinstein

  • Super Contributor
  • ***
  • Posts: 14475
  • Country: de
Re: Multislope Design
« Reply #72 on: December 26, 2018, 02:48:05 pm »
For the signal send to the comparator one can relatively easy limit the signal in an inverting amplifier: just have two additional diodes back to back in in the feedback. This way the output is between some -0.8 and +0.8 V, still with a steep slope around the zero crossing. With a simple divider towards 5 V (e.g. 5 K and 22 K) the signal would be in a range suitable for the arduino internal comparator.  This is the way I use it.  An alternative would be using an external comparator (e.g. LM311).

For debugging I prefer the scope over reading with the µC. Though reading with the µC internal ADC can also help. Here a divider can help to bring the signal in the right range and avoid damaging the µC.

Even under the arduino environment one can directly write to the IO ports to avoid the extra delay from digitalWrite. For the beginning it is not that bad, as it only adds a fixed time delay - though at least consistent with the same program. The extra delay makes the use of the slow slope a little more difficult, as the added delay means there would be quite some time for the slow slope to make up the delay. So the slow slope should not be that much slower (maybe around a factor of 10). Still if there are some 5 µs lost in the reaction time this would be some 50 µs lost to make it up at -1/10 the slope.

For the program the possibly tricky part can be that  "IF (x ==0)"  and "IF (x > 0)"  may take a different time. Also for 16 bit numbers some operations may take a different time depending on the value. Getting code with a well defined run time is one of the few cases where assembler programming has a real advantage - in C one would at least need lots of testing (e.g. in the simulator) on the actual timing. For a first low speed, less accurate version it may still work in C.

If possible I would such an conductive flux for sensitive parts.
 
The following users thanked this post: new299

Offline new299Topic starter

  • Regular Contributor
  • *
  • Posts: 119
Re: Multislope Design
« Reply #73 on: January 02, 2019, 01:32:42 pm »
Small update. I attempted to rebuild the board using all ADG1419s. This did not work well. After reset the integration capacitor had a tendency to swing negative. Before (very slowly over 60s as before) drifting back to a positive value. I put this down to higher charge injection, does this seem correct?

The ADG1419 datasheet does not list charge injection. Can this be calculated from other parameters? The Vishay, and Maxim DG419s do, as do some other Analog parts. This leads me to believe that charge injection may not be well controlled in the ADG1419, and it might not be an ideal part for my application.

I'm thinking about building a board, just for measuring charge injection to test various parts and improve my understanding.
 

Online Kleinstein

  • Super Contributor
  • ***
  • Posts: 14475
  • Country: de
Re: Multislope Design
« Reply #74 on: January 02, 2019, 02:28:33 pm »
For switching at the integrator the CMOS switches should not be very low resistance. So the ADG1419 are not a good choice. Usually charge injection goes up about like 1/R at a given voltage rating. So a high charge injection is very likely. The charge injection depends on the voltage level at the switch and the value near ground is close to optimum.

I use just simple 74HC4053 - except for missing tight the leakage specs they are quite suitable.  They are reasonable fast and thus suggest good jitter specs and 3 switches in a case is very convenient to the 3 main paths trough 1 chip.  I consider the on resistance about the right value. 
For leakage one might need to check before use and maybe select a good one - the typical specs are OK, it is just that they don't test them very much for such a cheap part.  I get a net charge injection for an ON/OF cycle of about 1 pC.

AFAIK the Fluke 8846 DMM also use HC4053.
 


Share me

Digg  Facebook  SlashDot  Delicious  Technorati  Twitter  Google  Yahoo
Smf