NEC μPC811µPC811 is a unique J-FET input operational amplifier that uses a high-speed PNP transistor (fT = 300 MHz) for the output stage to achieve fast response and high stability.
An opamp designed by NEC in the '80s and apparently still made by Renesas, offering "high input impedance, low offset voltage, high slew rate and stable AC operating characteristics", including ability to drive 10nF load. Offset voltage trimmed to 2.5mV max at 25°C, noise and speed similar to TL081, more input leakage. Decompensated version is available as μPC813 with same DC precision and noise, but 50% higher speed and limited capacitive load tolerance at unity gain. Corresponding duals are μPC812 and μPC814.
I got an old production NEC-branded chip from AliExpress, probably recycled, here's what it looks like (alongside μPC4570) if somebody is interested. NEC's font is quite unique, the μP prefix is omitted, bottom row seems to contain usual YYWW date codes.
Simplified schematic shows two stage topology similar to TL081.
Real circuit is slightly more complex than common JFET opamps. At the top, between pads 1 and 7 (labeled for our convenience) the trim circuitry is located. A current proportional to input stage bias passes through JFETs near pad 7 (not sure why) and reaches an array of JFETs of different sizes on the left. Their gate is biased through a diode-wired JFET, probably to prevent current backflow during zapping. Zener zaps collect current from selected JFETs to a trace which leads it back near pad 7 where it can be zapped into either pad 1 or pad 5 (offset null). Current from "unzapped" branches is absorbed by PNP emitter followers with bases grounded through some structure which may be a tiny JFET, this probably limits PNP base current during zapping. Contrary to the schematic, mirror resistors (located between IN pads on the left) are not adjustable.
The input stage is a JFET differential pair in usual four-transistor common centroid layout, loaded with an NPN current mirror to the left, also common centroid. An emitter follower analogous to Q5 drives the mirror like in TL081, but unlike TL081 both followers have active emitter loads instead of resistors. The mirror driver is bypassed at high frequencies by junction capacitor integrated between base and collector of one of the mirror NPNs.
The output stage is at the bottom, with PNP on the left, NPN on the right and resistors between them. Resistance is probably low to keep time constant with reactive loads under control, so active overcurrent protection for sourcing and sinking is used like in 741. Located nearby is the compensation capacitor and Q6 with its Baker clamp (not shown on the schematic).
The rest is bias generation, active loads, etc. Bias is derived from a zener reference and resistors, the input stage current source is a Wilson mirror for better CMRR.
Looking at a transistor near the output stage we can see usual surface distortion due to buried diffusion under the transistor (green arrows), as usual shifted slightly away from the true location of the buried diffusion (aligned with active part of the transistor). But we also see another buried diffusion (yellow arrows) surrounding the transistor, as well as other transistors. This may be buried isolation, applied in the same places as the usual (surface) isolation. Such technique was sometimes used to reduce diffusion time (each diffusion only needs to penetrate half of epitaxial layer thickness until they meet) and therefore horizontal spread of isolation diffusions, which enables tighter packing of transistors.
The "unique" output PNP appears to use construction with substrate collector, ground connections are made to isolations on its sides. No "hole" in buried isolation is visible here, so the diffusion may be present under the PNP to reduce its base thickness. The color of the PNP is slightly different than other transistors and it has a narrow "frame" of yet another color, which shows that some diffusions have been applied on the surface to fabricate this structure. It appears that the process can produce a somewhat decent vertical PNP, but only with collector fixed at ground. Other PNPs in the circuit need freely usable collectors and have conventional lateral construction, so this is not a fully complementary process.
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