Optimizing efficiency of SEPIC DCDC prototype.

[Psi]

Hi,
The files included below are my alpha prototype build for a new charger using SEPIC design with current regulation
(10.5-30V input / 13V output / 2A current regulation)

I've assembled the prototype and done a little testing.  I still have some tuning to do with the feedback loops, but the reason for this post is to ask where I'm losing most of my efficiency and why? Currently the efficiency is ~78% and I'd like it to be 85% or better. (The chip should be capable of over 94% see Fig 10-2 on page 30)
From using the thermal camera I can see the primary source of lost heat is the switching mosfet (70degC). So starting here seems like the best plan.
The inductors and diodes are around 40C so are less of a concern.

I know that the mosfet i'm currently using is way overkill, it was just something i had laying around from another project.
But the Rds-on is 1.1milli ohms, so the loss is not from Rds. Maybe the on/off time is too slow?  I dunno?

Any ideas, tips, or comments?

I know about the losses in the input polarity diode and the option of changing this to a mosfet.

(Note the schematic shown below is missing the mosfet for reverse battery on output protection, but i have bypassed that feature on PCB for now, so it doesn't matter)

Mosfet
https://nz.mouser.com/datasheet/2/916/PSMN1R0-40YLD-1320666.pdf

Diode
https://nz.mouser.com/datasheet/2/916/PMEG060V100EPD-1599823.pdf

Chip
https://www.ti.com/lit/gpn/lm5156h

Inductor
https://nz.mouser.com/datasheet/2/390/104CDMCCDS-786161.pdf

[filssavi]

Your hunch is correct, that MOSFET is way to big for that converter, while you will not have any on state loss to speak off, however it is so big that it is far too slow (at least an order of magnitude) to run anywhere near what you should run such a converter, giving you horrific switching losses, (cross conduction, output capacitance and reverse recovery)

You have 2 options

- Change to a faster mosfet ( with 10-50 times the on state resistance)
- drop the switching frequency as low as it will go and then some (that transistor is likely designed to work in the ten to one hundred kHZ range, not much more)

[jonpaul]

Agree on FET sizing, the gate C rises and may load the driver. The ESR of the cap and the losses of the inductor may cause some losses.   



Use your finger: Touch the MOSFET, inductor and series cap C5 after a long max load run.

Jon

[filssavi]

The mosfet is turning on slowly also because the gate drive current of the IC is way to little for something with an  8.8 nF capacitance. To get even close to datasheet figures, which are not that good BTW for a low voltage MOS, (it is normal since this is optimised for very high current) you will need at least 4/5 A of drive current (it is a guess, but you can calculate the value easily from gate charge, voltage swing and time)

But even if you achieve datasheet rise and fall times, do not expect great efficiency as the mosfet is still far to big for that application

[T3sl4co1l]

Why not coupled inductors?  They're readily available in this rating.

The switching loop is... all over the place?  Put the MOSFET, coupling cap, diode and output cap all right next to each other!  Likewise, the input should be bypassed near the inductor (but this is a lower priority, as the inductor current is triangular, not square; basically the trace length from inductor to filter/bypass cap acts in series with it, so has little effect on circuit operation, but mind the voltage drop if you connect anything else along that path!).

Definitely, that MOSFET is fuckoff massive, like, even a '3055 would do here I think?

(Cute sidenote: NTF3055, MTP3055, etc. are MOSFETs, bearing no relation to the 2N or TIP3055 -- though they seem to have similarly enduring popularity and genericity!)

Tim

[Psi]

Thanks T3sl4co1l , filssavi, jonpaul

Yep, mosfet replacement is first thing i will look at.
Need to order something specific for this project.

The reason I didn't go with coupled inductors was market supply.
Since they're a more specialized part I was worried they might be harder to get in the current market and more likely to go out of stock randomly. But I will have another look.

Yep, will tighten up the loop size for next PCB. Will be easier to do if i can use a coupled inductor.

[Psi]

Finally had time to replace the mosfet with something more reasonable.
https://www.infineon.com/dgdl/Infineon-IAUC28N08S5L230-DataSheet-v01_00-EN.pdf?fileId=5546d4626f1cf1c5016f1dd9c8340050

The FET temp dropped from 70C to 53C   (diode at 55C)
Which is more reasonable.

Just before FET change
IN 12.1V  1.95A 23.6W 
OUT 12.83V  1.33A 17W
=  72%

After FET change
IN 12.0V  1.72A 20.64W
OUT 12.84V 1.22A 15.66W
=  75%

So a little efficiency improvement, but not a huge amount.
(Although the circuit performed a bit different (current wise) with same input and load specs using new FET. So the numbers aren't totally comparable)

I'm thinking maybe it's just the switching loop in the PCB layout that needs to be much more tight?

How tight does the loop need to be? It seems a bit hard to get a really tight loop when using two inductors.
I really don't want to use one coupled inductor due to parts shortages.  Generic inductors will be a lot easier to source.

[trobbins]

Can you access other FET options and swap them for comparison?  You may identify a loss minima as FET gate charge is reduced whilst Rdson increases.  After that you can look at subtler aspects - do you have other options for the inductors?  Can you place some parts on the other side of the pcb, such as some bypass caps - that may allow you to clean up the layout?

[Psi]

The other side of the PCB has at most 4.3mm of clearance to case. So it would be tricky but not impossible if I can find a low profile inductor.
Will have a look.

[trobbins]

Rear side for key caps may provide much shorter transient current loops to benefit high current switching noise and control signal integrity, and not be a height risk.  Inductor placement on rear could be a risk for swapout to alternatives, and closeness to metal plates.