PCB 2 layer plane design

[pyrohaz]

Hi All,

I'm designing a PCB based around one of the standard LQFP32 STM32F0 IC's. I've got all of the decoupling capacitors near for low impedance power supplies etc. Infact, I've designed multiple PCB's using the STM32F0 series of chips and all have worked successfully so I'm not doubting my design ability. I'm mere asking here so I can hopefully improve it!

All of my designs are on two layers so I don't get the luxury of having individual ground and power planes on the outer layers of a 4 layer PCB. I use Eagle for my PCB design and can make ground plans using the polygon function (as I'm sure many of you know!). What I'm wondering is: What signal should I connect the top and bottom pours up to? I normally just connect them both to ground then scatter vias around the board to keep the impedance difference between the two planes low. My highest frequency signal is 24MHz SPI with a trace length of ~3cm. Are there any advantages to having one ground and one V+? I can imagine that this makes a relatively low values capacitor with the FR4 PCB as the dielectric. My whole board is 49x35mm with a PCB thickness of 0.8mm. This equals a capacitance (between V+ and Gnd if each plane is different and occupies the whole PCB - which it doesn't) of 83pF so I don't really see the massive advantages here?

Any info is welcome!
Harris

[Precipice]

I'd flood both layers with ground, and route power (with well placed decouplers next to IC pins) on tracks.
As you say, there's no worthwhile capacitance to be had from the inter-plane gap. Your mission is to keep a stable ground reference. Local decouplers keep the high frequency loops nice and small.

(Unless you're etching your own boards, or have rather more time than money, I suspect that 2-layer boards are making less and less sense. Elecrow want $24 (plus $5 postage to the UK) for 10-off 5x5cm 4-layer boards. Unless I need boards on a super-fast turn (hence local, hence 2-layer is cheaper), or bigger than this, I just knock stuff out on 4-layer and do something else until they arrive).

[pyrohaz]

My highest frequency signal is 24MHz SPI with a trace length of ~3cm.

I doubt that. Your highest frequency is determined by the signal's risetime and falltime, not the clock frequency.

Have a look at
http://www.edn.com/design/pc-board/4422579/PCB-design-course---checklist
Search for application notes etc that reference these books "High-Speed Signal Propagation: Advanced Black Magic" by Howard W. Johnson, "High Speed Digital Design: A Handbook of Black Magic" by Johnson, Howard, Graham, Martin

Thats very true! I failed to see that, isn't it normally up to the 5th harmonic IIRC? Meaning I'm looking at ~120MHz. Thats a really good EDN article actually.

I'd flood both layers with ground, and route power (with well placed decouplers next to IC pins) on tracks.
As you say, there's no worthwhile capacitance to be had from the inter-plane gap. Your mission is to keep a stable ground reference. Local decouplers keep the high frequency loops nice and small.

(Unless you're etching your own boards, or have rather more time than money, I suspect that 2-layer boards are making less and less sense. Elecrow want $24 (plus $5 postage to the UK) for 10-off 5x5cm 4-layer boards. Unless I need boards on a super-fast turn (hence local, hence 2-layer is cheaper), or bigger than this, I just knock stuff out on 4-layer and do something else until they arrive).

I don't etch my own board and I pretty much have more time than money  so I've not really made the move to 4 layers as of yet. I buy my PCB's from ITead Studio and while they offer 4 layers, its generally a fair bit more expensive than a standard 2 layer board. I've never designed a 4 layer PCB either and don't as of yet see my personal need, I don't feel limited with 2 layers, put it that way! What are the major advantages for relatively low speed electronics with 4 layers vs 2 layers?

[pyrohaz]

My highest frequency signal is 24MHz SPI with a trace length of ~3cm.

I doubt that. Your highest frequency is determined by the signal's risetime and falltime, not the clock frequency.

Have a look at
http://www.edn.com/design/pc-board/4422579/PCB-design-course---checklist
Search for application notes etc that reference these books "High-Speed Signal Propagation: Advanced Black Magic" by Howard W. Johnson, "High Speed Digital Design: A Handbook of Black Magic" by Johnson, Howard, Graham, Martin

Thats very true! I failed to see that, isn't it normally up to the 5th harmonic IIRC? Meaning I'm looking at ~120MHz. Thats a really good EDN article actually.

Not necessarily: it depends on the risetime and falltime of the signal - and that would be the same for a 24Hz (no M, no k) signal. The determining factor is the logic family and the loading.

Alternatively, consider that the relationship between a scope's bandwidth and risetime is t_rise/fall = 0.35/bandwidth. That presumes a linear-phase front end filter which wouldn't be the same for logic circuit, but it is a starting point.

You will need to understand what constitutes a "short" PCB trace that doesn't have to be impedance controlled. I suggest you read up about signal integrity; Johnson's books are a good starting point. There are plenty of applicaton notes around on the web, often relating to ECL (or LVDS) technology since the physics hasn't changed in the past 30 years!

 Johnson's blog is at http://www.edn.com/electronics-blogs/4238443/Signal-Integrity but he has now retired.

Its funny you mention Signal Integrity, that was the main aim of my summer placement this year! Though it was dealing with LVDS as opposed to the single ended SPI that I'm using here.

I remember reading that you need to start looking at trace impedance at 1/7 the wavelength of the signal under test, is this a correct value? Going off which, using the 120MHz as my signal frequency (5th harmonic of 24MHz), and EM speed through copper and FR4 being 2/3c, 1/7 the wavelength is equal to a distance of 238cm. My trace length is 28mm which is ~2 magnitudes smaller, that was my definition of short. I'm actually driving an LCD here though I don't know of any internal termination. As far as I know, the STM32F0 series has standard CMOS outputs with software controllable slew rate. Not here, I'm not actually experiencing any problems and I always put extra effort into keeping the trace length of the clock and data as close to each other as I can.

That is a really good read though! With respect to your 0.35/BW value, turning that on its head to get a relative frequency with respect to the rise time, should I be looking at my fundamental freuency multiplied by 2.85 (1/0.35) as opposed to 5?

Thanks a lot!

[pyrohaz]

You have a 40ns period signal (24MHz), but is the risetime 20ns, 10ns, 5ns, 1ns, ... 0.1ns? I rather doubt either extreme   Once you have defined the risetime, not the period, then and only then will you be in a position to determine the max track length that doesn't need to be controlled impedance.

For example, if there is a 3.5ns risetime (a quite plausible value) then the length would be around 3.5 inches; speed of light is 1ns/ft in vacuo, 1ns/6" on PCB (approx to keep the arithmetic easy), so taking 1/6 (not 1/7) leads to the critical length being 1" per ns of risetime.

(And let's hope I got that arithmetic right!)

Hi tggzzz,

Thanks a lot for that! Its a really concise and simple explanation. So I understand about the propagation time of a signal through a trace and that's why I aim to keep the trace lengths as close as possible to eachother, this should hopefully avoid violation of setup and hold between the clock and data, am I right with this assumption?

How does the above then relate to track reflections and transmission line considerations?

Thanks,

[AlfBaz]

Here's a good free book on the subject at hand
http://www.thehighspeeddesignbook.com/

[salbayeng]

If you can set the risetime on the pins, then simply setting risetime larger than trace length will prevent reflections,  (tggzzz already said this), so set it to ~ 2ns, personally I wouldn't worry with SPI and only 30mm of track , if the tracks were a bit longer I might be tempted to add say a 47ohm damping resistor on each track.

You don't need a fancy groundplane arrangement ,  if you can get a good groundplane and decoupling around the CPU then keeping that groundplane going up to the peripherals is quite easy.

[free_electron]

Doublesided boards don't have planes. The distance between the floods is too large to enjoy the plane effect. Besided, p,anes only work when they are uninterrupted.

[Precipice]

Doublesided boards don't have planes. The distance between the floods is too large to enjoy the plane effect. Besided, p,anes only work when they are uninterrupted.

That's a bit black & white (bordering on wrong), imho. With care (especially in placement), you can do a decent plane on a 2-layer, until the board gets too full.
Here's one I prepared earlier...

[DanielS]

All of that is either wrong or too black-and-white. Having said that, breaks in a plane do significantly reduce its effectiveness - which can be beneficial in the right circumstances. See any discussion of mixed analogue/digital PCB design.

I would not call gapping a plane to isolate analog circuitry from switching noises "reducing its effectiveness" since the plane's effectiveness is not going to degrade much unless you put those split-planes and slots in the path of high-speed signals.

[free_electron]

Ah, youngsters!

All of that is either wrong or too black-and-white. Having said that, breaks in a plane do significantly reduce its effectiveness - which can be beneficial in the right circumstances. See any discussion of mixed analogue/digital PCB design.

on a standard 1.62 millimeter thickness board you don't have enough coupling between top and bottom to get any kind of useful plane effect. it's as simple as that.

A typical i/o drive impedance is in the order of 25 ohms. good luck routing such a trace on a 1.62 mm board. you'd need 400 mil wide traces.

[Precipice]

I far more commonly see (and use) launch resistors than receiver terminations.
Bear in mind that signal integrity is only one thing you're optimising for - EMC tends to be at least as important, and the combination of slowing the edges down and matching(ish) track impedance is handy.

[DanielS]

I far more commonly see (and use) launch resistors than receiver terminations.

In tons of high-speed ASICs, you see neither because they are integrated in the devices themselves and are often programmable to some extent.

[free_electron]

All of that is either wrong or too black-and-white. Having said that, breaks in a plane do significantly reduce its effectiveness - which can be beneficial in the right circumstances. See any discussion of mixed analogue/digital PCB design.

I would not call gapping a plane to isolate analog circuitry from switching noises "reducing its effectiveness" since the plane's effectiveness is not going to degrade much unless you put those split-planes and slots in the path of high-speed signals.

Er, that's precisely one reason when you would have a split plane, the other being if there is high currents that you don't want near sensitive analogue (or digital) electronics. In those circumstances you don't want a single ground plane.

Maybe I'm missing what you are trying to say.

Currents don't just flow at random through planes. The faster the edge rate the more they couple into the plane. If you take a single trace positioned above a reference plane and terminated with a load into the plane at far end and you track the return current flow you will see the electrons run pretty much in a straight line from termination point back to source for DC current. Increase the frequency and they will start to follow the shape of the source path. Even though there is a solid slab of copper, they will run in the path shaped by the sender.

To get this effect (called the plane effect) you need to be within 1.5 times the width of the trace . Any further than that and the effect decays exponentially. At 3 times the width the effect is gone.

That's why you cannot control return current on a doublesided board. The thickness of the material makes it so that you need traces that are 3mm or more wide to get the effect.
On multilayers you play with the prepreg thicknesses to control the coupling.
If you can couple a power and ground plane for the frequency band you work in then you can use either as an energy return plane. You need to be aware for plane edges though. These can radiate and even resonate. Plane edges should be shunted for AC using small bypass caps. A large plane with no load is effectively a dipole antenna.

[ludzinc]

To get this effect (called the plane effect) you need to be within 1.5 times the width of the trace . Any further than that and the effect decays exponentially. At 3 times the width the effect is gone.

That's why you cannot control return current on a doublesided board. The thickness of the material makes it so that you need traces that are 3mm or more wide to get the effect.

Oh wow.  That moment when you realise you've always been doing PCBs wrong....

I once fixed a problematic board by running a TCW wire (grounded) in parallel above the signal line of interest even though there was a ground plane 'right below it'.  Now that I know that 1.6mm is too far away, this kludge finally make sense. 

[T3sl4co1l]

Currents don't just flow at random through planes. The faster the edge rate the more they couple into the plane.

Not sure how you'd come to such an observation; a trace of fixed geometry and variable length will "couple" (i.e., behave predominantly as a transmission line) for any length on par with the electrical length (i.e., wavelength) at the frequency of interest.  Regarding edges, that's roughly to do with rise time, rather than wavelength.

If you take a single trace positioned above a reference plane and terminated with a load into the plane at far end and you track the return current flow you will see the electrons run pretty much in a straight line from termination point back to source for DC current. Increase the frequency and they will start to follow the shape of the source path. Even though there is a solid slab of copper, they will run in the path shaped by the sender.

To get this effect (called the plane effect) you need to be within 1.5 times the width of the trace . Any further than that and the effect decays exponentially. At 3 times the width the effect is gone.

The "path of least impedance" effect has to do with the trace length compared to the electrical length (wavelength), and not the trace width, nor some absolute length scale.

For a circuitous path with line-of-sight L_0 and path length L_1, the cutoff from "DC" (line of sight, 'path of least resistance') will occur on par with wavelength ~= L_1 (I think).

The image current, reflected by a trace on the opposite side, will tend to be wider than the trace by a few times (as stated).

This sounds like a mistake, that you meant to say one thing and wrote another.  The dimensions of the image current is more or less true.  The path with respect to frequency was stated in terms of height above the ground plane, which is unrelated, or only very mildly so.  It depends on the path, of course.  So maybe you meant that.  Dunno.

That's why you cannot control return current on a doublesided board. The thickness of the material makes it so that you need traces that are 3mm or more wide to get the effect.

That sounds like more than enough to allow routing like signals together (e.g., differential pairs), and orders of magnitude sufficient to, say, build a dirty digital circuit on one side of the board, and a quiet analog circuit on the opposite side (say 10 * 3mm away).  Without cutting the ground plane.

On multilayers you play with the prepreg thicknesses to control the coupling.
If you can couple a power and ground plane for the frequency band you work in then you can use either as an energy return plane. You need to be aware for plane edges though. These can radiate and even resonate. Plane edges should be shunted for AC using small bypass caps. A large plane with no load is effectively a dipole antenna.

Yes, planes that are, for the most part, overlapping, appear as one.  You can even have a gap in one plane (say going from a 3.3V to a 1.8V domain, so the VCC pour changes), but with common ground underneath, and not really notice a change in the environment (you can actually do the 20ps TDR and see transitions as small as individual vias, and not see blips due to gaps in sufficiently large planes).

Though a plane pair acts as a low impedance transmission line, it still acts as one, and therefore can exhibit resonances, which is why you want bypasses -- notably, the physical locations of those bypasses need not be important!  What matters is that the plane (which itself acts as a low ESL capacitor) is well damped.  Appropriate size ceramic caps, plus beefy tantalum caps (chosen for their modest and stable ESR), are usually the best answer.

Tim

[DanielS]

That's why you cannot control return current on a doublesided board. The thickness of the material makes it so that you need traces that are 3mm or more wide to get the effect.

That sounds like more than enough to allow routing like signals together (e.g., differential pairs), and orders of magnitude sufficient to, say, build a dirty digital circuit on one side of the board, and a quiet analog circuit on the opposite side (say 10 * 3mm away).  Without cutting the ground plane.

That depends a lot on the nature of the noises you are dealing with and whether or not your analog stuff is sensitive to its characteristics. A large ASIC or FPGA generating 20mV of ground bounce due to combined IO and internal switching is a plane-wide wideband noise source; it will induce both common-mode and differential-mode noise in analog circuitry which are nearly impossible to get rid of without splitting the plane. (It can be done with via-stitching but you need RF engineering to make sure your stitch pattern will block all the frequencies you want to get rid of... and all that stitching adds so much impedance discontinuity to the ground plane, you might just as well gap it and spare yourself the RF math.)

[T3sl4co1l]

You mean, using the top side for VCC and the bottom for GND (or whatever)?  Where would signals go?

I normally route two-layer boards as full ground pour, stitched, with signals routed on the top where possible, and supplies on the bottom (invariably, some of both becomes necessary, but that's fine).

I'd kind of like to do a two layer, plane-pair type layout some time, but I can't convince myself that it's worth even trying.  As soon as you run just one trace, at all, anywhere, you have to stitch the same-layer plane by popping vias to the opposite side and making jumpers.  Repeat periodically along a bus, and then further, for each bus.  Then do it again for the opposite layer.  If nothing else, I'm sure you'd waste enough space routing it, that for the area savings versus stackup cost, it'll be cheaper to do it in 4 layers!  (Which is really just to say: that's what kind of layout a multilayer stackup is best at.)

Anyway, the lack of VCC plane is almost never a problem; indeed, it may even be an advantage, since the lengthy traces will filter ripple easier, as you are right to be concerned about.  It's another good reason to use the stitched ground method, I suppose: there's no paired conductor to form a transmission line, it's just ground all the way.  (Save for parasitic waveguide modes between stitch points, but those will all be low impedance, fairly lossy, and extremely high frequency.)  There may be ground bounce, but as seen by a local subcircuit, it will manifest as normal mode noise.

If you wanted to use a PLCC or TQFP packaged FPGA at high speeds, on a two layer board, you might have some problems packing in enough bypass caps and vias around the periphery, but for sure, the problem doesn't even exist in denser packages (BGAs) -- because you must use multilayer boards for those!

Tim

[pyrohaz]

Thank you all for your comments, they've been awfully insightful, albeit some over my head!

I've got an application specific question here, I'm designing the PCB for a simple parallel driven TFT display. My Byteclock will be ~2MHz and I've got round to laying out my board. I have the exact trace lengths and I'm wondering if this will cause any major problems with regards to data integrity.

(All in mm)
Data 0 - 25.918
Data 1 - 27.310
Data 2 - 28.787
Data 3 - 28.791
Data 4 - 25.460
Data 5 - 22.128
Data 6 - 18.797
Data 7 - 15.466
Clk      - 29.871

Each of the traces has one via included to go from top side to bottom side of the board.

[pyrohaz]

My Byteclock will be ~2MHz

But what's the edge rate or rise/fall transition time?

See http://www.ganssle.com/video/episode1.html for a graphic illustration of why the rise/falltime is more important than the repetition interval.

Thank you very much for that video, it was actually really good and cleared up a lot of my questions. One thing I do have to ask is why no development boards, or any of the ST products actually have termination? The STM32F4 discovery board for example has a codec on board with a bit clock of upto 192k*24 =  ~4.6MHz with the "fastest" defined rise time from the STM32F4 (defined at 100MHz IIRC) yet there is no form of termination or anything that has been explained in that video.  The board does however work and must work enough for them to sell the thousands of them that they have.

Sorry about my whole frequency relation thing with respect to signal integrity, I'm trying to get my head around why ST rate their rise times in relation to frequency.

[DanielS]

One thing I do have to ask is why no development boards, or any of the ST products actually have termination? The STM32F4 discovery board for example has a codec on board with a bit clock of upto 192k*24 =  ~4.6MHz with the "fastest" defined rise time from the STM32F4 (defined at 100MHz IIRC) yet there is no form of termination or anything that has been explained in that video.  The board does however work and must work enough for them to sell the thousands of them that they have.

As long as any oscillations from lack of termination have time to settle before the IC's clock-to-input setup window and remains stable through its input hold window, the stuff in-between can be almost any garbage within reason.

On short traces and relatively low transition rates, the signal will have time to settle even without termination and whatever ripple might be left from high frequency harmonics or edge noise will be too little to affect the outcome.

[DanielS]

Provided any out-of-tolerance voltages do not cause scr latchup - which depends on the the input protection designed in by the manufacturer.

That would be covered by the "within reason" part.

Provided ringing is not interpreted as a double transition - problematical if driving a counter, or if using "traditional hardware" i/o techniques where setup and hold times are closer to the limits than if  "bit banging" a clock separately from data.

What I wrote was only about the data signals. If you are going to "bit bang" a clock, you obviously need to make sure it is clean and meets the destination's timing requirements. In the case of the post I was replying to though, I doubt you would want to bit-bang a 5+Mbps stream to/from a DAC/ADC.

You ought to define "short". If the track (or stub) length is <1/6 the distance the transition occupies (~6"/ns), the rule-of-thumb is that there won't be a problem. That translates to 5" for a 5ns transition.

I go with 1/100th of the fundamental as my thumb-rule: even if the only termination on the data lines is the 8-10 ohms source drivers into 100-110 ohms traces, the signal should settle well within 5% long before the setup window no matter how sharp the transitions are.

Obviously, having 20-30 end-to-end reflections before the signal settles would not be acceptable on clocks.