PCB Power Plane question.

[kvresto]

Hi Everyone.

I’m laying out my first 4 layer board which I intend to have a pcb house make it up for me. I am using 4 voltage levels +-15V, +5V, and +3.3V, but as this is my first time in this playground, I have a question as to how many times is it wise to split your power plane, and is my design ok, or not?  I’ve included a pick of what it currently looks like.

Red = +5V
Blue = -15V
Green = +15V
Yellow = +3.3V
Violet = VDDIO, cpu io voltage.

Thanks.

[jahonen]

As long as you keep care that you don't route any high-speed signals in adjacent layer in such way that it crosses voltage planes, you should be fine. I have sometimes made something similar in the past:



Regards,
Janne

[kvresto]

Thanks jahonen

[T3sl4co1l]

The advantage of a ground "plane" over traces is, it's wider, so the characteristic impedance is lower, giving higher capacitance and lower inductance than traces can (and also making the impedance easier to terminate in bypass capacitors).  If you have it neck down a lot, you lose that advantage because now it looks like an electromagnetic dumbbell that resonates at some frequency (probably in the 100MHz range, just guessing from what it looks like).  Which can be effectively addressed with bypass caps and stuff, but then you need to be careful of that, too.

It seems like the 5V net doesn't have many connections; I suppose it's also not high speed or low noise?  That would be a good candidate to route as a trace (it practically is, already), maybe even on an outer layer (top or bottom).

You want to give priority to nets with lots of connections (routing traces to a hundred pads/vias is a PITA) and low noise nets (analog?), where the lower impedance helps out.  You want to avoid noisy circuitry (digital logic, switching supplies?) from overlapping low noise planes.  You also want to avoid traces crossing over the gaps between pours -- it's not so bad if ground (opposite inner layer) is contiguous (it acts to bypass the pours, so the coupling from/to the trace is relatively low), or if bypass capacitors are placed beside the traces, nailing down the edges between voltage domains.

Speaking of ground, the ground layer is solid, right?

Tim

[kvresto]

yep, solid all the way through. Top layer is pads/vias and tracks, second layer is ground, third is power, and the bottom is again tracks, which leads to another question, as the bottom layer is not filled with tracks there are large open areas left over, is it a good idea to stich the remaining surface area left over on the bottom layer to my ground plane? and whats the best method?

kv.

[T3sl4co1l]

I haven't had issues with leaving large areas open; top-to-bottom balance seems more important than balance across all layers.  At least with traditional "build-up" construction.

It would be nice to fill top and bottom, but I tend not to, just because it's such a pain.  You need to resolve vias through four layers at once, pinning loose ends of the ground pours (on top, bottom or both), while avoiding traces and internal planes.  And woe if you need to move things...

The "lazy" solution would be to pour everything, but that necessitates stitching, an involved process.  Ironically enough.  The less maintainable (I guess) approach might be to group traces as well as possible, and roughly fill the remaining areas, lightly stitched.  Annoying part is molding polys to the required shape.

If you have a situation that just naturally ends up that way, where you have a big bald spot you would like to fill in, sure, that's fine!  It's probably a good idea around noisy or low impedance circuits (switchers, ADCs, analog?), too.

Tim

[kvresto]

Thanks for your advice, and comments Tim. Having another look at my layout, and it seems your comments about avoiding traces and internal planes is in this case a bit of a nightmare, no matter where I look there's something in the way, so I'll just leave it bare no copper fill anywhere on the bottom other than the traces needed on this layer.

cheers
kv