Reducing ESP32-S3 current peaks during WiFi

[lutkeveld]

I have an ESP32 board that pulls about 150mA nominal, but 350mA peak during wifi transmission.
The peaks are only about 2ms, but trigger the over-current on the 250mA supply of the system (energy metering port).

The power flow is 5V > TLV62568A 1A buck > ESP32-S3
Currently I already reduced the wifi power from 21 to 11 dBm and added a 220uF elco to the 5V input.
The peak flattens and reduces a bit, but is still noticably there. Current profile measured with Nordic PPK2 is attached.
Now it is close to the 250mA limit, but with significantly reduced WiFi range.

How would I go about reducing these peaks so they get closer to the baseline?
More capacitance? Different type of capacitors? On the 5V rail, or on the 3V3 rail?
Some time of current clamp circuit?

[Psi]

More capacitance. But you really need a bulk storage ceramic cap on the 3.3v rail that the ESP32 is running on.
The electrolytic won't be able to respond fast enough for RF tx peaks, due to its high ESR, and having it far away on the 5V rail makes it even harder for the ESP32 to use. But if you add enough ceramic capacitance on the 3.3V rail then the electrolytic can probably stay on the 5V rail as secondary bulk capacitance.

You can get 100uF ceramics at 6.3V for like $0.50
But give it a try with a 22uF or 47uF if you have some, maybe that's all you need in conjunction with the 220uF elec. dunno.

[langwadt]

More capacitance. But you really need a bulk storage ceramic cap on the 3.3v rail that the ESP32 is running on.
The electrolytic won't be able to respond fast enough for RF tx peaks, due to its high ESR, and having it far away on the 5V rail makes it even harder for the ESP32 to use. But if you add enough ceramic capacitance on the 3.3V rail then the electrolytic can probably stay on the 5V rail as secondary bulk capacitance.

You can get 100uF ceramics at 6.3V for like $0.50
But give it a try with a 22uF or 47uF if you have some, maybe that's all you need in conjunction with the 220uF elec. dunno.

but it E= 0.5*CV^2 so you get more storage for "free" on 5V

[lutkeveld]

but it E= 0.5*CV^2 so you get more storage for "free" on 5V

Was also thinking along these lines, but seems more efficient in a sense to solve it at the origin (the 3V3 rail) if possible.

I tried a 100u 6.3V 1210 MLCC on the 3V3 rail but it does not do much to reduce the peaks unfortunately

Attached is a zoomed in version of the peak. It rises with about 25mA/us. Don't know if that can be calculated to a certain ESL/ESR target.
 

[Psi]

in that case you likely just need more capacitance.  Try 1000uF elec on the 5V rail.

Also, double check your scope probing/gnd to make sure what you're seeing is real.

Might also be worthwhile checking if your TLV62568A control loop bandwidth can regulate fast enough to handle the short ESP32 current pulses. But it's probably fine.

[lutkeveld]

Attached screenshot is with 2000uf on the 5V rail. This reduces the peak from 250 to 210mA.
Good start, but at the cost of significant bom cost and board space.
Don't know if the capacitance is effectively being used.
Could tolerate almost 500mV drop on the 5V rail, as long as the input current stays low.
Would be nice to get it to ~180mA but looking at ways to do it without 10.000 uF on the board.

[langwadt]

what happens if you limit the input current to, say, 200mA to spread out the recharge after the peak?

[Psi]

Are you sure the peaks are coming from the ESP32 and not from the TLV62568A responding aggressively to the ESP32 change in current draw.
It is after all a 1A regulator. Maybe you need a regulator where you can set the inductor current limit lower.

Can you try the same testing but supplying 3.3V from a lab PSU instead of the buck reg?

[lutkeveld]

what happens if you limit the input current to, say, 200mA to spread out the recharge after the peak?

I have considered something like the tps2553 to clamp the input, but its range it's too large (e.g. 240mA limit could be 180mA if you include variation)
Am looking into options with a shunt, op-amp and FET but not fully sure if that works out.

Are you sure the peaks are coming from the ESP32 and not from the TLV62568A responding aggressively to the ESP32 change in current draw.
It is after all a 1A regulator. Maybe you need a regulator where you can set the inductor current limit lower.

Can you try the same testing but supplying 3.3V from a lab PSU instead of the buck reg?

Will try to measure 3V3 consumption directly. How would a lower inductor current work? Wouldn't that cause droop on the 3V3 rail?

[mzzj]

Attached screenshot is with 2000uf on the 5V rail. This reduces the peak from 250 to 210mA.
Good start, but at the cost of significant bom cost and board space.
Don't know if the capacitance is effectively being used.
Could tolerate almost 500mV drop on the 5V rail, as long as the input current stays low.
Would be nice to get it to ~180mA but looking at ways to do it without 10.000 uF on the board.

One way to brute-force would be a small low-esr supercapacitor.
This for example would be a bit of overkill (you probably need to limit the charging current)
https://www.digikey.com/en/products/detail/cornell-dubilier-knowles/DGH504Q5R5/7387523

[marco.van.steen]

How much capacitance is required on 3.3V, if ALL current would come from the buffer capacitor:
First note that your DC/DC is efficient, so 100 mA too much on 5V is actually 100 x 5/3.3 = 150 mA too much on 3.3V rail.
C = (duration x current) / (allowable voltage drop) = 0.002s x 150mA / 0.2V = 1.5 milli farad.

Maybe this cap is nice: https://nl.rs-online.com/web/p/polymer-capacitors/8387721
(If you're lucky Wurth sends you free samples to try via their webshop)
It has 2 mF / 8 mOhm spec. Mount it very close to the ESP32  3.3V supply pin.

Now back to your basic problem: power port limit 250mA.
With the cap installed on 3.3V we must make sure that the pulse power comes from the cap, and not from the supply.
Adding a bit of resistance (roughly 1 Ohm, >> 8 mOhm) between the 3.3V regulator output and the radio supply should help for this.
But it may be easier to try to slow down the 5V regulator loop: remove C3 (as in their datasheet), if you have it.
If that doesn't fix it, try adding 100 pF ... 10 nF across R2.
A slow regulator loop gives effectively a higher AC output impedance, thus lower regulator input current peaks.

Good luck, keep sharing the results, and have fun!

[marco.van.steen]

Well, physics says in the 2 ms there is about 0.5 Joules more needed than the external 250 mA supply can deliver.
How can that ever be supplied from a small LC filter without excessive supply voltage drop?
A small LC will help to smooth out a DC DC switching frequency, but then you're talking 1 .. 10 us time scale, not 2 ms .

Turns out I'm not the only one saying this, see:
https://github.com/DiGierre/DSMR_reader_schematic_PCB

[lutkeveld]

Well, physics says in the 2 ms there is about 0.5 Joules more needed than the external 250 mA supply can deliver.

Supplying 1 W for time period of 2 ms is 2 mJ.

Which in theory is 160uF on 5V, which would work much better for me than using 2000uf+
How would I go about calculating such an input LC filter? Or as alternative/addition the output LC filter of the buck?
If I have a good starting value I can do some measurements to see its effect.

[CosteC]

I would try to add lots of capacitance, probably double layer 1 Farad or so capacitor. This however require PSU which will charge it up gradually and also will have current limit which will not trigger your source limits.
Also, very good reset and brown out mechanisms are mandatory as power will rise up sloooooowly.

I designed GSM modem powered for years from lithium cell. It required particular gymnastics around power management: how not to overload battery, still provide 2 A peak current when modem is transmitting, how to put it too sleep, how to wake it up and so good times.

[langwadt]

I would try to add lots of capacitance, probably double layer 1 Farad or so capacitor. This however require PSU which will charge it up gradually and also will have current limit which will not trigger your source limits.
Also, very good reset and brown out mechanisms are mandatory as power will rise up sloooooowly.

I designed GSM modem powered for years from lithium cell. It required particular gymnastics around power management: how not to overload battery, still provide 2 A peak current when modem is transmitting, how to put it too sleep, how to wake it up and so good times.

similar but possibly worse,  GSM modem on old school USB port, need ~2A peak, max from USB is 500mA with equivalent of max 10uF on VUSB

[lutkeveld]

The input LC filter. To make an appropriate calculation, I need to know the buck regulator inductor value and the switching frequency if you changed the chip meanwhile.

This is my current buck, but open to suggestion for a different part if that would work better

[spostma]

I would use an ordinary $0,40 PAM2808 analog 0 - 1.5A constant current LED driver
to limit the charging current into the big buffering electrolytic capacitor like this:

[tszaboo]

The ESP32 has indeed high current peaks. I don't think just a buck converters and regular capacitors are really going to solve the problem. The impedance of the P1 port's power supply is going to be ballpark lower than your capacitor, so it's going to try to supply this power.
You can go a few ways, basically you need to set a current limit lower. You can have a current limited boost converter go to let's say 24V and run an unlimited buck converter from that.
Or you can charge a capacitor, 5V with the P1 port, current limited, and have a buck-boost instead of a buck for the ESP32. This current limit can be as simple as a resistor. Maybe even a supercapacitor could work, something like 1F has plenty of energy to cover high current peaks and it's not as expensive as it sounds.

[xvr]

Peak current consumption is very high, making it impossible to solve this problem using standard smoothing methods (such as conventional capacitor-based circuits).
Supplying this peak requires a special energy source. A capacitor can serve this purpose, provided it is connected in a non-traditional way.

First, it is important to determine where to connect the capacitor. It must provide an energy reserve of 2 mJ (as mentioned earlier); however, it cannot deliver all its stored energy. The maximum allowable voltage drop limits the fraction of energy that can be transferred to the ESP. When connected to the 3.3 V rail, the capacitor can deliver about 17% of its energy (for instance, when discharging from 3.3 V to 3.0 V).
If connected on the 5 V side, about 56% of the energy can be utilized (during a drop from 5 V to 3.3 V, accounting for the voltage drop across the DC/DC converter).
Using a step-up/step-down (buck-boost) converter instead of a standard buck converter would allow for 97% efficiency (with a drop from 5 V to 0.8 V).

Second, the capacitor cannot be connected directly to the USB power source. It would attempt to draw all available power, so—as previously noted—a current limiter is required. Theoretically, an LC filter could be used, but it would need to smooth out the current spike while charging the capacitor from zero to full capacity over a relatively long period (to keep the current within acceptable limits). This would require an inductor with a fairly high inductance value.

Last but not least, the capacitor charging process will result in a slow voltage ramp-up in the power circuit. Consequently, you would need either a suitable DC/DC converter that ensures the correct output voltage rise time (I am not sure such devices exist), or use of the converter's "Power Good" signal, or an external reset IC for the ESP (alternatively, you could enable the built-in Brown-Out Detector and hope for the best).

[gspeed]

just add a series resistor before the capacitor??

[xvr]

Not at all. The switching frequency of the buck is 1.5 MHz. Reaching 30 dB or more attenuation is easy with small inductors and small capacitors.

I mean LC filter to smooth rush current from bulk capacitor charging, not from DC/DC convertor.

[Doctorandus_P]

I didn't read all posts, but my own preference would also be to have a big capacitor on the 5V side, and then use a voltage regulator that can handle the peak current. This way the capacitor can sag a bit without ill effects. You still have to ensure there is enough for the voltage regulator to do it's job.

[langwadt]

how will that help when the ESP uses ~7W for a few milliseconds?

Did you try to think about what your statement would imply? The chip measures 5x5 mm and would have to dissipate > 6 W when transmitting at + 20 dBm which is 100 mW (the power going into the antenna). Or perhaps the ESP32 is also a glow in the dark aparatus when used as a wifi module.

you are obviously right, I somehow got things mixed up with the talk of GSM using 2A in peak

[Someone]

Here is the official ESP32 data sheet:
https://documentation.espressif.com/esp32_datasheet_en.pdf

Page 52.

Transmit 802.11b, DSSS 1 Mbps, POUT = +19.5 dBm
Typ 240 mA

RF front ends usually operate at 10...20 % efficiency to avoid distortion. To output  100 mW, you will need about 1 W. It seems things agree. 3.3 V x 240 mA: 792 mW

Except the OP is having trouble with the peak current, which you conveniently chopped out of the "quote" (and only typical, not worst case).
Others measure pretty similar to the OP:
https://www.microelectronicos.net/measuring-power-on-esp32-modules/

[Someone]

I would use an ordinary $0,40 PAM2808 analog 0 - 1.5A constant current LED driver
to limit the charging current into the big buffering electrolytic capacitor like this:

Fairly sure your design wont work as the LED driver will let current pass to your output, the output current is not sensed by the Rs and only limited by the 2.5A over current protection for the pass element.