Testing Buffer for SAR ADC Ref Input

[Andree Henkel]

Hy, shown is a Buffer Circuitry to drive Ref Input of a SAR ADC
ADC is planned to be inside an µC from STM-Microelectronics: STM32C092RC
maximum sampling rate is stated 2,5MS, we likely will use two channels but at lower rate, 4 additional channels during factory calibration

My actual question is at end of post.


There will be a while until we have actually running firmware, so I want to test the buffer now
target is little voltage droop at different sampling rates and little AC perturbation

Thus I want to determine the values shown as tbd and evaluate, if the choice of OPV is suitable.

Theory: SAR Ref Input presents a pulsed load, current spikes at rate of sampling rate flow into the REF input to perform the SAR type charge redistribution in CAP Arrray
to smooth out the spikes you place the charge storage CR, usually a 10µF + a 100nF CAP, here µC with SAR is on different Board (so I plan two 100n, one at output of OP and one at REF Input of µC)
the current pulse train leads to a droop in voltage across the caps, depending on sampling frequency and characteristics of the current spikes
to counteract this drop the buffer U3 with Ref Signal fed to noninverted Input is used
RI prevents oscillation due to the large cap load, values 10..100 Ohms, most likely 22 to 47
RF is DC feedback, values around 1k..3k3, this takes care to steer voltage across CAP to be equal to Reference Voltage
Cf is fast negative feedback, values somewhere 33p..100p

Output goes via connector to µC eval board,

µ-Coax connector is there for easy connecting scope or 6.5digits dmm


Question:

I want to emulate the pulsed current spike load - using a function generator + Resistor
what are realistic values for height and duration of the current spikes to expect at the SAR REF input?

[Kleinstein]

For emulating the load from the ADC, I would use a series capacitor (some 5-100 pF (depends on the ADC) and square wave at the generator) with a series resistor (e.g. some 500 ohms maybe).
For a direct simulation with short pulse and resistor it would be again some 500 ohms (depends on the ADC - the DS may give more hint on the switch resistance) and than short pulse to get a comparable charge. 10 pF * 3 V are 30 pC and this would this be some 6 mA for 5 ns. If the genrator is not that fast one should get away with a longer puse like 100 ns or even 1 µs with less current as the 100 nF cap should smooth this largely.

[mtwieg]

Yeah you could build some sort of circuit to imitate how the ADC loads the buffer. But what you measure with that setup will just be a voltage waveform, and how can you relate that to actual ADC performance?

It would probably be far more worthwhile to make some simple firmware which exercises the ADC so you can directly observe its performance (THD, SINAD, etc).

[Andree Henkel]

I have done that in past, but was like 20+ years ago, I used that Buffer Config (other OP) for a 16Bit 100kS standalone SAR and it finally worked to 16Bit.

At start not. Firmware guy wrote me a test setup after it was discovered, that measured values did vary several bit between successive measurements.
At those times there were only 8 Bit scopes, so no chance to look at the buffered ref signal.

Firmware switched on ADC meassurement, and resulting values showed a damped sine wave response several Bits of magnitude. Culprit was as far I remember that feedback cap had to large value, so corrective action was too slow. With lower feedback cap it finally worked as desired.

But I´m not the person that will write the firmware, and person who will do, won´t have time for some months

fortunately this time by far requirement will not be 16Bit, ADC only has 12, I just want to make sure there are no nasty surprises

[Andree Henkel]

I will continue and report results.

I´ll start with Ri 22R, Rf 1k and Cf for time constant 1/2,5MHz= 400ns; 400ns/1k = 400pF -> choosen 33pF

observe stability with Scope R&S RTA4004 (10 Bit 350MHz), if necessary increase Ri

Inject pulse train via 500R coming from Agilent 81160A in pulse mode, pulses going negative from 2.1V to 0V, pulse width 5ns, rise and fall time at 1.2ns minimum.

check output voltage with 6.5 digit Keysight 64461A while varying pulse rate 1kHz to 2.5MHz

check transient response with scope at switching on and during pulses of different rates

scope is good for 500µV/Div, using 2,1V offset removal there is no need for AC couple mode

[Andree Henkel]

Yeah you could build some sort of circuit to imitate how the ADC loads the buffer. But what you measure with that setup will just be a voltage waveform, and how can you relate that to actual ADC performance?

It would probably be far more worthwhile to make some simple firmware which exercises the ADC so you can directly observe its performance (THD, SINAD, etc).

well, yes I´ll relate the voltage waveform to actual ADC performance using 2,096V/2^12 = 0,512mV LSB

[Andree Henkel]

change in planned test setup:

I´ll reduce resistor to 50Ohm, so I don´t need to worry about reflections for the pulses from generator
Scale pulse height to keep current pulse height
option to increase pulse height for larger current pulses

also this is closer to typical resistance values of analog switches within ADC

Connection U.FL to scope I´ll keep short using adapter cable U.FL to SMA and SMA to BNC adapter
Scope will be DC with offset, 1MOhm input

[HighSNR_Lab]

A few additional points may be worth considering.

The value of CF should not be derived from the ADC sampling period. The ADC sample rate does not directly determine the stability or correction speed of the buffer. With RF = 1 kΩ and CF = 33 pF, the RF/CF corner is about 4.8 MHz, but this is not the actual crossover frequency between the local and remote feedback paths. The load capacitance, RI, capacitor ESR and ESL, PCB layout, connector inductance, and the open-loop response of the OPA835 all take part.

So 33 pF looks like a reasonable starting value, but the comparison with the OPA835’s 56 MHz gain-of-one bandwidth does not by itself guarantee stability. A much larger value, such as 400 pF, would make the remote correction significantly slower and could bring back the damped ringing seen in the earlier 16-bit design.

Another point is the input bias current of the OPA835. It has bipolar inputs, and the specified bias current can reach about 400 nA at room temperature. At DC, the inverting-input bias current flows through RF.

With RF = 1 kΩ, this can produce about 0.4 mV of reference error, which is approximately 0.8 LSB for a 2.048 V, 12-bit ADC. With RF = 3.3 kΩ, the error can increase to about 1.3 mV, or roughly 2.6 LSB. The correct LSB value is 0.500 mV; the earlier 0.512 mV result used 2.096 V instead of 2.048 V.

This error is mainly a reference gain error rather than a fixed offset in every ADC result. It can be calibrated. Matching the DC resistance at the noninverting input to RF can also cancel much of the common bias-current error, leaving mainly the input offset current and resistor mismatch. The OPA835 input offset voltage should be included in the total error budget as well. In any case, this supports using the lower end of the proposed RF range.

The SAR ADC also does not draw one single current pulse per conversion. It performs a sequence of internal bit decisions during each conversion, with reference-current activity occurring at the ADC clock rate. The exact current waveform is not published, so assumptions about twelve identical spikes, or the MSB pulse always being the largest, should be treated as a useful model rather than a guaranteed internal waveform.

The STM32C092 datasheet gives a typical VREF current of about 65 µA at 2.5 MSPS. This corresponds to approximately 26 pC per conversion. If that charge were supplied entirely by an isolated 100 nF capacitor, the voltage change would be about 0.26 mV, or roughly half an LSB.

This makes the capacitor directly at the MCU VREF+ pin especially important. The local 100 nF capacitor will supply much of the high-frequency current, while the larger capacitors on the buffer board will mainly support the lower-frequency envelope. The exact charge sharing will depend on the connector and PCB inductance, RI, and the impedance of all capacitors involved.

For this reason, measuring only on the buffer board may significantly underestimate the disturbance at the MCU pin. I would inject and probe on both sides of the connector. Adding 1 to 4.7 µF directly beside the existing 100 nF at VREF+ is also worth considering, followed by another stability check with the complete interconnect and capacitor network fitted.

The LQFP64 version of the STM32C092 does have a separate VREF+ pin. The specified VREF+ range starts at 2.0 V, so a nominal 2.048 V reference gives only 48 mV of downward margin. That margin must include reference tolerance and drift, amplifier offset and bias-current errors, and dynamic droop.

Looking forward to the measurements, especially a comparison between injection and probing on the two sides of the connector.

[Andree Henkel]

first: the main purpose of the buffer in target circuit is to use same Ref for the µC internal ADC AND for external DACs.
So main purpose is to isolate Ref Inputs to the DACs from the SAR ADC Ref input current spikes.

So errors around like 1LSB may not be reason not to use it.

bias current of the OPA835. It has bipolar inputs, and the specified bias current can reach about 400 nA at room temperature. At DC, the inverting-input bias current flows through RF.

With RF = 1 kΩ, this can produce about 0.4 mV of reference error, which is approximately 0.8 LSB for a 2.048 V, 12-bit ADC.

I´ll consider adding 1k compensation resistor in noninverting path, however Yes, we will be doing some kind of system calibration for one of the ADC channels, and the other are mainly monitoring purposes

The STM32C092 datasheet gives a typical VREF current of about 65 µA at 2.5 MSPS. This corresponds to approximately 26 pC per conversion. If that charge were supplied entirely by an isolated 100 nF capacitor, the voltage change would be about 0.26 mV, or roughly half an LSB.

This makes the capacitor directly at the MCU VREF+ pin especially important. The local 100 nF capacitor will supply much of the high-frequency current, while the larger capacitors on the buffer board will mainly support the lower-frequency envelope. The exact charge sharing will depend on the connector and PCB inductance, RI, and the impedance of all capacitors involved.

for the moment I´ll only test the buffer ref+buffer board.
Yes It seems good idea to distribute the 10µF half at Buffer output and µC Ref Input
I´ll test that later in time
currently we make  a test build for a project, consisiting of 7 individual boards, one beeing the Ref+Buffer + DAC+Buffer for DAC and Pots for manual adjust instead of DAC (The DAC/Pot+Buffer are for  biasing pulsed transistor gates, so there will be similar buffer technique be used, another board is carrier board for µC Eval Kit
later that will be shrunk to one / two boards and a small for a TIA, but still the Ref + Buffer and µC withh ADC will likely be several cm apart, so I plan to still use ist

Yes test for whole setup with the several boards will be necessary, as well as test with target layout

The LQFP64 version of the STM32C092 does have a separate VREF+ pin. The specified VREF+ range starts at 2.0 V, so a nominal 2.048 V reference gives only 48 mV of downward margin. That margin must include reference tolerance and drift, amplifier offset and bias-current errors, and dynamic droop.

Planned Ref is MAX6070B at 0.08% initial tolerance, 1.63mV I guess the 48mV should be plenty, but still yes we will consider switching to 2.5V