Wien Bridge project

[Kleinstein]

The factor 3 applies to the case of equal reistors and equal capacitors for the frequency setting network. With the series connected R and C at 1/2 R and 2*C as the parallel pair the stable oscillation would be at a gain setting of 2 instead of 3.
The case with equal values is easier to calculate and may have slightly better stability, but at least small deviations do not change much. So with R and C with some 10% tolerance the required gain could be about in the 2.7 to 3.3 range.

The required adjustment range deopends on the accuracy of the RC networks to set the frequency. The better the parts are selected there, the smaller the AGC range can be.
2.95 to 3.05 would need relatively tight tolerance, though not imposible.  For a given frequency setting the required range could be quite a bit smaller and it does not have to be exactly around 3.  Accurate chosen resistors alone are not enough to get a stable amplitude, but they can reduce the needed AGC range. The automatic part only needs to overcome tolerances, drift and have enough range to get the amplitude up and stable in reasonable time. So for a given RC network the actually needed range could be something like 3.14 to 3.141  - more gain may be better for a fast start up.

The larger usually required adjustment range is no just a general trend to need more gain at higher frequency, it is likely more due to some not so well chosen RC networks for the frequency.

[richlooker]

So 2.95-3.25?  Why not 3.05?

Is the difference the aforementioned drop in loop gain at the high end?

Based on my experience during this project. Gain will not exceed the theoretical value assuming perfect opamp, so going much below 3 is not needed.  Gain will drop below the theoretical value, so a certain margin is needed.

Why not tweak out a frequency-dependent gain error using an RC network?  (This will introduce phase shift -- indeed, complementary to the op-amp's own phase shift, which is part of the effect as well!)

A theoretical possibility, but probably not worth the effort. If it was, someone would have done it before and published the result; eg. "Parasitic capacitance compensation for 1Hz-1MHz constant gain opamp"

Note that that formula works for the SPICE component.  But real devices aren't piecewise functions, they fade smoothly between regimes.  How should we express this fact?  And do we know whether it's responsible for the dominant part of distortion under whichever conditions?

Spice models are the closest approximations to real components mere mortals can afford. There are enough credible sources stating the model reflects actual behaviour for me to trust it. The models are certainly not perfect. But the conditions are not "whatever", they are controlled and specific. The JFET itself is the biggest contributor of (theoretical) uncertainty.

Richard

[T3sl4co1l]

A theoretical possibility, but probably not worth the effort. If it was, someone would have done it before and published the result; eg. "Parasitic capacitance compensation for 1Hz-1MHz constant gain opamp"

I mean... what's there to publish?  That just sounds like another day in the office at Tektronix, back in the day.

Like---humor me, how about some basic feasibility calculations?  Simulations?  Is this even in the right order of magnitude to be a relevant effect?  Should we just all sit in the dark, spitballing rumors until we all get tired and go home every day?..

The pursuit of high levels of precision, seems like a very worthwhile application of a little analysis here, but it doesn't seem to be gaining any traction, or even any recognition?  I'm just confused how that should be...

Spice models are the closest approximations to real components mere mortals can afford. There are enough credible sources stating the model reflects actual behaviour for me to trust it. The models are certainly not perfect. But the conditions are not "whatever", they are controlled and specific. The JFET itself is the biggest contributor of (theoretical) uncertainty.

Alright fine, but then, what's the point of low THD if 0.01%, heck, 0.1% is good enough for "mere mortals"?  Have I grossly misunderstood the priorities of this project? 

Tim

[richlooker]

Alright fine, but then, what's the point of low THD if 0.01%, heck, 0.1% is good enough for "mere mortals"?  Have I grossly misunderstood the priorities of this project? 

Tim

Design goals:

• 11Hz-100kHz frequency range in four switchable decades
• Fixed/discrete frequencies, 26 per decade, per 26-position rotary switch (derived from requirement 1: I want immediate and precise frequency selection; dual-ganged pots won't do; and 2: I have this switch and want to use it )
• Super-fast settling time at frequency change, no amplitude wobble
• +12dBu / 3.1V RMS output & 11-step attenuator 0db - -60dB
• THD < 0.01% 100Hz-10kHz
• Learn a lot & have fun
• Make an awesome looking and practically usable device

The gain variance caused by RC network tolerances is minimal, as I have ensured capacitors and resistors match to within 0.5%. Phase shift in the opamp at increasing frequencies is adequately handled through different compensation resistors per frequency decade. The remaining challenge is the THD one; the rest is just work. From my - admittedly limited - knowledge and what I have experienced so far, it's JFET channel length modulation that stands between me and the THD < 0.01% goal. If someone convinces me that frequency-dependent gain compensation will help, I will certainly look into that. But until then I'm focused on taming the prickly JFET

[Vovk_Z]

it's JFET channel length modulation that stands between me and the THD < 0.01% goal. If someone convinces me that frequency-dependent gain compensation will help, I will certainly look into that. But until then I'm focused on taming the prickly JFET

Have you tried different Fets? One of them may lead you to <=0.01%.
It has to be not very hard to go under 0.01% at some frequency. But it can be quite hard to have <0.01% in the whole frequency range.

[richlooker]

I have concluded that none of the JFETs I have are optimal for this application. I have a few on order; the 2N4338 used by Jim Williams plus some 2N5484 as this was used by ESP/sound-au.com. The former achieved 0.015% but without tweaking resistors to reduce it further, and measured at the resolution limit of the THD meter - meaning the actual result may have been even better - while the latter claimed < 0.01% in simulations, also without further tweaking. This gives me hope I can achieve the same result by replicating what they did, and maybe further improve upon that through patience and perseverance

Richard

[Vovk_Z]

through patience and perseverance

:-) I don't want to say that, but "I told you" at the very beginning that Wien-Bridge is not the best topology if you need both low distortion, high amplitude regulation, and wide frequency range.

[richlooker]

through patience and perseverance

:-) I don't want to say that, but "I told you" at the very beginning that Wien-Bridge is not the best topology if you need both low distortion, high amplitude regulation, and wide frequency range.

It's certainly not the easiest

Richard

[richlooker]

It dawned on me; the distortion from the JFET in the neg feedback network is a completely separate problem from oscillation conditions and regulation. Why not do some measurements with the complicating factors removed from the equation?

This is the amp exactly as it will be in the oscillator, just with the positive feedback network removed:



Until I get the 2N4338 and 2N5485 I have ordered, I will test BF245C, 2N5458, 2SK170BL and J110;

• Apply a 1kHz 0dBu/3 signal at U1A positive input
• Step through 6 different combinations of R3, R4 and R5
• Tune in Vgs with P2 for U1A gain=3 - ie. Vout = 12dBu
• Measure Vgs
• Tune P1 for lowest THD

The first three resistor combinations are the values from Jim Williams' circuit plus two variants keeping Vds approximately the same but with double and half the Ids. The next three combinations get approximately half the Vds, and again three different Ids values.



I have approximated Rds(on) at 100Ω; deviations from this value will just impact max gain - eg. J110 will probably have a much lower value, but this does not matter as it will not be operated in this region anyway.

Richard

[Vovk_Z]

THD of LM6172 itself both non-inverted or inverted mode is very low (ultra-low). It is somewhere near 0.001%. It depends somewhat on feedback resistors resistance.
The most and the only one non-linear element of this circuit is JFET.
That's why some designers use opto-resistors (as more linear) for ultralow distortion oscillators.
But it is hard to get them these days at the market.

[richlooker]

THD of LM6172 itself both non-inverted or inverted mode is vely low. It is somewhere near 0.001%. It depends somewhat on feedback resistors resistance.
The most and the only one non-linear element od this circuit is JFET.
Thats why some designers use opto-resistors (as more linear) for ultralow distortion oscillators.
But it is hard to get them theese days at the market.

[Vovk_Z]

The first three resistor combinations are the values from Jim Williams' circuit plus two variants keeping Vds approximately the same but with double and half the Ids. The next three combinations get approximately half the Vds, and again three different Ids values.

- I make a bet that the first combination has the lowest THD. 
(I don't have any deep theory about that, it's just a guess from my engineering experience with my own Wiene-Bridge project).

[bsfeechannel]

That's why some designers use opto-resistors (as more linear) for ultralow distortion oscillators.
But it is hard to get them these days at the market.

LDRs?

[Vovk_Z]

Yes, somebody use combination of LDR plus LED, but it is not very convenient.

[2N3055]

Some posts are missing...

There are optocouplers that combine LED and LDR as ready made units.
For instance NSL-32SR3 (now Luna Innovations Incorporated) as member Blackdog mentioned in missing posts...
You can easily make one by yourself from green LED and LDR, but will have to characterise it by yourself too.

[blackdog]

Hi,

This is strange...
My post about the NSL-32SR3 opto coupler has disappeared....

That's not because of my interference I just looked back on the forum and couldn't find my post anymore, what's going on?

Kind regards,
Bram

[RoGeorge]

Some posts are missing...

Yes, Dave told us that it was some database incident, so most probably it was necessary to roll back a day or so, in order to fix the issue.  Looking at my own posts, it seems like only about one day is missing, but IDK for sure how.

In this topic I was suggesting to put a photo-resistor together with a white LED and a few layers of black shrinking tube in order to improvise an optocoupler, and later from other replies it was suggested a green LED would be even better than white, and that many resistor based optocouplers can be ordered from Mouser or Farnell.

[David Hess]

Yes, Dave told us that it was some database incident, so most probably it was necessary to roll back a day or so, in order to fix the issue.  Looking at my own posts, it seems like only about one day is missing, but IDK for sure how.

It is a glitch in the Matrix.  It happens when they change something.

[richlooker]

It's been a long time. That's the way it is when you have too many simultaneous projects :-)

I finally got my FETs - 2N5484 and 2N5486 (Fairchild, eBay seller littlediode components, UK) and 2N4338 (unspecified, eBay seller nikkoelec, UK).

Did a quick check of Vgs(off) and measured the 2N4338 to -6V, very clearly a fake, just a rebadged generic TO-72 JFET.

Then I discovered Siliconix Application Note 105: JFETs as Voltage-Controlled Resistors: https://www.interfet.com/jfet-datasheets/siliconix-an105.pdf

This AN was very informative. It states that the JFET is most linear as a VCR when operated close to Rds(on), and that distortion rises significantly when Rds exceeds 10 x Rds(on). It reiterates that Vds must be kept low to minimize distortion, and that applying 1/2 of (AC) Vds to the gate keeps distortion at minimum. And then the crux:
- There are JFETs that are purpose-made for VCR application!



The VCR4N seems most suitable for my requirements. I ordered one from mouser, along with a genuine 2N4338.

I made a circuit to measure Rds(on) plus Rds at different Vgs and corresponding distortion when applying a 775mV 1.3kHz signal. To avoid the interdependency between the Vgs DC bias and the AC signal fed from drain, I introduced an opamp.



This provided some interesting learnings;

• VCR4N and 2N4338 don't actually have a Vgs(off) or Vp, they reach a max Rds at a certain Vgs which then does not increase with lower Vgs (approx 7.5 x Rds(on)
• VCR4N is substantially better than the RF/general-purpose JFETs
• My VCR4N has an Rds(on) at approx 430Ω, which is quite ideal for my application
• At Vds (AC) above 200mV, distortion rises sharply
• The 2N4338 is not very well suited to my application, with an Rds(on) around 1.2K and much higher distortion than VCR4N

[T3sl4co1l]

This AN was very informative. It states that the JFET is most linear as a VCR when operated close to Rds(on), and that distortion rises significantly when Rds exceeds 10 x Rds(on). It reiterates that Vds must be kept low to minimize distortion, and that applying 1/2 of (AC) Vds to the gate keeps distortion at minimum.

Well gosh, this must've been mentioned only about a dozen times in the thread!

And then the crux:
- There are JFETs that are purpose-made for VCR application!

The VCR4N seems most suitable for my requirements. I ordered one from mouser, along with a genuine 2N4338.

For reference:
http://www.farnell.com/datasheets/40047.pdf

Note that they hardly give any data, and no curves besides the extremely up-close drain curves -- which look reasonably controllable, but of course they do within such a small region, and it's not clear where cutoff lands (despite the label on the plot).

If they aren't some weird special design, they should be nothing more than devices selected for high Vgs(off), I think.

I made a circuit to measure Rds(on) plus Rds at different Vgs and corresponding distortion when applying a 775mV 1.3kHz signal. To avoid the interdependency between the Vgs DC bias and the AC signal fed from drain, I introduced an opamp.

This provided some interesting learnings;
VCR4N and 2N4338 don't actually have a Vgs(off) or Vp, they reach a max Rds at a certain Vgs which then does not increase with lower Vgs (approx 7.5 x Rds(on)

Hmm, this is not possible, or something is funny about the interpretation?

The datasheet clearly says Vgs(off) at Vds = 10V, Id = 1uA or whatever.  It has cutoff like any other JFET, and so Rds(on) will go towards infinity as Vgs falls -- and within a decreasing span of drain voltage for which the response is linear, or else increasing distortion at fixed drain voltage.  The drain-gate divider cannot fix this, as inevitably Vgs < Vgs(off) must occur at some point, and as it crosses the threshold, Id goes to ~0 resulting in distortion.  (Which should be, mostly a zero-crossing sort of thing, due to the effect of the divider?  Effectively as signal voltage goes negative, drain and source swap positions, so Vgs has the same response as for positive signals -- hence the half divider: the strategy is to put the gate "in the middle" between D and S, making the distortion symmetrical I think.  It's not that it's halving drain voltage, it's that it's averaging both drain and source voltages together.  Ah, I never noticed that before and merely took the trick for granted, makes sense.)

Are you measuring current exactly as indicated in the schematic, or actually Vds in which case Rs makes a divider with R4+R3 and anything else hanging off the circuit (presumably the probe is over a meg though)?  That could have that kind of effect.

Tim

[Kleinstein]

As shown the circuit adds the full drain votlage to the gate, not half as it should be for lowest distortion.

[richlooker]

Well gosh, this must've been mentioned only about a dozen times in the thread!

Not exactly. It has been mentioned that the "linear region" is where Vds < Vgs(off) - Vgs - but this linearity is in fact only very linear when Rds < Rds(on) x 10, and according to my measurements it's best to keep Rds < Rds(on) x 5

Note that they hardly give any data, and no curves besides the extremely up-close drain curves -- which look reasonably controllable, but of course they do within such a small region, and it's not clear where cutoff lands (despite the label on the plot).

If they aren't some weird special design, they should be nothing more than devices selected for high Vgs(off), I think.

VCR2N is specified for Vgs(off) between -1 and -3.5V, not very high?

I made a circuit to measure Rds(on) plus Rds at different Vgs and corresponding distortion when applying a 775mV 1.3kHz signal. To avoid the interdependency between the Vgs DC bias and the AC signal fed from drain, I introduced an opamp.

This provided some interesting learnings;
VCR4N and 2N4338 don't actually have a Vgs(off) or Vp, they reach a max Rds at a certain Vgs which then does not increase with lower Vgs (approx 7.5 x Rds(on)

Hmm, this is not possible, or something is funny about the interpretation?

The datasheet clearly says Vgs(off) at Vds = 10V, Id = 1uA or whatever.  It has cutoff like any other JFET, and so Rds(on) will go towards infinity as Vgs falls -- and within a decreasing span of drain voltage for which the response is linear, or else increasing distortion at fixed drain voltage.  The drain-gate divider cannot fix this, as inevitably Vgs < Vgs(off) must occur at some point, and as it crosses the threshold, Id goes to ~0 resulting in distortion.  (Which should be, mostly a zero-crossing sort of thing, due to the effect of the divider?  Effectively as signal voltage goes negative, drain and source swap positions, so Vgs has the same response as for positive signals -- hence the half divider: the strategy is to put the gate "in the middle" between D and S, making the distortion symmetrical I think.  It's not that it's halving drain voltage, it's that it's averaging both drain and source voltages together.  Ah, I never noticed that before and merely took the trick for granted, makes sense.)

Are you measuring current exactly as indicated in the schematic, or actually Vds in which case Rs makes a divider with R4+R3 and anything else hanging off the circuit (presumably the probe is over a meg though)?  That could have that kind of effect.

Tim

I am measuring Vds, with a 10M probe. For 2N5458, 2N5486 and the fake 2N4338, Rds reaches Rds(on) x 50 at Vgs ~-3V. VCR4N and 2N4338 refuse to increase Rds beyond Rds(on) x 8 - for a pure AC signal in the < 1V peak range. There may be something fishy about my measurement setup; I'll try with larger R3 and R4, and buffer Vd with a TL072 to avoid loading the circuit.

Richard

[richlooker]

As shown the circuit adds the full drain votlage to the gate, not half as it should be for lowest distortion.

This is a simulation of the circuit. Measurements match this.

[T3sl4co1l]

As shown the circuit adds the full drain votlage to the gate, not half as it should be for lowest distortion.

How so, the diff amp has gain 0.5?

Not exactly. It has been mentioned that the "linear region" is where Vds < Vgs(off) - Vgs - but this linearity is in fact only very linear when Rds < Rds(on) x 10, and according to my measurements it's best to keep Rds < Rds(on) x 5

Same same?  Rds, V(linear) and Vgs are all related.  Think I've also said, more qualitatively, that it's only useful over a narrow adjustable range, I might've said like 3x or something.  So that fits nicely with the above finding.

VCR2N is specified for Vgs(off) between -1 and -3.5V, not very high?

Check the datasheet I linked, Vishay's are -3.5/-3.5/-2.5 for the series.

The InterFET version shows otherwise:
https://www.mouser.com/datasheet/2/676/jfet-vcr2n-interfet.r00-1649182.pdf
Beware, YMMV?

Tim

[richlooker]

New test circuit, with a couple of extra opamps to isolate Rs & T1 from the feedback network and probe impedance, and to keep the load on the generator constant (zero).

Will redo the tests and see if VCR4N has a proper pinch-off or not. (2N4341 was the closest thing I found in the Tina-TI spice library)