Are you sharing your work or is the question missing?
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The 2 kV figure is not a lie. It seems to “only” be missing an important detail!
It feels like the designer didn’t fully understand the operation of the circuit. It seems as if somebody thought that in a Cockcroft-Walton multiplier a single stage is a single capacitor and a single diode, and what they make is a 5-stage multiplier giving 5× higher voltage.
But a single stage is an entire assembly of two diodes and two capacitors. So first we have a proper voltage quadrupler: C1…C4, D1…D4 in your schematic. Depending on conditions it produces solid 1.2–1.4 kV. After that there is a “funny half-stage” (C5, D5). This adds a sine wave of 600–650 Vp-p.
I guess your measurement is 1.2-1.3 kV plus 300–320 V from that sine wave, slightly sagging under the load. Measured as DC, so the average value. Marked as “M” on the chart below:
![Bug Zapper [repaired] - measuring high voltages and reverse engineered](https://www.eevblog.com/forum/index.php?action=dlattach;topic=473093.0;attach=2679443;image)
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As for the divider, mind accuracy. Circuits that have high output impedance are a bit tricky.
For this setup it didn’t matter that much, because it is already all over the place. But let’s take it as an example. Ignoring a minor influence from the DMM, this divider presents about 9 MΩ. Since the voltage multiplier has high output impedance (in the order of 100 kΩ), the measured voltage will sag by a good percent or two just from that measurement.
You also calibrated the divider with a known voltage source. That is a good choice! But if you didn’t and just went with 8:1 ratio, there is a trap. The DMM itself is about 10 MΩ, which would be in parallel with 1 MΩ. It is a small influence, but not something that can be completely ignored.