The art of logic signal manipulation with analogue components (D/R/C)

[wasedadoc]

By the way, I'm no expert, but I think the R/C part is probably not working as a filter here?

Correct.  Both R32&C and R34&C are to make delays, not to act as filters.

To be precise the setup in combination with the gates is what gives the signal its delay. The R/C combination is still a low pass filter. Just look at the signals on the capacitor and see how the edge of the signal is filtered into a slope.

Also when you raise the frequency of the input signal it will reach a point that the circuit does not work anymore.

Added an image plucked from the net to show this filtering.

1.  We don't know the value of the Cs but I'd wager the gate delay contributes very much less delay than the RC.

2.  Yes, RC forms a low pass filter but that is not the aim here.  The values of R and C were not computed  to give some specified value of attenuation at some specified frequency.  Rather they were computed so that the exponentially rising or decaying waveform reaches approximately 50% after some required time.   

[pcprogrammer]

1.  We don't know the value of the Cs but I'd wager the gate delay contributes very much less delay than the RC.

Correct, and that is also not what I intended to state. The gate is needed to reshape the signal edge and in combination with the other input to make the pulse. The delay of the gate itself will indeed be negligible.

2.  Yes, RC forms a low pass filter but that is not the aim here.  The values of R and C were not computed  to give some specified value of attenuation at some specified frequency.  Rather they were computed so that the exponentially rising or decaying waveform reaches approximately 50% after some required time.

I agree that the designers made calculations based on the RC time and were not aiming for a specific -3dB point.

Looking at a datasheet for a CD4030 when powered from 10V Vin low is max 3V and Vin high is min 7V, so depending on the actual supply voltage and the Vout of the first gate the times can be calculated. But for this the value of the capacitor needs to be known. I would have to search for the formula to do so. I do remember that t = R * C, and that after ~5t the capacitor is at near the supplied voltage.

Since max.wwwang indicated his intention to learn, it helps to provide as much information as is helpful. 

[max.wwwang]

To be precise the setup in combination with the gates is what gives the signal its delay. The R/C combination is still a low pass filter. Just look at the signals on the capacitor and see how the edge of the signal is filtered into a slope.

Also when you raise the frequency of the input signal it will reach a point that the circuit does not work anymore.

Added an image plucked from the net to show this filtering.

In some sense that's correct. And that's exactly what's illustrated in my second diagram (sync-1) with narrow pulses of the input signal, which means nothing but higher frequencies! In that case, i.e., when the frequency of the input signal is high enough, it will be essentially blocked (more precisely, bypassed) by the R/C 'filter', so some transitions of the input signal will be invisible to what connects to the output pins (and the output signals become less comprehensible --- at least to me). After all, and obviously, the R/C components don't know, and don't care, what hat we are putting on their heads! They just do what they are supposed to do. 

But in this case, I would say --- practically --- because the input signal is driven by mechanical parts, its frequency is unlikely to be very high (i.e., the speed of the machine is unlikely to be too high at one moment then all of a sudden too low, or the other way around). Practically, the R/C  bit is working more to introduce delays to create corresponding pulses, reflecting specific transitions in the input signal, feeding downstream of the circuit.

All good points and good debate, by the way!

[wasedadoc]

Looking at a datasheet for a CD4030 when powered from 10V Vin low is max 3V and Vin high is min 7V, so depending on the actual supply voltage and the Vout of the first gate the times can be calculated. But for this the value of the capacitor needs to be known. I would have to search for the formula to do so. I do remember that t = R * C, and that after ~5t the capacitor is at near the supplied voltage.

Those 3 and 7 Volt numbers are what TI give as spec limits below and above which the input will certainly be treated as a LOW or HIGH respectively when powered at 10 volts.  In practice the LOW to HIGH and HIGH to LOW transition voltages will be much closer to each other than those numbers suggest.  They will be slightly different between individual ICs and may also vary slightly with temperature.  I have not done an analysis but would not be surprised if the range of actual delay times encountered differed by as much as 20% of the calculated value.

[pcprogrammer]

I have not done an analysis but would not be surprised if the range of actual delay times encountered differed by as much as 20% of the calculated value.

No surprise there when you take component tolerances into account. The resistors will most likely be standard 5% ones and the capacitors used are most likely to have 20% tolerance.

In this part of the circuit it probably did not matter that much, but in the one given in the original post the potentiometers are there for a reason and it might well be to adjust for these tolerances.

Here a bit more about the filters to make the delay. Think Fourier and how a square wave is made up from an infinite set of sine waves with different frequencies and amplitudes. The RC combination filters the sine waves with frequencies above the -3dB point.

[max.wwwang]

I thought I got what's going on here, but probably not (at least not fully).

I would like a bit more discussion about the feedback of the upper half of the circuit through R78 (later maybe more in-depth analysis of the other parts of the circuit).

Assumptions:
Input signal frequencies are NOT so high to make the RC work like a filter, i.e. no bypass of any of the input pulses.

Symbols:
d1: delay on the rising edge of the input by D/R/C
d2: delay on the falling edge of the input (d2 >d1)

I've laid out the characteristic stages of the input signal and the levels (or trends) at points of interest, so we can figure out the current flowing through R78 at each of these stages. The feedback is considered "positive" when there is a current flowing backwards (from right to left), and vice versa. All in the diagram.

What exactly is the purpose of the feedback here?

I guess the most significant moments here are probably when crossing the threshold voltage, as highlighted in green.

Overall, apart from the nuances that R78 might bring into the equation, the function of this circuit is to detect the falling edge of the input and issue a constant width (that of the longer delay) pulse every time when the input signal falls to low.

(Also included is, again, another 'simulated' - by Excel - output of a random input.)

[Edit]

I think now I've figured out, indeed it's like a Schmitt trigger characteristic to reduce the bouncing between L/H when crossing the threshold. But this is only for the falling edge, which is more necessary because it's less steep. Will double check and update with more analysis ...

[max.wwwang]

Here a bit more about the filters to make the delay. Think Fourier and how a square wave is made up from an infinite set of sine waves with different frequencies and amplitudes.

This is no doubt correct.

The RC combination filters the sine waves with frequencies above the -3dB point.

The textbook doctrine may not apply here. In this case, or cases similar to this, the frequencies it blocks (or not) depend on the threshold voltage of the gate.

[pcprogrammer]

The RC combination filters the sine waves with frequencies above the -3dB point.

The textbook doctrine may not apply here. In this case, or cases similar to this, the frequencies it blocks (or not) depend on the threshold voltage of the gate.

The gate threshold voltage has nothing to do with the sine wave frequencies being blocked. The threshold voltage in combination with the RC time are what make up the delay the circuit is designed for.

Mark that I mention sine wave and not square wave. I know it is semantics, but what I'm trying to get across is that any RC combination is a filter, no matter the intent of the circuit. Sure it can be used to make a delayed signal, which is done in this case.

I would like a bit more discussion about the feedback of the upper half of the circuit through R78 (later maybe more in-depth analysis of the other parts of the circuit).

.......

I think now I've figured out, indeed it's like a Schmitt trigger characteristic to reduce the bouncing between L/H when crossing the threshold. But this is only for the falling edge, which is more necessary because it's less steep. Will double check and update with more analysis ...

The circuit with R78 can be seen as a network with two supplies (or sinks) and as such you can do calculations on it.

But a simple view is that when the output of the gate goes high it will slightly raise the voltage at the input and with that make sure that it stays above the threshold until the other supply (essentially the voltage across the capacitor) lowers so much that it falls below the threshold and the output of the gate will then also go low, and with doing this it will drop the voltage at the input below the threshold to make sure it stays below the threshold. It might be that they needed it to suppress some noise and adding this resistor made it stable.

Just like a Schmitt trigger circuit, as you already found out yourself.

[wasedadoc]

1. Thinking in terms of sine waves and their frequencies is not helpful when analysing these RC plus gate delays.  Instead consider the time domain. Start with zero voltage on the capacitor and then apply a voltage step to the input R.  Any decent textbook on circuit analysis will show the derivation of the formula for the voltage on the capacitor after a time t.

Vout = Vin(1-exp(-t/RC))

Where Vin is the height of the step and exp() means e (that 2.718 ... number) raised to the power of the number in the ().

Using that formula it is possible from R and C to compute the time to reach a target voltage or conversely to compute the RC product to reach a target voltage after a desired delay.  For example if the target voltage is 50% of the step height then

Vout/Vin = 0.5 = 1-exp(-t/RC)
exp(-t/RC) = 0.5
take natural logarithm of each side
-t/RC = -0.693
RC=t/0.693 or t = 0.693RC

The same analysis holds if we start with the voltage having been applied for a sufficiently long time that the capacitor has been fully charged and then it is changed to zero so that the capacitor discharges through the resistor.  Vout = Vin(exp(-t/RC))

2.  Despite sine waves and their frequencies not being used in the above, the inverse of frequency, that is period, does need to be considered if the input is not a single step but a sequence of pulses.  Clearly if the input LOW and HIGH times are too short then the capacitor does not reach the starting conditions assumed above.

3.  The 20% figure I wrote above was not because of the tolerances on the R and C.  It was the uncertainty of the logic gate's threshold voltage.  The spec says that worst case it can be anywhere between 3 and 7 volts when powered at 10 volts.  It is more likely to be nearer the middle of that range than the extremes but it will not be exactly the same for every individual chip, even if the same type number from the same manufacturer.

[feedback.loop]

Please next time try to make the subject line more specific.
Thank you.

[max.wwwang]

Please next time try to make the subject line more specific.
Thank you.

Feedback taken. 

[wasedadoc]

Re the changed title in the topic list.  In a sense there are no digital signals.  All practical signals have analogue characteristics but may be conveying digital information.  Considering their analogue requirements becomes increasingly important as the bit rate increases.

[max.wwwang]

Double checked and can confirm what I said earlier as correct. Tried to derive the formulas but found my math is a bit rusty  ,  so will need to refresh my calculus with a textbook before I'm able to do that  (but I will do it!). Notwithstanding this, qualitative analysis suffices here.

Have included the equivalent circuits at the start of several significant periods. Simplification has been made to make it clearer: when the diode is on, the resistors in parallel are ignored due to their significantly greater resistance than 10k (assuming the pot is also a big one). Have also included the revised timing diagram.

I said that the moments when the threshold voltage is crossed are significant. That's correct. But the second transition is more so, because of --- instinct tells me --- the change of direction of the feedback current before and after the crossing. That moment is now highlighted in orange to indicate its greater significance.

(You will need to excuse the messy and inconsistent component numbering because this is automatic and out of my control.)

[max.wwwang]

The gate threshold voltage has nothing to do with the sine wave frequencies being blocked. The threshold voltage in combination with the RC time are what make up the delay the circuit is designed for.

Mark that I mention sine wave and not square wave. I know it is semantics, but what I'm trying to get across is that any RC combination is a filter, no matter the intent of the circuit. Sure it can be used to make a delayed signal, which is done in this case.

We are talking about different things when both referring to "frequency". You are talking about the invisible sine waves making up the square wave. I'm talking about the visible and apparent square waves. If sine waves, or bypassing or blocking thereof, of course it has nothing to do with the gate characteristics.

The circuit with R78 can be seen as a network with two supplies (or sinks) and as such you can do calculations on it.

But a simple view is that when the output of the gate goes high it will slightly raise the voltage at the input and with that make sure that it stays above the threshold until the other supply (essentially the voltage across the capacitor) lowers so much that it falls below the threshold and the output of the gate will then also go low, and with doing this it will drop the voltage at the input below the threshold to make sure it stays below the threshold. It might be that they needed it to suppress some noise and adding this resistor made it stable.

Just like a Schmitt trigger circuit, as you already found out yourself.

Emm, yes. Everyone will have their own best way of intuitively, or theoretically, understanding what is exactly going on here.

I just find it not very helpful to stop with merely saying the feedback either raises or lowers the input, as the case may be, as if some magical parcels are being sent by a magician as we wish. I need something more concrete than that.

[max.wwwang]

1. Thinking in terms of sine waves and their frequencies is not helpful when analysing these RC plus gate delays.  Instead consider the time domain. Start with zero voltage on the capacitor and then apply a voltage step to the input R.  Any decent textbook on circuit analysis will show the derivation of the formula for the voltage on the capacitor after a time t.

Vout = Vin(1-exp(-t/RC))

Where Vin is the height of the step and exp() means e (that 2.718 ... number) raised to the power of the number in the ().

Using that formula it is possible from R and C to compute the time to reach a target voltage or conversely to compute the RC product to reach a target voltage after a desired delay.  For example if the target voltage is 50% of the step height then

Vout/Vin = 0.5 = 1-exp(-t/RC)
exp(-t/RC) = 0.5
take natural logarithm of each side
-t/RC = -0.693
RC=t/0.693 or t = 0.693RC

The same analysis holds if we start with the voltage having been applied for a sufficiently long time that the capacitor has been fully charged and then it is changed to zero so that the capacitor discharges through the resistor.  Vout = Vin(exp(-t/RC))

Inspired by the formulas, had a crack on this case. With simplifications as illustrated, I've got the formula for voltage across C over time for stage (2). From here, it's not too difficult to figure out time needed for the capacitor to reach any given voltage (between 0 and V*).

So this is the result of a quantitative analysis.

[Edit] * If we are going to be really precise, Vc will never reach V, but rather always less than V because of the ever-going current through all of the three resistors, hence the voltage drop on the first R1 (LHS of C). To be even more precise, its theoretical maximum (or "limit" in mathematical language) is the voltage at that point of the voltage divider formed by the three resistors, that is V/r (this means "between 0 and V" above should read "between 0 and V/r").

As TimFox rightly pointed out in this thread, C will never be "fully charged" in any finite amount of time, "only approach[ing] an asymptote". (This is so even in the simplest textbook RC charging circuit.)

[pcprogrammer]

And here I think you went wrong. See this thread for info about "Thevenin Equivalent"

The RC time is not based on the 10K resistor, but the resulting resistance of the parallel and series resistors.

That is why I wrote about calculations on networks in the earlier post where I gave a simple view on the positive feedback.

There are several ways to approach such networks. You can use Kirchhoff's laws or use Thevenin's equivalent or Norton's theorem.

[max.wwwang]

And here I think you went wrong. See this thread for info about "Thevenin Equivalent"

The RC time is not based on the 10K resistor, but the resulting resistance of the parallel and series resistors.

That is why I wrote about calculations on networks in the earlier post where I gave a simple view on the positive feedback.

There are several ways to approach such networks. You can use Kirchhoff's laws or use Thevenin's equivalent or Norton's theorem.

That's exactly the same problem.
I'm not sure if my formula is misunderstood. Nonetheless, I've updated its form only to make it clearer.

[pcprogrammer]

Yes, and your adjustment still feels wrong. It has been to long since doing this kind of math, but you are using C * R1, which is not the correct base for doing the calculations.

The numbering of your resistors is wrong for proper formulating this, but since both 10K resistors are named R1 and of the same value I'm using it in both terms.

The RC time in this case is C * ((R1 * (R1' + R2)) / (2R1 + R2))) Due to the fact that R2 is big compared to R1 the difference is not that big. Only ~120 Ohms.

The capacitor will only charge to the Thevenin equivalent voltage, which is calculated by V * ((R1' + R2) / (2R1 + R2)), which is only slightly less then V.

These are the values to use in the calculation for determining the voltage across the capacitor over time.

Edit: to explain, the resistance to use for the RC time is also based on the Thevenin equivalent of them being in parallel, that is R1 is parallel to the series resistance of R1' and R2.

[wasedadoc]

1.  I think we are agreed that the charge and discharge of the capacitor are not symmetrical and it is the longer one (diode path not operating) that is of interest.  In which case it is the discharge curve you should focus on.

As advised by pcprogrammer you ned to calculate the source voltage and resistance equivalent to the resistors you have and the voltages applied to them.  When the HIGH to LOW threshold is reached and the gate changes state the equivalent circuit will change and so will the discharge curve.  It will be slightly faster but that is not really of any consequence if it is only the delay to the switching time that you are working out.

2.  It is true that in theory the capacitor never becomes fully charged or discharged.  However the discrepancy from the asymptotic value becomes small.  Below is the percentage discrepancy for some values of t= nRC:

n=1:  36.8%
n=2:  13.5%
n=3:  4.98%
n=4:  1.83%
n=5:  0.67%
n=6:  0.25%

[max.wwwang]

Yes, and your adjustment still feels wrong.

Thanks for your use of "feel" now. You are entitled to have your feelings, whatever they might be! 
Just to be absolutely clear, I'm not saying 100% absolutely the formula I reached is correct. I can be wrong! 

It has been to long since doing this kind of math, ...

That's all good. Same here. Most of us are probably not mathematicians I would guess.

..., but you are using C * R1, which is not the correct base for doing the calculations.

Don't quite get this, since there is an "r" in the equation.

The numbering of your resistors is wrong for proper formulating this, but since both 10K resistors are named R1 and of the same value I'm using it in both terms.

I'm OK with that. Here R1/R2 are not meant to be numbering, but rather variables for the resistance to make it (a little bit) more generic. Since the two resistors have the same value, they are represented by R1, which is OK to me. This even does not lose the generality for the cases when the R's at the LHS and RHS of C are different.

What I have done is simply 1) a specific definition of the problem, based on reasonable simplification from the real world one, and 2) tackle that defined problem with mathematical methods and electronic rules. Simple as that. There is no intention to be perfect or cover cases beyond what has been specified.

The RC time in this case is C * ((R1 * (R1' + R2)) / (2R1 + R2))) Due to the fact that R2 is big compared to R1 the difference is not that big. Only ~120 Ohms.

The capacitor will only charge to the Thevenin equivalent voltage, which is calculated by V * ((R1' + R2) / (2R1 + R2)), which is only slightly less then V.

Don't completely get this. But I didn't say that the final Vc will be less than V, at a greater magnitude than it should be (according to the formula and the values of the components).

These are the values to use in the calculation for determining the voltage across the capacitor over time.

Edit: to explain, the resistance to use for the RC time is also based on the Thevenin equivalent of them being in parallel, that is R1 is parallel to the series resistance of R1' and R2.

Elaboration or, even better, step-by-step derivation would be great. But, of course, no obligations!

Only one point, I get the point of resistors in parallel. But note that it's only one 'branch' of the parallel that's charging the C.

[max.wwwang]

1.  I think we are agreed that the charge and discharge of the capacitor are not symmetrical and it is the longer one (diode path not operating) that is of interest.  In which case it is the discharge curve you should focus on.

Correct, that has been agreed on. But the charging stage happens to have been chosen for a quantitative analysis. This is not to say this stage (as the subject of the quantitative analysis) is more significant. It's not too long a way, from here, to a similar formula (or formulas) for that (more significant) stage, if need be.

As advised by pcprogrammer you ned to calculate the source voltage and resistance equivalent to the resistors you have and the voltages applied to them. ...

Dont' quite get this. What I did is based on first electronic principles (that is from scratch). I don't understand, in that approach, why I need to calculate anything like "equivalence".

...  When the HIGH to LOW threshold is reached and the gate changes state the equivalent circuit will change and so will the discharge curve.  It will be slightly faster but that is not really of any consequence if it is only the delay to the switching time that you are working out.

This is true for that stage, but not for this (stage 2) as the subject of the current analysis. There is no dispute about that from me (with regard to that stage).

2.  It is true that in theory the capacitor never becomes fully charged or discharged.  However the discrepancy from the asymptotic value becomes small.

Good to hear that. We are in agreement. By the way, I didn't say anything that can be read as the discrepancy will not become small. 

Below is the percentage discrepancy for some values of t= nRC:

n=1:  36.8%
n=2:  13.5%
n=3:  4.98%
n=4:  1.83%
n=5:  0.67%
n=6:  0.25%

I have not done the math here. But I presume you are referring to the basic textbook RC charging circuit here? In that case, not a problem!

However, correct me if it's not the case and please elaborate. 

[pcprogrammer]

To gain some insight in why the equivalent voltage and resistance just take a look at this video.



Or read this explanation about it.

Also a google (or other search engine) search can shed a lot of light. Gives for instance the wiki page about Thevenin.

Look into "solving electrical networks" for other theories and laws. I mentioned some of the big names before.

By the way the video and the article where mentioned in the thread I pointed to earlier.

[max.wwwang]

To gain some insight in why the equivalent voltage and resistance just take a look at this video.
...

Thanks again. But can I ask you --- have you realised my formula is exactly what's been given in the video? (Just put "R1+R2" into "R2" of the equation of the video). For convenience, I've attached a snapshot of that equation as well as the associated circuit.

By the way, I was well aware of these methods (though I used a harder one than this --- I used the differential equation approach but gosh I got the same result  ).

[Edit: Just to be honest and straight --- although I did know these methods, I don't recall using them in problems like this before. But my memory often fails me, I know!]

But thanks for these resources anyway! 

This is useful because now I'm reasonably sure that my formula was correct! 

[max.wwwang]

I think the upper half of the circuit in the OP has been resolved satisfactorily without dispute (hopefully). I'm now looking closely into the lower half (attached here again for convenience --- but excuse me for the change in numbering).

The LHS of it (in the red dash line box) is very simple now, so does not need more attention. The RHS (in the blue dash line box) looks similar but is different because C is serial in line, not wired like a bypass capacitor.

I've included a manual simulation of it, along with the LHS, to show what the who thing does between the input N1-3D-4 and the output N1-4C-8. Being normal low, it gives a constant width pulse (determined by C20 and R70) for the falling edges of the input.

(Again, one assumption here is that the input pulse widths are big enough to accommodate the delays of RC both ways, rising or falling.)

As we know, when C20 is charged, then when its LHS suddenly falls to L, its RHS will immediately fall to -V (V as the voltage for H, -11V here). Although for this scenario the discharge of C will be fairly quick (because D is ON so the RC constant is small), pin 9 of U9C will momentarily 'see' a negative input voltage -V (assuming its input impedance is high). If ignoring its input voltage limit, this negative voltage will be interpreted as L.

But there is a range of voltage that the input must not go beyond. This is in the "absolute maximum ratings" of the Toshiba TC4069BP chip. Its input range goes down only to Vss-0.5, which is 0.5V [Edit: -0.5V]. (Snippet of datasheet included.)

The question then is, why is the circuit designed this way without fearing that this negative input voltage (beyond the absolute maximum rating) may damage the chip?

I have carefully checked the PCB and am sure the circuit shown correctly reflects the board.

[wasedadoc]

See the schematic https://www.alldatasheet.com/datasheet-pdf/pdf/50860/FAIRCHILD/CD4069.html


The input has protection diodes and there is that external series 220k resistor. The FETs experiences only small voltages beyond the rails and the currents in the diodes are acceptably low.