Hi everyone, can anyone say,
What should be the clearance/isolation between a GPS chip antenna and 1621 MHz patch antenna in PCB layout, to reduce the interference of received signals?
Thanks in advance.
Simulation, simulation, and simulation. That is how you find out. This depends on a lot of things, and someone with a lot of experience might be able to look at something and go "that'll probably be fine", but the only way to be confident in it is to simulate.
Is the 1621MHz patch transmitting, or just receiving?
If it's transmiting, you'll need significant separation to avoid overloading the first LNA of the GPS receiver. If it's receiving, the biggest issue will either be detuning of the GPS chip antenna, or unintentional transmission (via LO leakage) from the 1621MHz patch.
The patch antenna is both transmitting and receiving.
Can you tell me the range of separation between both antennas, is it in mm or cm or m range?
There are no simple answers to this.
The RF coupling between the two antennas will be both radiated(near field) and conducted. Hence hard to calculate.
The duty cycle of your tx will have a be effect. So long as its not damaging the GPS should recover when the tx is off.
The out of band emmisions will have an effect.
The input filtering of the GPS engine will have an effect. Note you can possibly add a SAW filter to help with this.
Through bitter experience, i know that GPS engines are sensitive to on board interference from other high frequency signals on board such as clock harmonics etc. Take great care with layout and earth loops and decoupling. Etc etc.
Can anyone tell me
The circuitry involved in interfacing a single dual-band antenna to two different modules in a single circuit
Thanks in advance
@odgen
I request you to elaborate more on the circuitry.
Will the circuit have diplexer and its supporting circuitry ?
Can you please provide me any resources or reference design for understanding the hardware involved
I request you to elaborate more on the circuitry.
Will the circuit have diplexer and its supporting circuitry ?
You are
requesting me to elaborate you circuitry? On what grounds? I am not your slave LOL
p.s. I gave you direction:
diplexer. Supposing that you study subject and use your head to think how it can possibly solve your problem. If you have further questions regarding
diplexer specifics - I will not hesitate to share my knowledge as far as I know.
I request you to elaborate more on the circuitry.
That really isn't how this forum works. As Ogden said, the bulk of the design needs to come from you, after which this is an excellent place to seek review and suggestions.
You're not going to find one 'off the shelf' solution that perfectly matches your requirements. The optimal implementation for your application will depend on a lot of factors, including the following for each band:
- Maximum transmit/receive power
- Signal bandwidth
- Maximum allowable attenuation
- Out of band rejection required
- Physical available size/weight for diplexer
- Device operating temperature constraints
- ...etc
Hi,
I am not sure on the following two issues, could any one tell if I can perform these in my layout design:
a. Can I draw RF traces near tin plated steel mounting holes?
b. Can anyone tell me the issues faced if RF traces of different frequency travel on the same layer with a clearance of approximately 4 mm?
If Yes, Any precautions to be followed while performing the above??
Regards,
Simulation, simulation, and simulation.
any suggestion on software simulation?
For my work I use "professional" tools, by which I mean tools that are unfortunately outside of the budget of the average hobbyist.
For full 3D simulation we use HFSS - transitions from high metal layers to the gate/drain/source connections of the transistors on chip. Full verification of system before tapeout but these are simulations that take days or weeks. Non-planar structures such as wave guide launchers, SIW, etc.
General RF design is in Keysight ADS/Momentum. This is also the tool where we put everything together (either this or in Cadence Virtuoso). Things we use this for would be on-chip inductors and transformers during the design (once we have a design that seems to work, we use HFSS to do a full 3D simulation to make sure, but this takes a lot longer). I've also used it for distributed filters and matching networks. This is the core tool I use for doing PCB transmission lines - We would put a rough idea of the transmission line in Altium or Allegro, and then export the design and put the actual line in with ADS so we can verify and simulate performance.
I have little experience with "free" tools, though I hear a lot of people talk about QUCS. I've never used it myself, so I don't know if it is actually any good. The pictures I've seen look like it is going after a free version of ADS.
To be clear, the problem with the OP's questions are that they are looking for a black and white answer to a scenario with so many unknowns.
It's like trying to assemble a 1000 piece jigsaw puzzle, but you only have two pieces.