Siglent SDS2000X Plus

[tautech]

So this begs the question does the OEM Siglent Logic Analyzer display this kind of behavior?

Maybe tautech can do a quick test for us

Best,

Sure but latererer as have another project on for a few hours........

[oz2cpu]

now with 4ch, they track just fine, and the jitter is exactly the same on them all,
I trig on analog ch1

[oz2cpu]

and see the difference, here i trig on D1
now all digitals are perfectly stable to each other, but the analog jitter

[tubularnut]

With SPL2016.

[oz2cpu]

cool tubularnut
and please try trig on D0
now you see the analog go blury ? and jitter, the same as the digitals did,
I say your jitter is exactly the same, try using the same 10nS / div

[tubularnut]

Ok, looks very similar.

[oz2cpu]

exactly the same.. I hope most people use the LA with together with Analog channels on slow stuff, since then it is not that visible.

[tubularnut]

... and in case there is any doubt as to what I was using.

Also I know it’s not the best connection for signal integrity or impedance matching, but just using what I had to hand.

[oz2cpu]

tubularnut ?
how do you think the scope shell is assembled ?
glue ? ultra sonic welded ? or just a screw under the sticker ?
we are dying to see one, inside, nice close ups :-)
possible also of the lock and press mecanics.

[DL2XY]

The oem probe should behave the same.

As Thomas already mentioned in the video the +/-2ns jitter is normal due to the 500Mhz sampling frequency of the digital acquisition.
And of course you will see this jitter on all analog channels if trigger on a digital channel.

@Thomas
I believe your divider is overcompensated. In the video you got -16ns skew a about 4ns risetime, now at 13ns risetime it is only -8ns skew.
The skew should be independent of risetime at approximatly -4ns. This value is due to the missing coax extension between adapter and pods on the oem probe.
It can be eleminated by deskew setting of digital inputs.

edit:
@tubularnut
Just saw your reply. Seems like you also have -4ns with the oem probe. How long was the coax from tee to C1 input?

[tubularnut]

tubularnut ?
how do you think the scope shell is assembled ?
glue ? ultra sonic welded ? or just a screw under the sticker ?
we are dying to see one, inside, nice close ups :-)
possible also of the lock and press mecanics.

I will have a closer look tomorrow evening as I am out during the day

[rf-loop]

is there an official bug reporting thread somewhere ?
that siglent monitor ?
maybe here on eevblog ? or somewhere else ?

I think i found a bug,
my siglent SPD3303X got odd random time delay between analog channels and logic analyzer.
or ? am i doing something wrong here ?
or is this really how it is supposed to be ?

https://youtu.be/WzokRBxDM-g

PS: i am using my own logic analyzer input pcb, but as you see now with my latest speed trimmed resistor values
the digital to digital channels are perfectly fine, with in 2nS jitter = normal = the time resolution for LA.

This should be very easy to recreate, 25MHz 5V signal

Can you explain why you think there is some kind of "bug" in scope.
When your trigger come from D0-15 this trigger engine is based to simple 0-1 transition. Detector is simple comparator with some hysteresis and user settable threshold.  Sampling interval 2ns (500MSa/s). One sample occur below threshold and with next one level is crossed over threshold, more or less.  There is available only this information and so there is nothing for adjust this analog signal position. We really do not know where inside 2ns period this threshold have crossed and more... signal is just 1 or 0. There is no information for make fine interpolation.
Of course if we really know that this analog signal is perfectly same what digital channel see, we can think it is possible to do nice image where analog signal image is fake adjusted for nearly zero jitter. But how it works when analog channel signal is not at all from same what is going to digital channel.
Without further evidences and with these displayed "data". Looks like  the "bug"  is more in understanding how oscilloscope works and not inside oscilloscope.   
Other note, about skew adjustment do not work when only digital channels are in use. Skew between what signal.

Also it looks bit weird that diy LA probe things are all handled here is common SDS2000XPlus thread. My opinion is that it is lot of better if whole this thing have its own thread... but accident have happen so walking back to history and change it...

This LA Diy project is interesting and nice project so I think it earn its own thread where these things can keep concentrated to just it.

[tubularnut]

edit:
@tubularnut
Just saw your reply. Seems like you also have -4ns with the oem probe. How long was the coax from tee to C1 input?

Yes, I realised the length of the coax would affect the reading after I posted. It was approx 75cm. LA lead is approx 1 meter.

Taken again with coax replaced by coupler (5cm) at 10kHz. Of course, LA lead is still 1 meter.

Also view at 10Mhz

[rf-loop]

How is your digital channel state threshold level.
If you adjust it  (using custom threshold) , you can see how it affect.

[tubularnut]

How is your digital channel state threshold level.
If you adjust it  (using custom threshold) , you can see how it affect.

Thank you.

Digital threshold was set to 1.6V, same as the analog channel.

If I bring the digital threshold down to 1.13V, I can get the skew to zero on rising and falling edge 

[tubularnut]

tubularnut ?
how do you think the scope shell is assembled ?
glue ? ultra sonic welded ? or just a screw under the sticker ?
we are dying to see one, inside, nice close ups :-)
possible also of the lock and press mecanics.

The cases appear to be ultrasonically welded, so it would be destructive to get a look inside, sorry.

[tautech]

So this begs the question does the OEM Siglent Logic Analyzer display this kind of behavior?

Maybe tautech can do a quick test for us

Best,

Sure but latererer as have another project on for a few hours........

Digital trigger analog channel jitter ? 

Test setup:
SDG1032X BNC to croc leads
3.3Vp-p
40ns pulse @ 150 KHz ......16.8ns rise and fall times.
SDS5054X SDS5104X 
SPL2016



Yes there is some digital to analog jitter but where from ?
Both units NOT referenced so one thinks system jitter.
Some infinite persistence and cursors:

[rf-loop]

Of course there is jitter between digital and analog when trigger is in digital channel. It is how it works.
There is no way to fine interpolate/fine adjust analog channel  because trigger is from digital. There is no data for fine interpolate between true sample points. Digital side most fast sample interval is 0.8ns in SDS5000X. And 2ns in SDS2000Xplus


Now just pen and paper and plot sample points and when you randomize these related to true input signal you can see where from come system jitter. Only way to reduce this jitter is rising digital channel sample speed. Basic jitter is +/- 1 sample interval. In digital side there is no way to fine interpolation trigger (signal placement) between true sample points. When trig is in digital side analog signal position can walk where ever between these samples. Information for placement can not produce from nothing.
Nearly as hard fact that energy can not develop from nothing. Naturally there ia also something more jitter than just this ideal minimum jitter what is just based to sample interval.

Analog channel trigger engine works totally different. And when use it, now this digital channel sample interval jitter is in digital side. Pen and sheet of grid paper and thinking is most advanced problem analyzer. 

Of course in real world there is then some other jitter mechanism what are then included in total jitter. Starting from not ideal digital channels trigger comparator and ... couple of other things.

[oz2cpu]

comments to

#2484
>I believe your divider is overcompensated. In the video you got -16ns skew a about 4ns risetime, now at 13ns risetime it is only -8ns skew.

Dont look at the fixed skew, i played with the settings in the deskew menu, and i expect all other users will do the same, it is a cable length compensation factor,
none of us will use the same factor here.

---

#2486
>Can you explain why you think there is some kind of "bug" in scope.

the 2nS digital time resolution i understand and accept.
BUT the bug as i see it, is the RANDOM time jitter from digital to analog, it is also within the 2nS sample time,
but it is RANDOM, I would expect it to jump in fixed 2nS hops, not anythng in between,
it looks like someone tried to smooth this, or avarage it, by adding random time jitter.

>This LA Diy project is interesting and nice project so I think it earn its own thread where these things can keep concentrated to just it.

YES Agree, there is, mine is here:
https://www.eevblog.com/forum/testgear/diy-logic-analyzer-probe-and-pods-for-siglent-scopes/

but all this is more related to general usage of LA and analogs, and triggers, and skew, deskew adjustment,
the fixed and the random jitter, all this apply (like we have proven) to any type of LA hardware, DIY or original.

----

#2489
>Digital threshold was set to 1.6V, same as the analog channel.
>If I bring the digital threshold down to 1.13V, I can get the skew to zero on rising and falling edge

YES if the incoming wave is with rise/fall times slower that the skew, changing digital trigger point, will "move" the curve seen on screen in time,
however this is not the right way, better to have the trigger in the middle and use the deskew feature to correct the cable length difference.

---

#2490
>The cases appear to be ultrasonically welded, so it would be destructive to get a look inside, sorry.

darn it.. but thanks alot for looking into it anyways,

---

#2491
>Yes there is some digital to analog jitter but where from ?

YES your jitter looks the same as all ours, about 2nS and random,
you would expect it to be in fixed 2nS jumps.

This scope got a VERY fast timebase, to be used for its very fast scope features, however when combined with LA
the user must use a timebase of max 50nS/div or even better 100nS/div, this the random jitter is completely gone (invisible)

and we can focus on our real work and debugging of our hardware and software designs :-)

[rf-loop]

#2486
>Can you explain why you think there is some kind of "bug" in scope.

the 2nS digital time resolution i understand and accept.
BUT the bug as i see it, is the RANDOM time jitter from digital to analog, it is also within the 2nS sample time,
but it is RANDOM, I would expect it to jump in fixed 2nS hops, not anythng in between,
it looks like someone tried to smooth this, or avarage it, by adding random time jitter.

Of course it is random. If it is not random then I am very alarmed what is going on there.

My small suggestion was  previously: "Take just pen and grid paper and plot sample points using imagined signal edges and randomize these fixed interval samples position in every acquisition  (not synchronous with input signal) not digital side nether analog side. Sampling clock walks its own rhythm.  There come time to sample, digital signal is just below threshold... then come next sample and it is over threshold = trig. But it can not know if sample before threshold was just below threshold or just 2ns before - random position!  Analog signal run there also.. but digital side trigger can occur up to 2ns wrong place. And how wrong it is, it is random. So analog signal have random position jitter. Signal true rising edge can be where ever inside this 2ns if all works ideally. Naturally there is also some other things what add sjome jitter so in practice it is more.
I do not know any method to remove this jitter. If not like this "fat" edge then turn scope acquisition to slow acquisition mode instead of fast mode. But jitter itself stay, but in one TFT screen only one acquisition..

[2N3055]

@oz2cpu

Some good thinking but not taking everything into account.
Let's recap:
Input signal connected to digital ch, wil get quantized to 2ns, so incoming edge will be detected on either neighbouring sampling intervals of digital input. When looking at input signal that  is not phase coherent with the scope (as it won't be), that edge will jump around 2 ns.

In addtion to fact thet  analog signals having 4x quicker sampling rate that gives sampling period of 500 ps, by virtue of being analog, they also can interpolate between samples, and indeed, Siglent is using interpolator that allows estimating trigger position on order of 2-10 ps, much better than sampling rate itself.

So when you're triggering from analog channel you get exact trigger time position. For same signal in parallel, digital channel can only decide for sampling edge before or edge after, depending on where exactly edge is...So it will jitter back and forth..
Sa will any system that has two separate clock domains.

If you will, you can also look at this a resampling signal coming in with one clock being resampled with another system that has different sampling clock with fractional ratio to original clock. And you have quantization errors, showing as jitter.
Analog channel has interpolation, and can extract subsampling resolution and recover original timing information

[DL2XY]

#2484
>I believe your divider is overcompensated. In the video you got -16ns skew a about 4ns risetime, now at 13ns risetime it is only -8ns skew.

Dont look at the fixed skew, i played with the settings in the deskew menu, and i expect all other users will do the same, it is a cable length compensation factor,
none of us will use the same factor here.

You are complaining on 2ns jitter but ignoring more then 10ns variable timing error due to impulse response of the voltage divider?

#2486
>Can you explain why you think there is some kind of "bug" in scope.

the 2nS digital time resolution i understand and accept.
BUT the bug as i see it, is the RANDOM time jitter from digital to analog, it is also within the 2nS sample time,
but it is RANDOM, I would expect it to jump in fixed 2nS hops, not anythng in between,
it looks like someone tried to smooth this, or avarage it, by adding random time jitter.

This "randomnes" is simply the interference between the input signal frequency and the samplerate, strobed by display rate.
If you use a signal which is phase coherent to samplerate the jitter reduces to about 45ps.

[oz2cpu]

>This "randomnes" is simply the interference between the input signal frequency and the samplerate, strobed by display rate.

YES and the fact that digital 500MHz clock, and 2GHz analog part clock, is NOT from the same main source,
they are free running, that is the only way I can explain the digital to analog part , sub pS jitter, in compleete random time.

if this is a wanted "feature" or ignoring in the long run, I dont know yet,
how is this on other brands ? I can surely compare at work with R&S and other brands too

[DL2XY]

>This "randomnes" is simply the interference between the input signal frequency and the samplerate, strobed by display rate.

YES and the fact that digital 500MHz clock, and 2GHz analog part clock, is NOT from the same main source,
they are free running, that is the only way I can explain the digital to analog part , sub pS jitter, in compleete random time.

if this is a wanted "feature" or ignoring in the long run, I dont know yet,
how is this on other brands ? I can surely compare at work with R&S and other brands too

The clocks must be from the same source.  Look at this: Triggered on a digital channel, signalgen synchronized to scope clock, 50Mhz/1ns . There is absolute no jitter visiable!
There is still a variable delay from 0 to 2ns, but it stays stable even if changing timebase.

2Ghz and 500Mhz clocks are coherent but not time-synchronized.
Maybe in a later firmeware release it will be possible to resync the 2Ghz to the 500 Mhz?

Edit: 2nd screenshot with unsynced siggen to compare

[2N3055]

>This "randomnes" is simply the interference between the input signal frequency and the samplerate, strobed by display rate.

YES and the fact that digital 500MHz clock, and 2GHz analog part clock, is NOT from the same main source,
they are free running, that is the only way I can explain the digital to analog part , sub pS jitter, in compleete random time.

if this is a wanted "feature" or ignoring in the long run, I dont know yet,
how is this on other brands ? I can surely compare at work with R&S and other brands too

Did you ignore my post or didn't understand me?

Problem is because external signal clock and scope clock is not from the same clock domain.
It is resampling of one frequency with other frequency. Scope digital channels are asynchronously sampling input signal.
There will be rounding errors.

Of course scope digital and analog clock source is same, divided by different divider.

But analog oscilloscope is time domain instrument and it will try to follow input signal as good as possible.
Since analog channel possesses accurate reconstruction of signal, it can, in fact, very accurately estimate where signal passed through the trigger point, and it will adjust (in time) signal representation on the screen. So it is sampling at 500 ps intervals, but internal scope timebase has sub ps resolution, and will shift signal representation to the exact place signal is, better than sampling rate.

So phenomenon you see is actual real show how your digital channels see and detect incoming edges. That 2 ns jitter is timing uncertainty of digital edge detection, with signal coming from the outside world..
Analog channel is ideal (lets say so in this case, comparatively) representation of incoming signal, synchronous down to few ps with real life input.

And to answer the incoming question, all (good) digital scope do the same. Some have higher digital sample rate, so uncertainty is smaller. Keysight 3000T also does the same, and funny enough, they draw digital channels traces such that in your case they would use 2 ns thick vertical transition. A solid block, signifying that edge is "somewhere in there".

If you wish I can later take a screen grab to demonstrate it.

And now to why. Well, as you already said before, debugging computer adr/data busses is not really something people do nowadays (unless you're into retro computing, and for that you need 32 channels to start with or more when you include all control signals). For serial busses it's plenty enough...