Trigger JitterThe datasheet specifies the trigger jitter as follows:
• <9ps RMS (typical) for ≥300MHz sine and ≥6 divisions peak to peak amplitude for vertical gain settings from 2.5mV/div to 10V/div.
• <5ps RMS (typical) for ≥500MHz sine and ≥6 divisions peak to peak amplitude for vertical gain settings from 2.5mV/div to 10V/div.
The EXT trigger jitter is not exactly stellar at <200 ps RMS – but then again this is a classical analog (comparator) trigger and not the fully digital trigger system that we get when using one of the input channels as trigger source.
Now let’s verify this with a 1 GHz sine signal from an OCXO-driven AWG (SDG7102A), fed into channels 3 and 4 of an SDS6204 H12 Pro (which has an individual ADC for each channel) via a 12.4 GHz resistive power splitter. This way we can observe the jitter in the trigger channel as well as a not triggered channel, where both are using different ADCs, hence are completely unrelated.
The high quality 1 GHz sine signal has been chosen for its fast edges and low inherent jitter – after all we want to characterize the DSO and not the signal source. See the attached screenshot which has been taken after more than 15 minutes running with infinite persistence:
SDS6204 Pro H12_Trigger_Jitter_1GHz_15m
At a timebase of 100 ps/div, we can see the peak to peak jitter in the triggered as well as the non-triggered channel after more than 15 minutes at infinite persistence.
The jitter measurements are as follows:
Triggered channel: 6 ps pk-pk, 698 fs rms;
Un-triggered channel: 11.3 ps pk-pk, 1.564 ps rms;
Skew Ch.3-Ch.4: 12.06 ps pk-pk, 1.594 ps rms;