How to design with CMOS inverter amplifiers

[Infraviolet]

Ok, so a while ago someone on here suggested to me a trick (sorry, can't remember who, but thank you, it looks like it can be a very useful trick to me)  for amplification of signals too fast for the op amps I had to hand by using a 74HCU04 (or other UNBUFFERED NOT gate chips) in a linear mode.

This involves coupling a capacitor from the signal source to one end of an input resistor, the other end of the input resistor goes to the NOT gate's input, a feedback resistor then runs from the gate's input pin to its output, and the output can then, either with capacitive coupling*, or directly*, be used to provide higher voltage signals to further circuit elements.

*some descriptions seem to show the capacitor on the output, others don't I certainly didn't seem much effect when having it there versus replaced by just a wire, both when the amplifier's final output was driving just an o-scope probe (10Mohm, <12pF), and when it was driving in to a 1K resistor to ground as well as the scope probe. Is there a reason they show it, if one is driving a second stage of CMOS inverter amplification then surely one only needs the coupling capacitor input one would already fit it with if it were acting independently, no need for an extra coupling cap?

National Semiconductor's AN-88 app note covers this concept "CMOS Linear Applications" briefly.

I've been giving it a go and found some odd things and wanted to understand a bit more, but don't know where I can get further info, because AN-88 doesn't say a vast amount (even so much as not giving the equations and full captions you'd expect for its figures), and google searching didn't find me that many full answers, just discussions. This https://wiki.analog.com/university/courses/electronics/electronics-lab-20 also covers some stuff, but not enough either.

I had thought the ratio of the input and feedback resistors will equal the gain, roughly, but I'm finding things very diferent. For a 3MHz sine signal  input(500mV peak to peak) with a 5V and ground power supply for the inverter chip I'm needing resistor ratios of 10s to get gains of 3. I'm also finding things don't seem to depend solely on the ratio, a larger pair of resistors with the same ratio doesn'tgive the same gain, not even close, as a smaller pair. A 1K input and 10K feedback gives a gain of around 3, whereas a 10K input and 100K feedback gives a gain less than 1.

Is there a clear equation governing the gain of a CMOS inverter amplifier, ignoring circumstances where one is trying to gain something to the extent it would come very close to the rail?

Is there some sort of "slew rate" like thing going on here, perhaps controlled by the absolute sizes of the resistances rather than their ratios, where gain is limited for a signal at a particular speed?

Then when I stacked up two CMOS inverter amplifiers with one feeding the input of the next, keeping the coupling capacitors an input resistors so each alone was just the same circuit as a single one acting alone would be, I got a gain from the pair much greater than the product of the gains either had given when used alone.

Are they interacting with each other in some manner, or does the output of one provide some input impedance effect to the next stage despite having an input resistor present?

And I had expected that when the input and feedback resistors were equal I'd get a gain of 1, but instead I found a gain much less than 1, again varying with how big the resistors actually were. Yet when putting two such amplifiers in sequence, the first with a large enough ratio to give a gain and the second with a 1:1 ratio, the final output was nonetheless larger than the gain of just the first stage alone.

Trying to work out empirical equations for whatever is going on would require varying an awful lot of independent parameters it seems, resistance sizes as well as ratios, amplifiers in sequence and alone...

Another thing I found was that within a single chip, I could run two amplifier stage just fine, but if I tried three amplifier stages  then I got a much higher frequency signal(15 to 20MHz maybe) superimposed on the waveform, and when the input signal was weak and one would expect the output to be sitting at close to 2.5V and nearly flat, I instead got this high frequency waveform becoming dominant.

I'm also a bit unsure about the maximum number of elements in the hex chip one should use, a single gate acting in this manner, with the others all grounded on their inputs, has the chip comsuming about 12mA. There is an abs max figure given in most 74HCU04 datasheets of 50mA for the whole chip, and 25mA per channel, but no recommend long term operating maximum. Does this mean I'm ok to run up to 4 gates in this fashion, 4x12<50, or is there a further percentage by which I should try to work below the abs-max current draw? The chip (DIP in breadboard testing, SOIC in my final application) doesn't have any obvious pad for heatsinking if I ought to do that, but I could make the ground and power planes/traces near the chip's suppply pins big with lots of vias if that would be wise?

Can anyone point to resources that give the full details on how to make use of this "Unbuffered CMOS NOT GATE as amplifier" trick, particularly an equation to let one select the most appropriate resistors for a desired gain rather than having to trial-and-error it.

Thank you

[Benta]

You're applying "op-amp" rules to this, where a CMOS inverter actually has a voltage gain of perhaps 3 or 5 or 7 (undefined).
Your spurious oscillations are more likely layout/decoupling related.
Are you one of the poor souls that use "solderless breadboards"? Aka "where's the garbage bin?"

[Infraviolet]

Yes, this is on a solderless breadboard, I know they have issues but it is quicker to test ideas on one than get an actual PCB made for soldering to, or work with stripboard.

If we ignore the strange situation with those fast oscillations, is there an equation for the gain versus the resistances?

[mawyatt]

We've used CMOS Logic Gates as analog amplifiers and limiters since RCA first introduced the CD4000 series way back around 1970. As Benta indicated you can't treat these as infinite gain op-amps, however if you do a little analysis assuming a finite gain G and a high input Z and low output Z CMOS gate you can estimate the closed loop gain as -{(Rf/Ri)G/((Rf/Ri)+1+G)}, where Rf and Ri are much smaller than the CMOS input Z and larger than the CMOS output Z, and G is the Open loop ~ midpoint (VDD/2) CMOS Gate small signal gain magnitude.

 With G ~ infinity then the gain becomes -Rf/Ri as expected!! With an Rf/Ri ratio of 10, and G ~ 5, ones aspects a closed loop gain of -3.125.

A little more involved in the details of the internals one finds they are not symmetrical as assumed, the PMOS is weaker than the NMOS. You can observe this by simply shorting the input and output and measuring the resultant DC voltage, it's not exactly VDD/2 as a symmetrical structure would produce. If you look or plot the static transfer (Vo/Vi) you will see a nice smooth compression at the extremes like a soft slanted stretched "S", which can be quite useful in analog signal processing.

BTW you can get the Gain G by taking the slope of the transfer curve around the center VDD/2 point, it's simply (delta Vo)/(delta Vin).

Best,

[tggzzz]

You're applying "op-amp" rules to this, where a CMOS inverter actually has a voltage gain of perhaps 3 or 5 or 7 (undefined).
Your spurious oscillations are more likely layout/decoupling related.
Are you one of the poor souls that use "solderless breadboards"? Aka "where's the garbage bin?"

Beat me to it!

Yes, this is on a solderless breadboard, I know they have issues but it is quicker to test ideas on one than get an actual PCB made for soldering to, or work with stripboard.

Does that "quicker" include the time spent wondering what's happening, writing your post, waiting for responses and responding to them?

The speed of inserting components is an irrelevant metric; what matters is the time to getting a working circuit (or knowing why it cannot work).

You should understand why manhattan techniques enable you to easily and speedily get good electrical behaviour and results.

FFI see examples in the latter part of https://entertaininghacks.wordpress.com/2020/07/22/prototyping-circuits-easy-cheap-fast-reliable-techniques/

Engineering maxim: it is faster to "do it right2 than it is to "do it over".

[Infraviolet]

Mawyatt, thank you very much indeed for that equation. I'll do some more tests and see how well it applies to them.

Closed_loop_gain= ( Rf/Ri )G  / ( (Rf/Ri)+1+G )

[glarsson]

Your spurious oscillations are more likely layout/decoupling related.
Are you one of the poor souls that use "solderless breadboards"? Aka "where's the garbage bin?"

We experimented with CMOS inverter amplifiers in 1977 using a solderless breadboard.  At power on it oscillated in the FM broadcast band, so clearly it didn't work as an amplifier. It produced a carrier detectable over 100 meters away. 

[tggzzz]

Your spurious oscillations are more likely layout/decoupling related.
Are you one of the poor souls that use "solderless breadboards"? Aka "where's the garbage bin?"

We experimented with CMOS inverter amplifiers in 1977 using a solderless breadboard.  At power on it oscillated in the FM broadcast band, so clearly it didn't work as an amplifier. It produced a carrier detectable over 100 meters away. 

If it oscillated, it must have worked as an amplifier!

[glarsson]

If it oscillated, it must have worked as an amplifier!

Ok. It couldn't be used as an amplifier.

[Infraviolet]

From what I've heard that sort of extreme oscillation happens if you try to use unbuffered NOT gates in this manner. I haven't had anything like that with the 74HCU04. That weird oscillation I saw (more like 15MHz than 100MHz) only occured when I used several gates at once in one chip, I'm doing some more breadboard tests today to establish one or two more things before I get PCBs ordered.

[Zero999]

You built it on a breadboard, so have a nice LC oscillator.

Just one question: why? The usual reasons for using a logic gate in its linear region is to make an oscillator, or boost a low level signal up to make a nice square wave. In other words, logic gates are not typically used to amplify a signal to give a nice linear output. That's the domain of op-amps. Logic gates are inherently non-linear. The gain varies depending on the output voltage. It's always higher, when the output voltage is closer to half the supply voltage because the MOSFETs are biased more into their transconductance regions.

[T3sl4co1l]

Don't pay much attention to the poopers poo-pooing breadboards.

Just remember, as is the case anywhere, lead length and dress matters.

Don't use those goofy ten inch premade crimp pin jumper kits.  Cut your own from solid wire, flat to the board or in short arcs.
Mind the effect of capacitance between slots (typically ~4pF).
Mind the effect of basically not ever having ground plane.  You rely on wiring and supply buses (just more wires, they're only strips embedded in the board) for ground quality.
All of these effects can be quantified and accounted for, between theory and practice.

3MHz is not extreme for a breadboard, but you do need to be careful with it.

The main thing is, a random circuit, build on breadboard, with random (as yet undefined -- we need to know before we can tell!) materials and parts, is more likely to perform badly, while a random circuit, built on PCB, is more likely to perform well.  There is no guarantee that either will perform correctly at all.  Only once both are fully defined: that is, including the length and placement of wires, components, etc., and nearby / surrounding / supporting metal (preferably, build your PCB with a ground plane; for the breadboard, mount it on a metal plate and wire that to circuit common/GND), can operation be reasonably anticipated.

I'm quite serious -- get out a ruler and measure the length of those jumpers!  Length matters, because signals propagate at the speed of light, and the in-circuit consequence of that is some capacitance which loads the signal, and inductance acting in series along the wire.  It's a rate of roughly 1 nH/mm.  So those 10" jumpers or whatever they usually are, add up quite quickly (~200nH?) when you're taking MHz signals.

Not to mention, where jumpers make large sweeping arcs amongst each other, there's comparable mutual inductance between them (affecting signal or power quality further, or providing feedback for high-frequency oscillation).  Short links have less mutual inductance to each other, better compartmentalizing sections of the circuit.

Tim

[MK14]

I don't know if the OP, has seen this.  It seems to go into a lot of details, about this amplification technique.

[tggzzz]

...
3MHz is not extreme for a breadboard, but you do need to be careful with it.

The main thing is, a random circuit, build on breadboard, with random (as yet undefined -- we need to know before we can tell!) materials and parts, is more likely to perform badly, while a random circuit, built on PCB, is more likely to perform well.  There is no guarantee that either will perform correctly at all.  Only once both are fully defined: that is, including the length and placement of wires, components, etc., and nearby / surrounding / supporting metal (preferably, build your PCB with a ground plane; for the breadboard, mount it on a metal plate and wire that to circuit common/GND), can operation be reasonably anticipated.

tpd is 6ns, so gain at >>3MHz.

Other construction techniques have a better chance of success; manhattan on a solid groundplane is much better.

I'm quite serious -- get out a ruler and measure the length of those jumpers!  Length matters, because signals propagate at the speed of light, and the in-circuit consequence of that is some capacitance which loads the signal, and inductance acting in series along the wire.  It's a rate of roughly 1 nH/mm.  So those 10" jumpers or whatever they usually are, add up quite quickly (~200nH?) when you're taking MHz signals.

Not to mention, where jumpers make large sweeping arcs amongst each other, there's comparable mutual inductance between them (affecting signal or power quality further, or providing feedback for high-frequency oscillation).  Short links have less mutual inductance to each other, better compartmentalizing sections of the circuit.

Having a look at the datasheet https://www.ti.com/lit/gpn/cd74hcu04 indicates that when an input is at Vcc/2, then the current is ~15mA and the input capacitance is 40pF. The current  falls off fast as the input moves away from Vcc/2.

All that means a surprisingly high (cf opamps) current change, a relatively high (cf logic levels) capacitance, and probably relatively long lead inductance. That's all a recipe for unintended behaviour in a lazily/ constructed circuit.

A simple spice simulation of a current step into a 40pF capacitor and a realistic inductance (200nH?) should yield useful insights as to the potential for oscillation.

[T3sl4co1l]

For reference, I've breadboarded amplifiers and switching circuits using 2N3904s and friends (fT ~ 300MHz) before.  Which go almost as fast, and at comparable bias currents (10mA).  Oscillation isn't at all guaranteed there, either, but keep in mind that might be a single transistor, or few at a time, not an array of six pairs.

In contrast, I once breadboarded a Z80-CPU and a handful of other things, and that, just running at 4MHz (yes yes, implied edge rate some times higher, but it's "only" NMOS, fairly weak drive strength; the TTL bus latches (output ports for blinkenlites) were probably the worst offenders; also being that one had an LED display matrix on ribbon cable hanging off it, heh.  It worked fine for the most part, but would crash randomly -- or not really "random", but also "perfectly" randomly, in that it was reliable/consistent (weeks of uptime blinking out a set pattern) in an earlier version, but a later version I added an LFSR noise generator, after which it might run a day or a week between crashes.  (And it would crash-crash, because it was the NMOS CPU; clock bounces or stops momentarily or whatever it was reading that upset it, and that's it, it's toast, internal state is lost, reset required.  Well maybe CMOS would crash too, I don't know, if it were a fast double-tap, that could corrupt it just as well.  But those are my assumptions anyway.  No way to tell, and actual cause doesn't matter anyway; obviously it's a marginal signal quality issue caused by the breadboard.)

The worst of both worlds, however, was one time I tried breadboarding a -- I think it might've been a type-T flip-flop in ECL/CML?  That most definitely did NOT work: too many transistors, too much gain, it oscillated between stages -- at some 100MHz or so, which is a frequency consistent with lead lengths / propagation delays along such a chain, and node capacitances and all that.  (I eventually later built a variant of that circuit Manhattan-style, which worked beautifully.  It's a rather pleasing circuit, in terms of topology and construction, and might make a good project to investigate and build, if I might so humbly suggest. )

Yet another example, of more direct application / reference here, was one time where I had a ATMEGA32 breadboarded, and wired to an analog (ADC/DAC) board I had put together -- this on ground plane, hand carved / Manhattan style, with SPI leads going back to the breadboard.  Well, those fly leads were a good 10" or so long, and, you guessed it, the data was crap.  Put a ferrite bead on SCK and SDI/O, added a couple more ground wires -- no problem, solid data, reliable readings.  (Which was at a time when I "knew what I was doing", so the problem was easily recognized, verified (there was significant ringing on the signals) and addressed.)  ATMEGA isn't particularly fast (it's 5V CMOS, roughly 74HC scale I think?), but I just wasn't sure if it was fast enough to be a problem here, and it turns out it was -- good to know.

So, the stability, the coupling and risk of oscillation, the general noise levels, all of it gets worse with scale.  Telling someone they can't do a single-gate oscillator or amplifier this way?  Come on, that's BS and y'all know it.  It needs to be done carefully, and let's say might be a good learning opportunity in seeing how wire length matters -- as long as one is aware of the effect, and has the commitment to play around enough to tell -- it does take some effort to replug the circuit, making sure unused gates are tied off, supplies are wired short and well bypassed, signal lines are short and low, etc.  Conversely, if you're not interested in that kind of exploration -- maybe keep it to simpler things, like single transistors, and low bias currents where they don't sing, or add a ferrite bead around the base lead to kill any possibility of it trying.

Tim

[RoGeorge]

If you look or plot the static transfer (Vo/Vi) you will see a nice smooth compression at the extremes like a soft slanted stretched "S", which can be quite useful in analog signal processing.

Such a sigmoid-like function should also work well for making an artificial neuron out of a CMOS gate. 

The coefficients of the neural network (NN) can be calculated on a computer at first.  Once the NN was trained on the computer, then the calculated coefficients can be implemented in hardware, as summing resistors at the input of each gate, a resistor for each summing coefficient.  The resistor's values will encode the NN coeficients.

With fixed resistors (fixed NN coefficients and hardwired architecture) such a NN will have a fixed functionality, but hey, would be fun to make an "analog OCR" (Optical Character Recognition) entirely in hardware, out of a bunch of 4000 CMOS chips and a bag of resistors. 

[tggzzz]

For reference, I've breadboarded amplifiers and switching circuits using 2N3904s and friends (fT ~ 300MHz) before.  Which go almost as fast, and at comparable bias currents (10mA).  Oscillation isn't at all guaranteed there, either, but keep in mind that might be a single transistor, or few at a time, not an array of six pairs.

My latest Philips scope, with a risetime of 200ps, has mainly BC107s in the signal path. There are three transistors with an fT of 2GHz, in the trigger circuit.

Strange, wonderful scope, with controls and measurement artefacts that would confuse most engineers. Basically you are required to visualise the signal you are trying to observe before you can fully observe it. Not a bad discipline

In contrast, I once breadboarded a Z80-CPU and a handful of other things, and that, just running at 4MHz (yes yes, implied edge rate some times higher, but it's "only" NMOS, fairly weak drive strength; the TTL bus latches (output ports for blinkenlites) were probably the worst offenders; also being that one had an LED display matrix on ribbon cable hanging off it, heh.  It worked fine for the most part, but would crash randomly -- or not really "random", but also "perfectly" randomly, in that it was reliable/consistent (weeks of uptime blinking out a set pattern) in an earlier version, but a later version I added an LFSR noise generator, after which it might run a day or a week between crashes.  (And it would crash-crash, because it was the NMOS CPU; clock bounces or stops momentarily or whatever it was reading that upset it, and that's it, it's toast, internal state is lost, reset required.  Well maybe CMOS would crash too, I don't know, if it were a fast double-tap, that could corrupt it just as well.  But those are my assumptions anyway.  No way to tell, and actual cause doesn't matter anyway; obviously it's a marginal signal quality issue caused by the breadboard.)

The pattern sensitive intermittent operation is the worst case, of course. It is bad enough for an experienced engineer to sort it out; a beginner won't have a clue where to begin: is it software, digital, flaky connection. (Intel's first DRAM, the 1kbit 1103, had a reputation for being pattern sensitive. Oops)

My first computer was a 6800 with 128bytes of RAM on several home-made circuit boards, tested using a voltmeter, LEDs and switches. The clock input was non-TTL with strict voltage limits, so before inserting the precious 6800, I looked at it using the university's scope. That taught me about lead length and inductance Terrible construction, but I learned a lot - and that was useful when chatting with engineers during job interviews.

The worst of both worlds, however, was one time I tried breadboarding a -- I think it might've been a type-T flip-flop in ECL/CML?  That most definitely did NOT work: too many transistors, too much gain, it oscillated between stages -- at some 100MHz or so, which is a frequency consistent with lead lengths / propagation delays along such a chain, and node capacitances and all that.  (I eventually later built a variant of that circuit Manhattan-style, which worked beautifully.  It's a rather pleasing circuit, in terms of topology and construction, and might make a good project to investigate and build, if I might so humbly suggest. )

That's an example of why I push beginners away from solderless breadboards and towards better breadboard techniques such as manhattan or deadbug. Those that persist in using solderless breadboards soon find out that manhattan/deadbug is faster. Plus you have to learn which end of a soldering iron is hot

Yet another example, of more direct application / reference here, was one time where I had a ATMEGA32 breadboarded, and wired to an analog (ADC/DAC) board I had put together -- this on ground plane, hand carved / Manhattan style, with SPI leads going back to the breadboard.  Well, those fly leads were a good 10" or so long, and, you guessed it, the data was crap.  Put a ferrite bead on SCK and SDI/O, added a couple more ground wires -- no problem, solid data, reliable readings.  (Which was at a time when I "knew what I was doing", so the problem was easily recognized, verified (there was significant ringing on the signals) and addressed.)  ATMEGA isn't particularly fast (it's 5V CMOS, roughly 74HC scale I think?), but I just wasn't sure if it was fast enough to be a problem here, and it turns out it was -- good to know.

So, the stability, the coupling and risk of oscillation, the general noise levels, all of it gets worse with scale.  Telling someone they can't do a single-gate oscillator or amplifier this way?  Come on, that's BS and y'all know it.  It needs to be done carefully, and let's say might be a good learning opportunity in seeing how wire length matters -- as long as one is aware of the effect, and has the commitment to play around enough to tell -- it does take some effort to replug the circuit, making sure unused gates are tied off, supplies are wired short and well bypassed, signal lines are short and low, etc.  Conversely, if you're not interested in that kind of exploration -- maybe keep it to simpler things, like single transistors, and low bias currents where they don't sing, or add a ferrite bead around the base lead to kill any possibility of it trying.

Agreed.

But the key point is that a beginner simply won't be able to do it "carefully". Hopefully beginners won't be put off by unexplained behaviour and change to something easier such as web front ends

[Infraviolet]

To be clear, I've already made this 3MHz circuit work using both 2N3904s on a breadboard and 2N3904s (SOT23 version) on a PCB, it works well. But I'm investigating using CMOS gates for amplification this way because they let one work with a much lower count of passives, which when one has a lot of separate channels to amplify signals on gives substantial area savings on a PCB, which is pretty useful when the final design of the PCB is going to be used within projects with moving parts and therefore spatial constraints on board size. I'm also expecting that while CMOS won't let me amplify linearly* all the way rail-to-rail, it will let my signals get a bit bigger than with transistors, which will improve the accuracy of the final readouts taken at the end of the amplification and processing stages. And as the CMOS amplification circuit has a natural negative feedback to it I expect it shouldn't have the same potential for performance variation with temperature and randomly scattered device characteristsics(as Hfe is for transistors) that transistors can. I'm already expecting this CMOS version to be more current-hungry than the transistor version is, but it seems worth it for smaller board area and potentially a slightly better accuracy from having a somewhat bigger voltage for the amplified signal.

*The parameter which really matters here by the way is having a linear relationship between the peak amplitude of the input sine wave and the peak amplitude of the amplified one, a distortion of the wave would technically be alright so long as the positive peak height got linearly scaled. As things stand so long as I don't make the gain too high both the CMOS (in some of the tests so far, not in all tests yet, but the gain equation has made it clear how to do better on that front) and transistor versions have kept both a linear relationship between input vs output peak heights and have left the wave shape undistorted.


After breadboarding I'm going to design PCBs for this CMOS version too.

P.S. as beginners go, I'm a "beginner" in terms of having gaps in my knowledge and experience (I'd never used discrete transistors as anything except "digital" type switches and logic inverters until a few months back), but I've been breadboarding, PCB designing, soldering and debugging of projects for many years. I'm certainly not going to quit and take up web design. I defend the solderless breadboard mainly for the ability to change component values faster than one can de-solder (even removing an 0603, though easier than through-hole removal, takes time to do it carefully and not tear off the pad), and because one can completely change a circuit topology to test ideas in a way which isn't posible on a PCB unless you had an absolute f***-tonne of zero-ohm jumper resistors with which to reconfigure the layout.

[tggzzz]

To be clear, I've already made this 3MHz circuit work using both 2N3904s on a breadboard and 2N3904s (SOT23 version) on a PCB, it works well.

To be clear, no you haven't. You have made one circuit using NPN BJT transistors work, and now you are trying to make a second circuit using PMOS and NMOS transistors work.

P.S. as beginners go, I'm a "beginner" in terms of having gaps in my knowledge and experience (I'd never used discrete transistors as anything except "digital" type switches and logic inverters until a few months back), but I've been breadboarding, PCB designing, soldering and debugging of projects for many years. I'm certainly not going to quit and take up web design. I defend the solderless breadboard mainly for the ability to change component values faster than one can de-solder (even removing an 0603, though easier than through-hole removal, takes time to do it carefully and not tear off the pad), and because one can completely change a circuit topology to test ideas in a way which isn't posible on a PCB unless you had an absolute f***-tonne of zero-ohm jumper resistors with which to reconfigure the layout.

With solderless breadboards and DIP ICs you need absolute f***-tonne of zero-ohm jumper resistors inductors to re-configure it before experimenting.

The time/expense taken to layout a PCB and have it manufactured/shipped is noticeable, and worth avoiding where possible. Fortunately it is possible, without resorting to solderless breadboards.

If you are actually interested getting a circuit working soonest, you really need to look at manhattan and deadbug techniques[1]. There are good reasons why those techniques are favoured by experts - and even shipped as proof-of-principle products[2].

[1,2] see the refs in the link I mentioned earlier.

[T3sl4co1l]

(hmm, could use bottom text, not sure what)

[MK14]

N.B. I rewrote your post, for you.

I hate breadboards!

Then, how come, an electronics engineer, who works (or use to), for Tektronix, designing their oscilloscopes (or so I gather/think).  Seems to use them (breadboards):

See here:

[tggzzz]

Breadboards can be fine, and can be similar to using PCBs. Solderless breadboards are problematic

[nfmax]

Shahriar of The Signal Path made an excellent video tutorial (with the assistance of his brother) on exactly this topic - how to understand and analyse the 'CMOS inverter amplifier':

[tggzzz]

N.B. I rewrote your post, for you.

I hate breadboards!

Strawman argument!

I don't hate breadboards; indeed I use them fairly regularly.

So do people that are widely acknowledged to be experts, e.g.:

• Jim Williams' famous LT AN47 “High Speed Amplifier Techniques” http://cds.linear.com/docs/en/application-note/an47fa.pdf especially the tutorial section p26-31.
  
• Or this low noise example is a professional example from Jim Williams’ classic Linear Tech AppNote120 “1ppm Settling Time Measurement for a Monolithic 18-Bit DAC. When Does the Last Angel Stop Dancing on a Speeding Pinhead?”
  
  
• Or this from someone mentioned several times by name in TAoE, showing judicious use of a range of techniques in something he shipped/showed to a customer:
  
  

I do freely and willingly acknowledge that I hate solderless breadboards. And you'll note none of those experts are using solderless breadboards.

Then, how come, an electronics engineer, who works (or use to), for Tektronix, designing their oscilloscopes (or so I gather/think).  Seems to use them (breadboards):

Ah. That's no better than arguing "I walked into a road without looking, and wasn't knocked down", therefore anybody can successfully walk into any road.

[langwadt]

I recognize that board. John Larkin who post on sci.electronics.design made it, he gets blank ENIG boards make for such protos, never tanish and looks pretty

[T3sl4co1l]

Ah yes, changing the goalposts: when people are using "breadboard" in short for the solderless variety, then fake-agreeing with everyone by requiring the specific definition when no one else does.

Also very no-true-scottsman-fallacy to bring up examples that most likely require ground plane. Boards studded with coax connectors? GTFO. That's not what we're talking about here and you know it.

Hm, sadly I didn't take pictures of the setup, but this one was on solderless breadboard: https://www.eevblog.com/forum/projects/simple-induction-heater/
Apparently it's impossible.  Or a variety of other non-critical examples.  Several of which I already gave.

But clearly you aren't operating on logic -- and no number of examples, nor sequence of reasoning, will convince you otherwise.  Sorry.

Tim

[tggzzz]

Ah yes, changing the goalposts: when people are using "breadboard" in short for the solderless variety, then fake-agreeing with everyone by requiring the specific definition when no one else does.

Some people use "breadboard" to mean "solderless breadboards". Other people use "breadboard" to mean a range of prototyping techniques. Being unambiguous helps converstations.

As famously put 170 years ago, presuming "glory" not meaning "knock down argument", hinders conversations.

Also very no-true-scottsman-fallacy to bring up examples that most likely require ground plane.

Yes, using "breadboard" to mean only "solderless breadboard" is a no-true-Scotsman-fallacy.

Boards studded with coax connectors? GTFO. That's not what we're talking about here and you know it.

Solderless breadboards have several problems that can't be addressed by the addition of a groundplane, so concentrating on that aspect only also rates a "GTFO".

I'm talking about the about the problems the OP has had; what problems are you considering?

It looks like the most significant problems relate to RF mis-behaviour, and - as you expounded(!) - long wires and poor decoupling are likely to be a cause. Both those problems are magnified with solderless breadboards and easily minimised by other breadboarding techniques.

If there weren't easy alternatives, then it would be worth putting up with the infelicities of solderless breadboards.

Personally, if there is an easy way to avoid problems, I'll take the easy path. You?

Hm, sadly I didn't take pictures of the setup, but this one was on solderless breadboard: https://www.eevblog.com/forum/projects/simple-induction-heater/
Apparently it's impossible.  Or a variety of other non-critical examples.  Several of which I already gave.

But clearly you aren't operating on logic -- and no number of examples, nor sequence of reasoning, will convince you otherwise.  Sorry.

Clearly you are regarding your experiences (as an expert) as being typical of the experiences of beginners -- and the directly relevant counter-example of the OP's experience won't convince you otherwise. Sorry.

[mawyatt]

Shahriar of The Signal Path made an excellent video tutorial (with the assistance of his brother) on exactly this topic - how to understand and analyse the 'CMOS inverter amplifier':

Thanks for posting!!!

Superb "The Signal Path" video as usual 

Nice to see his brother involved, and he's got a PhD in EE also

This is a must view for anyone remotely interested in CMOS devices and how they behave wrt analog use.

Best,

[Infraviolet]

They are definitely the 74HCU04 type, bought from RS or Farnell.

I've done some (solderless) breadboard tests and the principle seems to work roughly according to that amplification equation, enough I can now be confident enough in overall circuit topology to design a PCB.

I do note though that when multiple channels of a chip are in use as amplifiers there seems to be a "bump" in the amplification on all channels at times when the input on any single channel is a small signal close to 2.5V. Perhaps an effect related to the way that gates draw more current when they are amplifying something which doesn't give an output which comes close to the rails. Or maybe just a consequence of the limited chip decoupling cap arrangement possible with a breadboard, which might disappear once I get a proper PCB for this.

[Benta]

Ah yes, changing the goalposts: when people are using "breadboard" in short for the solderless variety, then fake-agreeing with everyone by requiring the specific definition when no one else does.

Some people use "breadboard" to mean "solderless breadboards". Other people use "breadboard" to mean a range of prototyping techniques. Being unambiguous helps converstations.

As famously put 170 years ago, presuming "glory" not meaning "knock down argument", hinders conversations.

Also very no-true-scottsman-fallacy to bring up examples that most likely require ground plane.

Yes, using "breadboard" to mean only "solderless breadboard" is a no-true-Scotsman-fallacy.

Stop waffling. You've moved completely off-centre. This is not the "house of commons", but an engineering forum.
Semantics have no place, you know EXACTLY what was meant by "breadboard" in previous posts.

[T3sl4co1l]

They are definitely the 74HCU04 type, bought from RS or Farnell.

I've done some (solderless) breadboard tests and the principle seems to work roughly according to that amplification equation, enough I can now be confident enough in overall circuit topology to design a PCB.

I do note though that when multiple channels of a chip are in use as amplifiers there seems to be a "bump" in the amplification on all channels at times when the input on any single channel is a small signal close to 2.5V. Perhaps an effect related to the way that gates draw more current when they are amplifying something which doesn't give an output which comes close to the rails. Or maybe just a consequence of the limited chip decoupling cap arrangement possible with a breadboard, which might disappear once I get a proper PCB for this.

There will be some amount of supply resistance on-chip, which is and is not shared between devices; you can observe this by setting one to fixed 1/0 output, and seeing if the level varies with load on nearby or other gates.  Probably it's a few ohms if that?  But that might be enough to see changes when amplification is included.

Tim

[mawyatt]

They are definitely the 74HCU04 type, bought from RS or Farnell.

I've done some (solderless) breadboard tests and the principle seems to work roughly according to that amplification equation, enough I can now be confident enough in overall circuit topology to design a PCB.

I do note though that when multiple channels of a chip are in use as amplifiers there seems to be a "bump" in the amplification on all channels at times when the input on any single channel is a small signal close to 2.5V. Perhaps an effect related to the way that gates draw more current when they are amplifying something which doesn't give an output which comes close to the rails. Or maybe just a consequence of the limited chip decoupling cap arrangement possible with a breadboard, which might disappear once I get a proper PCB for this.

All the unused gates must have the inputs grounded, otherwise they will "sing". Also decouple the supply VDD close to the chip on both VDD and Ground.

Best, 

[tggzzz]

Ah yes, changing the goalposts: when people are using "breadboard" in short for the solderless variety, then fake-agreeing with everyone by requiring the specific definition when no one else does.

Some people use "breadboard" to mean "solderless breadboards". Other people use "breadboard" to mean a range of prototyping techniques. Being unambiguous helps converstations.

As famously put 170 years ago, presuming "glory" not meaning "knock down argument", hinders conversations.

Also very no-true-scottsman-fallacy to bring up examples that most likely require ground plane.

Yes, using "breadboard" to mean only "solderless breadboard" is a no-true-Scotsman-fallacy.

Stop waffling. You've moved completely off-centre. This is not the "house of commons", but an engineering forum.
Semantics have no place, you know EXACTLY what was meant by "breadboard" in previous posts.

Semantics have no place?! Really?! That's a demonstrable glory[1]

And yes, I do know what is meant by "breadboard" - and a solderless breadboard is merely one type of breadboard. Your narrow-minded definintion would exclude people like Bob Pease, Bob Widlar, Jim Williams[2] and similar, because they "breadboard" to mean things other than solderless breadboard.

[1] With apologies to Lewis Carroll, q.v.

[2] let me know if you don't know their contribution to electronic engineering, and I'll give you some pointers (again).

[tggzzz]

They are definitely the 74HCU04 type, bought from RS or Farnell.

I've done some (solderless) breadboard tests and the principle seems to work roughly according to that amplification equation, enough I can now be confident enough in overall circuit topology to design a PCB.

I do note though that when multiple channels of a chip are in use as amplifiers there seems to be a "bump" in the amplification on all channels at times when the input on any single channel is a small signal close to 2.5V. Perhaps an effect related to the way that gates draw more current when they are amplifying something which doesn't give an output which comes close to the rails. Or maybe just a consequence of the limited chip decoupling cap arrangement possible with a breadboard, which might disappear once I get a proper PCB for this.

There will be some amount of supply resistance on-chip, which is and is not shared between devices; you can observe this by setting one to fixed 1/0 output, and seeing if the level varies with load on nearby or other gates.  Probably it's a few ohms if that?  But that might be enough to see changes when amplification is included.

Inductance in power/gnd leads may well be as significant, given the transition times, changes in load currents, changes in shoot-through current when the output is near Vcc/2. A simple simulation should indicate the orders of magnitude involved.

Those effects are one reason for favouring SMD components and single-gate components.

[Ian.M]

A century or so ago, it was common practice to prototype or home construct electronics (mostly radio receivers back then) on a literal wooden breadboard, with all large components screwed down to it, and smaller components hung between their terminals, and maybe a few solid copper wire bus bars e.g. for power and ground supported by and soldered to brass panel pins driven into the wooden board.  You'll find an excellent reconstruction of this construction style here: https://www.qsl.net/ab0cw/NW0O_hartley.htm

Then in the '70s Ladybird Books (a well known London (UK) based publisher of non-fiction childrens books) resurrected this style of breadboarding and made it solderless!  See: https://hackaday.com/2018/08/08/memories-of-a-mis-spent-youth-learnabout-simple-electronics/

Although 'Solderless breadboard' is the generic term  in current use english for a 0.1" pitch plug-in type breadboard, it may not always be so, especially to ESL readers, so in the interest of clear unambiguous communications, it pays to be specific.

[tggzzz]

A century or so ago, it was common practice to prototype or home construct electronics (mostly radio receivers back then) on a literal wooden breadboard, with all large components screwed down to it, and smaller components hung between their terminals, and maybe a few solid copper wire bus bars e.g. for power and ground supported by and soldered to brass panel pins driven into the wooden board.  You'll find an excellent reconstruction of this construction style here: https://www.qsl.net/ab0cw/NW0O_hartley.htm

Make that half a century, in my case.

Pre-teens I used spring clips in a Philips EE20 kit.
Early teens I banged nails into a piece of wood, and soldered between them. That would have been before the Ladybird books you mention.
Mid teens I learned to make PCBs using fablon and nail varnish as an etch resist. Created my 6800 computer like that Much better results than the Decon Dalo pens.

Then in the '70s Ladybird Books (a well known London (UK) based publisher of non-fiction childrens books) resurrected this style of breadboarding and made it solderless!  See: https://hackaday.com/2018/08/08/memories-of-a-mis-spent-youth-learnabout-simple-electronics/

Although 'Solderless breadboard' is the generic term  in current use english for a 0.1" pitch plug-in type breadboard, it may not always be so, especially to ESL readers, so in the interest of clear unambiguous communications, it pays to be specific.

Precisely.

If you don't say what you mean, it is difficult to mean what you say - and vice versa!

[langwadt]

A century or so ago, it was common practice to prototype or home construct electronics (mostly radio receivers back then) on a literal wooden breadboard, with all large components screwed down to it, and smaller components hung between their terminals, and maybe a few solid copper wire bus bars e.g. for power and ground supported by and soldered to brass panel pins driven into the wooden board.  You'll find an excellent reconstruction of this construction style here: https://www.qsl.net/ab0cw/NW0O_hartley.htm

https://gotechdk.files.wordpress.com/2016/03/sc3b8mbrc3a6t.jpg

[Infraviolet]

I fixed the "bump" effect by rearranging the way the inverter gates were used, I've now got each chip doing multiple stages of subsequent amplification on the same channel, and a separate chip per channel. No bumps this time.

Unlike earlier tests where a single chip was used to amplify a signal at multiple stages, this time it seems immune from that very fast oscillation, perhaps because I've put a few more resistors in to limit the gains per stage of amplification.

It seems like I'm ready to design it for a PCB now, so the eternal breadboard debates are, for now, purely academic again.

I could use checking though, is 30mA total consumption in a 74HCU04 ok? When any one of them is amplifying a particularly small signal? The absolute maximum is 50mA according to the datasheet (for a 74HCU04 from any manufacturer TI, Nexperia, didoesInc...), but there's nothing about a recommend long term current rating, most of that current being current in the CMOS gate itself rather than current being supplied to a load. Should I be trying to use large ground planes, or large area traces on the specific traces which go to either end of the gates in use? Or would 30mA not need any special precautions taken to prevent the gate overheating?
Thanks

P.S. that All Electronics Channel video, why does he have that small (100 ohm) resistor and an unspecified cap in series with it leading to ground from the gate's output? Is that an attempt to bleed away any high frequency noise to ground or something? It isn't shown in other articles discussing uing inverters as amplifiers.

[tggzzz]

P.S. that All Electronics Channel video, why does he have that small (100 ohm) resistor and an unspecified cap in series with it leading to ground from the gate's output? Is that an attempt to bleed away any high frequency noise to ground or something? It isn't shown in other articles discussing uing inverters as amplifiers.

Can't tell from that description, and I'm not going to spend my remaining life watching a yootoob vid unless I know it will be worth it.

If they don't state the reason, then that is a reason to be suspicious of the rest of the information.

[MK14]

P.S. that All Electronics Channel video, why does he have that small (100 ohm) resistor and an unspecified cap in series with it leading to ground from the gate's output? Is that an attempt to bleed away any high frequency noise to ground or something? It isn't shown in other articles discussing uing inverters as amplifiers.

I think that, that video is about a subtly different, area, of this subject area, which perhaps is adding to any possible confusion.

He seems to NOT be using unbuffered parts, i.e. standard HC CMOS versions.  Which, seems to have another set of pros and cons.

The advantages, seem to be he is getting (assuming his calculations/measurements are correct, I haven't checked them), a large 1 GHz Gain Bandwidth product.  Which sounds rather impressive, for (what can be) an extremely cheap device (until they become increasing obsolete), with 6 in a single package.

Also, a reasonably large gain (NOT compared to a real op-amp), of (he seems to say), 132, after it is reigned in by his circuitry (he seems to say the open-loop gain would be 200, otherwise).

The Capacitor value, is perhaps 100nF (at around 9 minutes, his paper pad seems or diagram, seems to say, 100m, I assume the m doesn't stand for milliFarads, so the 100nF is a guess on my part, as to what they really meant).

He seems to say, that the 100 Ohm resistor and capacitor (100nF), are to reduce the open loop gain, down to 132 (before being further reduced, by the other components).  It is specifically controlling the AC loading of the output, hence the resistor, capacitor arrangement.

On the one hand, some op-amp types, can readily come 4 to a cheap package (ignoring component shortages, and price increases, when components are going obsolete).  But on the other, it can be fun and very educational, to try things like this.

I assume, that if more than one item was needed.  The dangers, of unexpected (difficult to compensate for), component to component (especially the CMOS device(s) in question), variations.  Would be risky/worrying for anything beyond, a one-off, (presumed) uncritical hobby/experimental type of project.

Potentially cheap, standard op-amps, have the datasheet characterisation, massive excess open loop gain (so the characteristics, will tend to be as good, or nearly as good, as the gain setting etc, components, surrounding the op-amp) and other features.  To help design things, so that things beyond the first/initial prototype, can work well, for years and decades, into the future.

On the other hand, things (before common IC usage), were commonly designed using just transistors.  Which have wildly varying Hfe, over things such as current, voltage, temperature and especially device to device changes.  So in theory, it can be done.

I wonder if the potentially high currents, hence high package power dissipation and corresponding high die temperature.  Could lead to its characteristics, changing too much, over time.  Because in pure (1, 0) logic mode, such changes would tend to not matter, until the device reached its end of life.  As it just needs to be on or off, the linear aspects, don't matter too much (in pure digital use mode).

[mawyatt]

When the original CD4000 series came out in ~70 we started using them for various analog functions, these were able to operate with a  maximum VDD of +18V I recall, and a HV version of +20V. They were Un-Buffered types and fit well with the typical analog supplies of +-15V we used.

It's well known the unequal P and N channel device strengths of the various CMOS flavors, and one can help by referencing the load resistance to VDD rather than ground if possible. This gives the output PMOS device a little help driving a rising output voltage and helps compensate for the unequal output drive capability, whereas the usual ground referenced load places an additional burden on the output PMOS device as the "center reference" is VDD/2 and thus the load draws a static current of VDD/(2*Rload) all coming from the weaker PMOS device. Using VDD reference for the load causes the stronger NMOS device to sink VDD/(2*Rload) current and the PMOS contributes nothing.

Best,

[MK14]

My recollections, are that the original type (4000's), were known as type 'A' (the part number would have the 'A', immediately after the number bit, e.g. 4001A), and signify the unbuffered type, potentially suitable for analogue use, but especially sensitive to static electricity damage (ESD).

But, they later were usually the 'B' type, which had improvements, were usually all buffered and were better protected, against static electricity damage (ESD).

But, the changes (such as an extra, final output stage, buffer), to make the new 'B' types, made them completely unsuitable for using as analogue devices.

Checking the above, from internet sources:
https://wiki.analog.com/_media/university/courses/4000_series_article.pdf

The original 4000 Series devices (the A range, with part numbers 4xxxA) had unbuffered
outputs.

Some 4000 Series devices are still available in the unbuffered A variety, but today most are
found as buffered B types, which have part numbers 4xxxB. In the buffered versions, as
shown in Figure 2, inverting buffers are between the actual gates and the input and output
terminals.

These buffers are used only on input and output terminals, not internally between stages in
more complex devices. In the simplest buffered gates, there are three stages between input
and output instead of one, so buffered devices have faster output slew rate, but slightly slower
propagation delay. They are also slightly less vulnerable to damage from electrostatic
discharge (ESD).

[Infraviolet]

"He seems to NOT be using unbuffered parts, i.e. standard HC CMOS versions.  Which, seems to have another set of pros and cons."

I saw 74HC04 on his whiteboard and thought it was just a typo, if he actually is using unbuffered I can see why he'd have to work differently. Fortunately I'm only need gains in the range of factor of 2.5 to factor of 5, although I need to be able to get a fairly accurately set gain within that range (exactly where being a choice to make by resistor sizing once I have the PCB), and need 3 channels each with gains close to each other.

It will be interesting to test this against the accuracy of gains I get with the existing discrete NPN transistor based amplifier method, once I've got the CMOS PCB delivered and soldered it up, any suggestions as to what tests I could perform on both the transistor and CMOS versions to compare them for stability?

P.S. if I didn't note it earlier, the reason I'm trying CMOS amplification, and also the reason I designed the existing version with discrete transistors, is that the signal is 3MHz and needs amplifying up from 100s of mV to as large a proportion of the 0V to 5V range as I can get without clipping. Most rail-to-rail op amps for single sided 5V supply situations don't seem to have quite enough slew rate to cope with this.

Thanks

[MK14]

"He seems to NOT be using unbuffered parts, i.e. standard HC CMOS versions.  Which, seems to have another set of pros and cons."

I saw 74HC04 on his whiteboard and thought it was just a typo, if he actually is using unbuffered I can see why he'd have to work differently. Fortunately I'm only need gains in the range of factor of 2.5 to factor of 5, although I need to be able to get a fairly accurately set gain within that range (exactly where being a choice to make by resistor sizing once I have the PCB), and need 3 channels each with gains close to each other.

It will be interesting to test this against the accuracy of gains I get with the existing discrete NPN transistor based amplifier method, once I've got the CMOS PCB delivered and soldered it up, any suggestions as to what tests I could perform on both the transistor and CMOS versions to compare them for stability?

P.S. if I didn't note it earlier, the reason I'm trying CMOS amplification, and also the reason I designed the existing version with discrete transistors, is that the signal is 3MHz and needs amplifying up from 100s of mV to as large a proportion of the 0V to 5V range as I can get without clipping. Most rail-to-rail op amps for single sided 5V supply situations don't seem to have quite enough slew rate to cope with this.

Thanks

Thanks, that is a good explanation, of what is going on, and why you want to go down the path of this thread.

Disclaimer.  I think I've gone for a significantly over-specified (too good), part.  But on the other hand, I wanted to make sure I chose an example, that would work, for this application.

What about the following (I'm expecting you to say, it is a bit on the expensive side.  There seem to be plenty of cheaper ones, but I'm not certain enough of the actual requirements and specifications, to choose, between the cheaper ones).

https://www.digikey.co.uk/en/products/detail/texas-instruments/TLV3544IPWR/6595639

TLV3544IPWR, with 4 op-amps per unit.  Datasheet:  https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Ftlv3542

It seems to meet or exceed, the mentioned specifications.  Such as 5 volt operation, high slew rate, rail to rail (inputs and outputs), able to rapidly swing the output, within the 5V range.

I don't know how you are going to react to its price (between £2.13 and £1.05, depending on quantity, x1 .. x1000), but as I'm sure you know, significantly cheaper, devices are available, but at various reductions in capabilities.  It's all too easy for one or more of the components specifications, to make it unsuitable for your application.

TLV354x 200-MHz, Rail-to-Rail I/O,
CMOS Operational Amplifiers for Cost-Sensitive Systems
1
1 Features
1• Wide-Bandwidth Amplifier for Cost-Sensitive
Systems
• Unity-Gain Bandwidth: 200 MHz
• High Slew Rate: 150 V/μs
• Low Noise: 7.5 nV/√Hz
• Rail-to-Rail I/O
• High Output Current: > 100 mA
• Excellent Video Performance:
– Diff Gain: 0.02%, Diff Phase: 0.09°
– 0.1-dB Gain Flatness: 40 MHz
• Low Input Bias Current: 3 pA
• Quiescent Current: 5.2 mA
• Thermal Shutdown
• Supply Range: 2.5 V to 5.5 V

[Infraviolet]

The TLV3544IPWR looks good, and far cheaper than I'd expected for the performance, I'd thought rail to rail with slew rates above 10V/us was usually £10 or so and rarely available as more than a 2 unit chip for that price. Will have to get some, thanks.