Author Topic: How to design with CMOS inverter amplifiers  (Read 4814 times)

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Offline T3sl4co1l

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Re: How to design with CMOS inverter amplifiers
« Reply #25 on: September 09, 2023, 09:58:47 pm »
Ah yes, changing the goalposts: when people are using "breadboard" in short for the solderless variety, then fake-agreeing with everyone by requiring the specific definition when no one else does. :palm:

Also very no-true-scottsman-fallacy to bring up examples that most likely require ground plane. Boards studded with coax connectors? GTFO. That's not what we're talking about here and you know it.

Hm, sadly I didn't take pictures of the setup, but this one was on solderless breadboard: https://www.eevblog.com/forum/projects/simple-induction-heater/
Apparently it's impossible.  Or a variety of other non-critical examples.  Several of which I already gave.

But clearly you aren't operating on logic -- and no number of examples, nor sequence of reasoning, will convince you otherwise.  Sorry.

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Online tggzzz

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Re: How to design with CMOS inverter amplifiers
« Reply #26 on: September 09, 2023, 10:40:25 pm »
Ah yes, changing the goalposts: when people are using "breadboard" in short for the solderless variety, then fake-agreeing with everyone by requiring the specific definition when no one else does. :palm:


Some people use "breadboard" to mean "solderless breadboards". Other people use "breadboard" to mean a range of prototyping techniques. Being unambiguous helps converstations.

As famously put 170 years ago, presuming "glory" not meaning "knock down argument", hinders conversations.

Quote
Also very no-true-scottsman-fallacy to bring up examples that most likely require ground plane.

Yes, using "breadboard" to mean only "solderless breadboard" is a no-true-Scotsman-fallacy.

Quote
Boards studded with coax connectors? GTFO. That's not what we're talking about here and you know it.

Solderless breadboards have several problems that can't be addressed by the addition of a groundplane, so concentrating on that aspect only also rates a "GTFO".

I'm talking about the about the problems the OP has had; what problems are you considering?

It looks like the most significant problems relate to RF mis-behaviour, and - as you expounded(!) - long wires and poor decoupling are likely to be a cause. Both those problems are magnified with solderless breadboards and easily minimised by other breadboarding techniques.

If there weren't easy alternatives, then it would be worth putting up with the infelicities of solderless breadboards.

Personally, if there is an easy way to avoid problems, I'll take the easy path. You?

Quote
Hm, sadly I didn't take pictures of the setup, but this one was on solderless breadboard: https://www.eevblog.com/forum/projects/simple-induction-heater/
Apparently it's impossible.  Or a variety of other non-critical examples.  Several of which I already gave.

But clearly you aren't operating on logic -- and no number of examples, nor sequence of reasoning, will convince you otherwise.  Sorry.

Clearly you are regarding your experiences (as an expert) as being typical of the experiences of beginners -- and the directly relevant counter-example of the OP's experience won't convince you otherwise. Sorry.
« Last Edit: September 09, 2023, 10:43:26 pm by tggzzz »
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Offline mawyatt

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Re: How to design with CMOS inverter amplifiers
« Reply #27 on: September 09, 2023, 11:42:58 pm »
Shahriar of The Signal Path made an excellent video tutorial (with the assistance of his brother) on exactly this topic - how to understand and analyse the 'CMOS inverter amplifier':

Thanks for posting!!!

Superb "The Signal Path" video as usual  :clap:

Nice to see his brother involved, and he's got a PhD in EE also :-+

This is a must view for anyone remotely interested in CMOS devices and how they behave wrt analog use.

Best,
Curiosity killed the cat, also depleted my wallet!
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Offline InfravioletTopic starter

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Re: How to design with CMOS inverter amplifiers
« Reply #28 on: September 11, 2023, 09:37:00 pm »
They are definitely the 74HCU04 type, bought from RS or Farnell.

I've done some (solderless) breadboard tests and the principle seems to work roughly according to that amplification equation, enough I can now be confident enough in overall circuit topology to design a PCB.

I do note though that when multiple channels of a chip are in use as amplifiers there seems to be a "bump" in the amplification on all channels at times when the input on any single channel is a small signal close to 2.5V. Perhaps an effect related to the way that gates draw more current when they are amplifying something which doesn't give an output which comes close to the rails. Or maybe just a consequence of the limited chip decoupling cap arrangement possible with a breadboard, which might disappear once I get a proper PCB for this.
 

Offline Benta

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Re: How to design with CMOS inverter amplifiers
« Reply #29 on: September 11, 2023, 10:00:07 pm »
Ah yes, changing the goalposts: when people are using "breadboard" in short for the solderless variety, then fake-agreeing with everyone by requiring the specific definition when no one else does. :palm:


Some people use "breadboard" to mean "solderless breadboards". Other people use "breadboard" to mean a range of prototyping techniques. Being unambiguous helps converstations.

As famously put 170 years ago, presuming "glory" not meaning "knock down argument", hinders conversations.

Quote
Also very no-true-scottsman-fallacy to bring up examples that most likely require ground plane.

Yes, using "breadboard" to mean only "solderless breadboard" is a no-true-Scotsman-fallacy.

Stop waffling. You've moved completely off-centre. This is not the "house of commons", but an engineering forum.
Semantics have no place, you know EXACTLY what was meant by "breadboard" in previous posts.
 
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Offline T3sl4co1l

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Re: How to design with CMOS inverter amplifiers
« Reply #30 on: September 11, 2023, 10:52:01 pm »
They are definitely the 74HCU04 type, bought from RS or Farnell.

I've done some (solderless) breadboard tests and the principle seems to work roughly according to that amplification equation, enough I can now be confident enough in overall circuit topology to design a PCB.

I do note though that when multiple channels of a chip are in use as amplifiers there seems to be a "bump" in the amplification on all channels at times when the input on any single channel is a small signal close to 2.5V. Perhaps an effect related to the way that gates draw more current when they are amplifying something which doesn't give an output which comes close to the rails. Or maybe just a consequence of the limited chip decoupling cap arrangement possible with a breadboard, which might disappear once I get a proper PCB for this.

There will be some amount of supply resistance on-chip, which is and is not shared between devices; you can observe this by setting one to fixed 1/0 output, and seeing if the level varies with load on nearby or other gates.  Probably it's a few ohms if that?  But that might be enough to see changes when amplification is included.

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!
 
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Offline mawyatt

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Re: How to design with CMOS inverter amplifiers
« Reply #31 on: September 11, 2023, 11:05:30 pm »
They are definitely the 74HCU04 type, bought from RS or Farnell.

I've done some (solderless) breadboard tests and the principle seems to work roughly according to that amplification equation, enough I can now be confident enough in overall circuit topology to design a PCB.

I do note though that when multiple channels of a chip are in use as amplifiers there seems to be a "bump" in the amplification on all channels at times when the input on any single channel is a small signal close to 2.5V. Perhaps an effect related to the way that gates draw more current when they are amplifying something which doesn't give an output which comes close to the rails. Or maybe just a consequence of the limited chip decoupling cap arrangement possible with a breadboard, which might disappear once I get a proper PCB for this.

All the unused gates must have the inputs grounded, otherwise they will "sing". Also decouple the supply VDD close to the chip on both VDD and Ground.

Best, 
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Online tggzzz

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Re: How to design with CMOS inverter amplifiers
« Reply #32 on: September 12, 2023, 12:24:51 am »
Ah yes, changing the goalposts: when people are using "breadboard" in short for the solderless variety, then fake-agreeing with everyone by requiring the specific definition when no one else does. :palm:


Some people use "breadboard" to mean "solderless breadboards". Other people use "breadboard" to mean a range of prototyping techniques. Being unambiguous helps converstations.

As famously put 170 years ago, presuming "glory" not meaning "knock down argument", hinders conversations.

Quote
Also very no-true-scottsman-fallacy to bring up examples that most likely require ground plane.

Yes, using "breadboard" to mean only "solderless breadboard" is a no-true-Scotsman-fallacy.

Stop waffling. You've moved completely off-centre. This is not the "house of commons", but an engineering forum.
Semantics have no place, you know EXACTLY what was meant by "breadboard" in previous posts.

Semantics have no place?! Really?! That's a demonstrable glory[1]

And yes, I do know what is meant by "breadboard" - and a solderless breadboard is merely one type of breadboard. Your narrow-minded definintion would exclude people like Bob Pease, Bob Widlar, Jim Williams[2] and similar, because they "breadboard" to mean things other than solderless breadboard.

[1] With apologies to Lewis Carroll, q.v.

[2] let me know if you don't know their contribution to electronic engineering, and I'll give you some pointers (again).
There are lies, damned lies, statistics - and ADC/DAC specs.
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Online tggzzz

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Re: How to design with CMOS inverter amplifiers
« Reply #33 on: September 12, 2023, 12:28:01 am »
They are definitely the 74HCU04 type, bought from RS or Farnell.

I've done some (solderless) breadboard tests and the principle seems to work roughly according to that amplification equation, enough I can now be confident enough in overall circuit topology to design a PCB.

I do note though that when multiple channels of a chip are in use as amplifiers there seems to be a "bump" in the amplification on all channels at times when the input on any single channel is a small signal close to 2.5V. Perhaps an effect related to the way that gates draw more current when they are amplifying something which doesn't give an output which comes close to the rails. Or maybe just a consequence of the limited chip decoupling cap arrangement possible with a breadboard, which might disappear once I get a proper PCB for this.

There will be some amount of supply resistance on-chip, which is and is not shared between devices; you can observe this by setting one to fixed 1/0 output, and seeing if the level varies with load on nearby or other gates.  Probably it's a few ohms if that?  But that might be enough to see changes when amplification is included.

Inductance in power/gnd leads may well be as significant, given the transition times, changes in load currents, changes in shoot-through current when the output is near Vcc/2. A simple simulation should indicate the orders of magnitude involved.

Those effects are one reason for favouring SMD components and single-gate components.
« Last Edit: September 12, 2023, 12:30:05 am by tggzzz »
There are lies, damned lies, statistics - and ADC/DAC specs.
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Online Ian.M

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Re: How to design with CMOS inverter amplifiers
« Reply #34 on: September 12, 2023, 01:09:31 pm »
A century or so ago, it was common practice to prototype or home construct electronics (mostly radio receivers back then) on a literal wooden breadboard, with all large components screwed down to it, and smaller components hung between their terminals, and maybe a few solid copper wire bus bars e.g. for power and ground supported by and soldered to brass panel pins driven into the wooden board.  You'll find an excellent reconstruction of this construction style here: https://www.qsl.net/ab0cw/NW0O_hartley.htm

Then in the '70s Ladybird Books (a well known London (UK) based publisher of non-fiction childrens books) resurrected this style of breadboarding and made it solderless!  See: https://hackaday.com/2018/08/08/memories-of-a-mis-spent-youth-learnabout-simple-electronics/

Although 'Solderless breadboard' is the generic term  in current use english for a 0.1" pitch plug-in type breadboard, it may not always be so, especially to ESL readers, so in the interest of clear unambiguous communications, it pays to be specific.
« Last Edit: September 12, 2023, 01:16:52 pm by Ian.M »
 

Online tggzzz

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Re: How to design with CMOS inverter amplifiers
« Reply #35 on: September 12, 2023, 02:02:35 pm »
A century or so ago, it was common practice to prototype or home construct electronics (mostly radio receivers back then) on a literal wooden breadboard, with all large components screwed down to it, and smaller components hung between their terminals, and maybe a few solid copper wire bus bars e.g. for power and ground supported by and soldered to brass panel pins driven into the wooden board.  You'll find an excellent reconstruction of this construction style here: https://www.qsl.net/ab0cw/NW0O_hartley.htm

Make that half a century, in my case.

Pre-teens I used spring clips in a Philips EE20 kit.
Early teens I banged nails into a piece of wood, and soldered between them. That would have been before the Ladybird books you mention.
Mid teens I learned to make PCBs using fablon and nail varnish as an etch resist. Created my 6800 computer like that :) Much better results than the Decon Dalo pens.

Quote
Then in the '70s Ladybird Books (a well known London (UK) based publisher of non-fiction childrens books) resurrected this style of breadboarding and made it solderless!  See: https://hackaday.com/2018/08/08/memories-of-a-mis-spent-youth-learnabout-simple-electronics/

Although 'Solderless breadboard' is the generic term  in current use english for a 0.1" pitch plug-in type breadboard, it may not always be so, especially to ESL readers, so in the interest of clear unambiguous communications, it pays to be specific.

Precisely.

If you don't say what you mean, it is difficult to mean what you say - and vice versa!
There are lies, damned lies, statistics - and ADC/DAC specs.
Glider pilot's aphorism: "there is no substitute for span". Retort: "There is a substitute: skill+imagination. But you can buy span".
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Online langwadt

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Re: How to design with CMOS inverter amplifiers
« Reply #36 on: September 12, 2023, 02:04:19 pm »
A century or so ago, it was common practice to prototype or home construct electronics (mostly radio receivers back then) on a literal wooden breadboard, with all large components screwed down to it, and smaller components hung between their terminals, and maybe a few solid copper wire bus bars e.g. for power and ground supported by and soldered to brass panel pins driven into the wooden board.  You'll find an excellent reconstruction of this construction style here: https://www.qsl.net/ab0cw/NW0O_hartley.htm

https://gotechdk.files.wordpress.com/2016/03/sc3b8mbrc3a6t.jpg
 

Offline InfravioletTopic starter

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Re: How to design with CMOS inverter amplifiers
« Reply #37 on: September 13, 2023, 02:14:29 am »
I fixed the "bump" effect by rearranging the way the inverter gates were used, I've now got each chip doing multiple stages of subsequent amplification on the same channel, and a separate chip per channel. No bumps this time.

Unlike earlier tests where a single chip was used to amplify a signal at multiple stages, this time it seems immune from that very fast oscillation, perhaps because I've put a few more resistors in to limit the gains per stage of amplification.

It seems like I'm ready to design it for a PCB now, so the eternal breadboard debates are, for now, purely academic again.

I could use checking though, is 30mA total consumption in a 74HCU04 ok? When any one of them is amplifying a particularly small signal? The absolute maximum is 50mA according to the datasheet (for a 74HCU04 from any manufacturer TI, Nexperia, didoesInc...), but there's nothing about a recommend long term current rating, most of that current being current in the CMOS gate itself rather than current being supplied to a load. Should I be trying to use large ground planes, or large area traces on the specific traces which go to either end of the gates in use? Or would 30mA not need any special precautions taken to prevent the gate overheating?
Thanks

P.S. that All Electronics Channel video, why does he have that small (100 ohm) resistor and an unspecified cap in series with it leading to ground from the gate's output? Is that an attempt to bleed away any high frequency noise to ground or something? It isn't shown in other articles discussing uing inverters as amplifiers.
« Last Edit: September 13, 2023, 02:19:55 am by Infraviolet »
 

Online tggzzz

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Re: How to design with CMOS inverter amplifiers
« Reply #38 on: September 13, 2023, 07:43:24 am »
P.S. that All Electronics Channel video, why does he have that small (100 ohm) resistor and an unspecified cap in series with it leading to ground from the gate's output? Is that an attempt to bleed away any high frequency noise to ground or something? It isn't shown in other articles discussing uing inverters as amplifiers.

Can't tell from that description, and I'm not going to spend my remaining life watching a yootoob vid unless I know it will be worth it.

If they don't state the reason, then that is a reason to be suspicious of the rest of the information.
There are lies, damned lies, statistics - and ADC/DAC specs.
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Offline MK14

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Re: How to design with CMOS inverter amplifiers
« Reply #39 on: September 13, 2023, 09:47:10 am »
P.S. that All Electronics Channel video, why does he have that small (100 ohm) resistor and an unspecified cap in series with it leading to ground from the gate's output? Is that an attempt to bleed away any high frequency noise to ground or something? It isn't shown in other articles discussing uing inverters as amplifiers.

I think that, that video is about a subtly different, area, of this subject area, which perhaps is adding to any possible confusion.

He seems to NOT be using unbuffered parts, i.e. standard HC CMOS versions.  Which, seems to have another set of pros and cons.

The advantages, seem to be he is getting (assuming his calculations/measurements are correct, I haven't checked them), a large 1 GHz Gain Bandwidth product.  Which sounds rather impressive, for (what can be) an extremely cheap device (until they become increasing obsolete), with 6 in a single package.

Also, a reasonably large gain (NOT compared to a real op-amp), of (he seems to say), 132, after it is reigned in by his circuitry (he seems to say the open-loop gain would be 200, otherwise).

The Capacitor value, is perhaps 100nF (at around 9 minutes, his paper pad seems or diagram, seems to say, 100m, I assume the m doesn't stand for milliFarads, so the 100nF is a guess on my part, as to what they really meant).

He seems to say, that the 100 Ohm resistor and capacitor (100nF), are to reduce the open loop gain, down to 132 (before being further reduced, by the other components).  It is specifically controlling the AC loading of the output, hence the resistor, capacitor arrangement.

On the one hand, some op-amp types, can readily come 4 to a cheap package (ignoring component shortages, and price increases, when components are going obsolete).  But on the other, it can be fun and very educational, to try things like this.

I assume, that if more than one item was needed.  The dangers, of unexpected (difficult to compensate for), component to component (especially the CMOS device(s) in question), variations.  Would be risky/worrying for anything beyond, a one-off, (presumed) uncritical hobby/experimental type of project.

Potentially cheap, standard op-amps, have the datasheet characterisation, massive excess open loop gain (so the characteristics, will tend to be as good, or nearly as good, as the gain setting etc, components, surrounding the op-amp) and other features.  To help design things, so that things beyond the first/initial prototype, can work well, for years and decades, into the future.

On the other hand, things (before common IC usage), were commonly designed using just transistors.  Which have wildly varying Hfe, over things such as current, voltage, temperature and especially device to device changes.  So in theory, it can be done.

I wonder if the potentially high currents, hence high package power dissipation and corresponding high die temperature.  Could lead to its characteristics, changing too much, over time.  Because in pure (1, 0) logic mode, such changes would tend to not matter, until the device reached its end of life.  As it just needs to be on or off, the linear aspects, don't matter too much (in pure digital use mode).
 

Offline mawyatt

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Re: How to design with CMOS inverter amplifiers
« Reply #40 on: September 13, 2023, 01:29:01 pm »
When the original CD4000 series came out in ~70 we started using them for various analog functions, these were able to operate with a  maximum VDD of +18V I recall, and a HV version of +20V. They were Un-Buffered types and fit well with the typical analog supplies of +-15V we used.

It's well known the unequal P and N channel device strengths of the various CMOS flavors, and one can help by referencing the load resistance to VDD rather than ground if possible. This gives the output PMOS device a little help driving a rising output voltage and helps compensate for the unequal output drive capability, whereas the usual ground referenced load places an additional burden on the output PMOS device as the "center reference" is VDD/2 and thus the load draws a static current of VDD/(2*Rload) all coming from the weaker PMOS device. Using VDD reference for the load causes the stronger NMOS device to sink VDD/(2*Rload) current and the PMOS contributes nothing.

Best,
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Offline MK14

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Re: How to design with CMOS inverter amplifiers
« Reply #41 on: September 13, 2023, 05:25:48 pm »
My recollections, are that the original type (4000's), were known as type 'A' (the part number would have the 'A', immediately after the number bit, e.g. 4001A), and signify the unbuffered type, potentially suitable for analogue use, but especially sensitive to static electricity damage (ESD).

But, they later were usually the 'B' type, which had improvements, were usually all buffered and were better protected, against static electricity damage (ESD).

But, the changes (such as an extra, final output stage, buffer), to make the new 'B' types, made them completely unsuitable for using as analogue devices.

Checking the above, from internet sources:
https://wiki.analog.com/_media/university/courses/4000_series_article.pdf

Quote
The original 4000 Series devices (the A range, with part numbers 4xxxA) had unbuffered
outputs.

Quote
Some 4000 Series devices are still available in the unbuffered A variety, but today most are
found as buffered B types, which have part numbers 4xxxB. In the buffered versions, as
shown in Figure 2, inverting buffers are between the actual gates and the input and output
terminals.

Quote
These buffers are used only on input and output terminals, not internally between stages in
more complex devices. In the simplest buffered gates, there are three stages between input
and output instead of one, so buffered devices have faster output slew rate, but slightly slower
propagation delay. They are also slightly less vulnerable to damage from electrostatic
discharge (ESD).
 

Offline InfravioletTopic starter

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Re: How to design with CMOS inverter amplifiers
« Reply #42 on: September 13, 2023, 08:16:49 pm »
"He seems to NOT be using unbuffered parts, i.e. standard HC CMOS versions.  Which, seems to have another set of pros and cons."

I saw 74HC04 on his whiteboard and thought it was just a typo, if he actually is using unbuffered I can see why he'd have to work differently. Fortunately I'm only need gains in the range of factor of 2.5 to factor of 5, although I need to be able to get a fairly accurately set gain within that range (exactly where being a choice to make by resistor sizing once I have the PCB), and need 3 channels each with gains close to each other.

It will be interesting to test this against the accuracy of gains I get with the existing discrete NPN transistor based amplifier method, once I've got the CMOS PCB delivered and soldered it up, any suggestions as to what tests I could perform on both the transistor and CMOS versions to compare them for stability?

P.S. if I didn't note it earlier, the reason I'm trying CMOS amplification, and also the reason I designed the existing version with discrete transistors, is that the signal is 3MHz and needs amplifying up from 100s of mV to as large a proportion of the 0V to 5V range as I can get without clipping. Most rail-to-rail op amps for single sided 5V supply situations don't seem to have quite enough slew rate to cope with this.

Thanks
 
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Offline MK14

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Re: How to design with CMOS inverter amplifiers
« Reply #43 on: September 13, 2023, 10:13:07 pm »
"He seems to NOT be using unbuffered parts, i.e. standard HC CMOS versions.  Which, seems to have another set of pros and cons."

I saw 74HC04 on his whiteboard and thought it was just a typo, if he actually is using unbuffered I can see why he'd have to work differently. Fortunately I'm only need gains in the range of factor of 2.5 to factor of 5, although I need to be able to get a fairly accurately set gain within that range (exactly where being a choice to make by resistor sizing once I have the PCB), and need 3 channels each with gains close to each other.

It will be interesting to test this against the accuracy of gains I get with the existing discrete NPN transistor based amplifier method, once I've got the CMOS PCB delivered and soldered it up, any suggestions as to what tests I could perform on both the transistor and CMOS versions to compare them for stability?

P.S. if I didn't note it earlier, the reason I'm trying CMOS amplification, and also the reason I designed the existing version with discrete transistors, is that the signal is 3MHz and needs amplifying up from 100s of mV to as large a proportion of the 0V to 5V range as I can get without clipping. Most rail-to-rail op amps for single sided 5V supply situations don't seem to have quite enough slew rate to cope with this.

Thanks

Thanks, that is a good explanation, of what is going on, and why you want to go down the path of this thread.

Disclaimer.  I think I've gone for a significantly over-specified (too good), part.  But on the other hand, I wanted to make sure I chose an example, that would work, for this application.

What about the following (I'm expecting you to say, it is a bit on the expensive side.  There seem to be plenty of cheaper ones, but I'm not certain enough of the actual requirements and specifications, to choose, between the cheaper ones).

https://www.digikey.co.uk/en/products/detail/texas-instruments/TLV3544IPWR/6595639

TLV3544IPWR, with 4 op-amps per unit.  Datasheet:  https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Ftlv3542

It seems to meet or exceed, the mentioned specifications.  Such as 5 volt operation, high slew rate, rail to rail (inputs and outputs), able to rapidly swing the output, within the 5V range.

I don't know how you are going to react to its price (between £2.13 and £1.05, depending on quantity, x1 .. x1000), but as I'm sure you know, significantly cheaper, devices are available, but at various reductions in capabilities.  It's all too easy for one or more of the components specifications, to make it unsuitable for your application.

Quote
TLV354x 200-MHz, Rail-to-Rail I/O,
CMOS Operational Amplifiers for Cost-Sensitive Systems
1
1 Features
1• Wide-Bandwidth Amplifier for Cost-Sensitive
Systems

• Unity-Gain Bandwidth: 200 MHz
High Slew Rate: 150 V/μs
• Low Noise: 7.5 nV/√Hz
Rail-to-Rail I/O
• High Output Current: > 100 mA
• Excellent Video Performance:
– Diff Gain: 0.02%, Diff Phase: 0.09°
– 0.1-dB Gain Flatness: 40 MHz
• Low Input Bias Current: 3 pA
• Quiescent Current: 5.2 mA
• Thermal Shutdown
Supply Range: 2.5 V to 5.5 V
« Last Edit: September 13, 2023, 10:16:25 pm by MK14 »
 

Offline InfravioletTopic starter

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Re: How to design with CMOS inverter amplifiers
« Reply #44 on: September 14, 2023, 05:28:50 pm »
The TLV3544IPWR looks good, and far cheaper than I'd expected for the performance, I'd thought rail to rail with slew rates above 10V/us was usually £10 or so and rarely available as more than a 2 unit chip for that price. Will have to get some, thanks.
 
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