First CPLD Design Feedback

[MinMax]

I'm designing my first PCB that doesn't use auto routing.  This is also my first CPLD board.  I'm hoping to get some feed back, especially on things that will prevent the board from working.

This design is based on a schematic for the Altera MAX II EPM240 "developer board".  This is just the first step for me.  I'm hoping to start off simple and then move on to other more complex devices like the MAX 5, MAX 10 and maybe some proper FPGAs eventually.  The idea is to learn how to make these boards so that I can then easily use a FPGA in my own future projects.  This design was done in EasyEDA and will be assembled by JLCPCB. What do you guys think?

If you have an EasyEDA account, you can view my project here: https://u.easyeda.com/join?type=project&key=edc8f4291a3d8e2bfcc6537b3a06b62b&inviter=4e5d07c01957454a8bc3e589484919cc

I'm using the usual 4 layer board stack-up: signal, ground, power, signal.

[MarginallyStable]

Are we missing a layer? Doesn't look like any of the VCC's are connected

[MinMax]

Yes, I have a power layer and a ground layer.  There are no traces on there so I didn't include them.  I updated the post to include them now.

[AK6DN]

Inner 2 layer display looks like it includes both Inner 2 and Top, can you post just Inner 2 alone?

[MinMax]

Inner 2 layer display looks like it includes both Inner 2 and Top, can you post just Inner 2 alone?

Fixed.

[dobsonr741]

This is a very low complexity board, and to that the size is huge. If you want to hone in your skills in optimizing using multiple layers, make the board smaller. And if you want to gain marketable skills, the progression is toward the inside of the cold/fpga, not in the surrounding PCB. In other words, focus on RTL design and simulation.