Learn FPGA from scratch

[suzhiming]

updating

[zapta]

In April 2025 you said that you don't know a thing about FPGA, so it seems that you had a long way since then. Good job!

[suyoupeng]

HKEY
Press delay → Release detection → Execute once

Code: [Select]

/**************高级PWM+EPM570***********************/
/**************ID:共同学习FPGA**********************/
/*****************20260301*************************/
/*****************按键*****************************/
module anjian
(
input clk,
input k_ent,
output reg kent_anjian
);
reg kent_shang; //确认上次;
reg kent_a1; //按键确定标志位1;
reg kent_a2; //按键确定标志位2;
reg[9:0] kent_cnt; //定时用;
always@(posedge clk )
begin

kent_cnt <= ~k_ent ?(kent_cnt < 1000 ? kent_cnt + 1 : 1000) : 0; //按键按下开始计时
kent_a1 <= kent_cnt == 1000; //按下

kent_shang <= ~k_ent; //记住上一次状态
kent_a2 <= kent_shang && k_ent; //松手

kent_anjian <= kent_a1 && kent_a2 && (!kent_anjian);

if(kent_anjian) begin kent_a1 <= 0; end
end
endmodule



[suyoupeng]

Code: [Select]

/**************高级PWM+EPM570***********************/
/**************ID:共同学习FPGA**********************/
/*****************20260301*************************/
/*****************pwm******************************/
//100   /\        /\        /\        /\   FFFF
// |   /  \      /  \      /  \      /  \   |
// |  /|  |\    /    \    /    \    /    \  |计数
// | / |  | \  /      \  /      \  /      \ |
// 0/__|_S|__\/____N___\/____S___\/____N___\0
//     |  |
//     比较
//------------|-------H桥---------|-----------+
//            |                   |
//            /1h   S     N     2h\
//            |-----~~~L~~~-------|
//            \1l               2l/
//            |                   |
//------------|-------------------|-----------gnd
module pwm
(
input clk,
input pwm_qidong, //pwm启动;
input [3:0] pwm_dangwei, //pwm档位;

output reg pwm1_h,
output reg pwm1_l,
output reg pwm2_h,
output reg pwm2_l
);


reg[1:0] pwm_state; //状态机寄存器4种状态;
reg[31:0] pwm_jishu; //计数器;
reg[31:0] pwm_bijiao; //比较器;
reg[31:0] pwm_bijiao1; //比较器;
//reg[7:0] pwm_siqu; //死区;
/**************************************************/
always@(*)
begin
case(pwm_dangwei)
1: pwm_bijiao = 45_000_000;
2: pwm_bijiao = 40_000_000;
3: pwm_bijiao = 35_000_000;
4: pwm_bijiao = 30_000_000;
5: pwm_bijiao = 25_000_000;
6: pwm_bijiao = 20_000_000;
7: pwm_bijiao = 15_000_000;
8: pwm_bijiao = 10_000_000;
9: pwm_bijiao = 5_000_000;
default: pwm_bijiao = 25_000_000;
endcase
end
/**************************************************/
always@(posedge clk)
begin
if(pwm_qidong)
begin
/**************************************************/
case(pwm_state)
/**************************************************/ //上升(S开比较);
0:
begin


if(pwm_jishu == 0) //0更新比较器数据
begin
if(pwm_bijiao1 != pwm_bijiao )
begin
pwm_bijiao1 <= pwm_bijiao;
end
end


if(pwm_jishu < 50_000_000)
begin
pwm_jishu <= pwm_jishu + 1;
if(pwm_jishu == pwm_bijiao1) //开比较
begin
pwm1_h <= 1;
pwm2_l <= 1;
end
end
else
begin
pwm_state <= 1;
end
end
/**************************************************/ //下降(S关比较);
1:
begin
if(pwm_jishu > 0)
begin
pwm_jishu <= pwm_jishu - 1;
if(pwm_jishu == pwm_bijiao1) //关比较
begin
pwm1_h <= 0;
pwm2_l <= 0;
end
end
else
begin
pwm_state <= 2;
end
end
/**************************************************/ //上升(N开比较);
2:
begin

if(pwm_jishu == 0) //0更新比较器数据
begin
if(pwm_bijiao1 != pwm_bijiao )
begin
pwm_bijiao1 <= pwm_bijiao;
end
end


if(pwm_jishu < 50_000_000)
begin
pwm_jishu <= pwm_jishu + 1;
if(pwm_jishu == pwm_bijiao1)
begin
pwm2_h <= 1;
pwm1_l <= 1;
end
end
else
begin
pwm_state <= 3;
end
end
/**************************************************/ //下降(N关比较);
3:
begin
if(pwm_jishu > 0)
begin
pwm_jishu <= pwm_jishu - 1;
if(pwm_jishu == pwm_bijiao1)
begin
pwm2_h <= 0;
pwm1_l <= 0;
end
end
else
begin
pwm_state <= 0;
end


end
/**************************************************/
endcase
/**************************************************/
end
/**************************************************/
else
begin
pwm_state <= 0;
pwm1_h <= 0;
pwm1_l <= 0;
pwm2_h <= 0;
pwm2_l <= 0;
end
/**************************************************/
end
endmodule



[suyoupeng]

Code: [Select]

/**************高级PWM+EPM570***********************/
/**************ID:共同学习FPGA**********************/
/*****************20260301*************************/
/*****************pwm******************************/
//100   /\        /\        /\        /\   FFFF
// |   /  \      /  \      /  \      /  \   |
// |  /|  |\    /    \    /    \    /    \  |计数
// | / |  | \  /      \  /      \  /      \ |
// 0/__|_S|__\/____N___\/____S___\/____N___\0
//     |  |
//     比较
//------------|-------H桥---------|-----------+
//            |                   |
//            /1h   S     N     2h\
//            |-----~~~L~~~-------|
//            \1l               2l/
//            |                   |
//------------|-------------------|-----------gnd
module pwm
(
input clk,
input pwm_qidong, //pwm启动;
input [3:0] pwm_dangwei, //pwm档位;

output reg pwm1_h,
output reg pwm1_l,
output reg pwm2_h,
output reg pwm2_l
);

reg[1:0] pwm_state; //状态机寄存器4种状态;
reg[15:0] pwm_jishu; //计数器;
reg[15:0] pwm_bijiao; //比较器;
reg[15:0] pwm_bijiao1; //比较器1;
parameter pwm_siqu = 63; //死区;
parameter pinlv = 30000; //调整频率用;
/**************************************************/
always@(*)
begin
case(pwm_dangwei)
1: pwm_bijiao = 27000;
2: pwm_bijiao = 24000;
3: pwm_bijiao = 21000;
4: pwm_bijiao = 18000;
5: pwm_bijiao = 15000;
6: pwm_bijiao = 12000;
7: pwm_bijiao = 9000;
8: pwm_bijiao = 6000;
9: pwm_bijiao = 3000;
default: pwm_bijiao = 15000;
endcase
end
/**************************************************/
always@(posedge clk)
begin
if(pwm_qidong)
begin
/**************************************************/
case(pwm_state)
/**************************************************/ //上升(S开比较);
0:
begin


if(pwm_jishu == 0) //0更新比较器数据
begin
if(pwm_bijiao1 != pwm_bijiao )
begin
pwm_bijiao1 <= pwm_bijiao - pwm_siqu;
end
end


if(pwm_jishu < pinlv)
begin
pwm_jishu <= pwm_jishu + 1;
if(pwm_jishu == pwm_bijiao1) //开比较
begin
pwm1_h <= 1;
pwm2_l <= 1;
end
end
else
begin
pwm_state <= 1;
end
end
/**************************************************/ //下降(S关比较);
1:
begin
if(pwm_jishu > 0)
begin
pwm_jishu <= pwm_jishu - 1;
if(pwm_jishu == pwm_bijiao1) //关比较
begin
pwm1_h <= 0;
pwm2_l <= 0;
end
end
else
begin
pwm_state <= 2;
end
end
/**************************************************/ //上升(N开比较);
2:
begin

if(pwm_jishu == 0) //0更新比较器数据
begin
if(pwm_bijiao1 != pwm_bijiao )
begin
pwm_bijiao1 <= pwm_bijiao - pwm_siqu;
end
end


if(pwm_jishu < pinlv)
begin
pwm_jishu <= pwm_jishu + 1;
if(pwm_jishu == pwm_bijiao1)
begin
pwm2_h <= 1;
pwm1_l <= 1;
end
end
else
begin
pwm_state <= 3;
end
end
/**************************************************/ //下降(N关比较);
3:
begin
if(pwm_jishu > 0)
begin
pwm_jishu <= pwm_jishu - 1;
if(pwm_jishu == pwm_bijiao1)
begin
pwm2_h <= 0;
pwm1_l <= 0;
end
end
else
begin
pwm_state <= 0;
end


end
/**************************************************/
endcase
/**************************************************/
end
/**************************************************/
else
begin
pwm_state <= 0;
pwm1_h <= 0;
pwm1_l <= 0;
pwm2_h <= 0;
pwm2_l <= 0;
end
/**************************************************/
end
endmodule



[suyoupeng]

ADC potentiometer: no power connected

Code: [Select]

/*****************EPM240+100Mhz+ADS7822************/
/*****************ID:共同学习FPGA*******************/
/*****************20260222*************************/
//     _____       _____       _____       _____
//    |5161B|     |     |     |     |     |     |
//    |     |     |     |  .  |     |     |     |
//     -----       -----       -----       -----
//    |     |     |     |  .  |     |     |     |
//    |_____|     |_____|     |_____|     |_____|
//      千,4        百,3        十,2         个,1
/**************************************************/
module adc1
(
input shizhong,
input res,
output reg[7:0] shumaguan_1,
output reg[7:0] shumaguan_2,
output reg[7:0] shumaguan_3,
output reg[7:0] shumaguan_4,
output reg ad_cs, //片选
output reg ad_dclock, //时钟
input wire ad_dout //数据
);
/**************************************************/ //ads7822,100Mhz;
reg[15:0] ad_a1; //ad值
reg[15:0] ad_a2; //ad临时值
reg ad_b1; //ad启动
reg[7:0] ad_c1; //ad计数用
reg[11:0] ad_c2; //ad计时用
always @(posedge shizhong or negedge res)
begin
if(~ res)
begin
ad_cs <= 1; //高电平
ad_dclock <= 1; //高电平
ad_a1 <= 0;
ad_a2 <= 0;
ad_b1 <= 0;
ad_c1 <= 0;
ad_c2 <= 0;
end
else
begin
/**************************************************/
if (miao)
begin
ad_a2 <= 0; //ad清零;
ad_b1 <= 1; //启动ad;
ad_c1 <= 15; //下降沿次数;
ad_c2 <= 1000; //10us;
end
/**************************************************/
if(ad_b1)
begin
ad_cs <= 0; //片选;
if(ad_c1)
begin
if(ad_c2 == 0)
begin
ad_c2 <= 1000;
ad_dclock <= ~ad_dclock;
if(ad_dclock == 1) //取上升沿的信号;
begin
ad_c1 <= ad_c1 -1;
ad_a2 <= {ad_a2[11:0],ad_dout}; //位拼接
end
end
else
begin
ad_c2 <= ad_c2 -1;
end
end
else
begin
ad_cs <= 1; //片选取消;
ad_a1 <= ad_a2;
end

end
/**************************************************/
end
end

/**************************************************/ //时钟输出秒信号;
reg[25:0] jishuqi;
reg miao;
always @(posedge shizhong or negedge res)
begin
if(~ res)
begin
jishuqi <= 0;
miao <= 0;
end
else
begin
/**************************************************/
if(jishuqi == 49_999_999) //0.5秒/次
begin
jishuqi <= 0;
miao <= 1;
end
else
begin
jishuqi <= jishuqi + 1;
miao <= 0;
end

/**************************************************/
end
end

/**************************************************/ //显示程序
parameter seg_0 = 8'hc0, //0
seg_1 = 8'hf9, //1
seg_2 = 8'ha4, //2
seg_3 = 8'hb0, //3
seg_4 = 8'h99, //4
seg_5 = 8'h92, //5
seg_6 = 8'h82, //6
seg_7 = 8'hf8, //7
seg_8 = 8'h80, //8
seg_9 = 8'h90, //9
seg_A = 8'h88, //A
seg_B = 8'h83, //B
seg_C = 8'hc6, //C
seg_D = 8'ha1, //D
seg_E = 8'h86, //E
seg_F = 8'h8e, //F
seg_off = 8'hff; //熄灭
/**************************************************/
reg[3:0] shumaguan_a1;
reg[3:0] shumaguan_a2;
reg[3:0] shumaguan_a3;
reg[3:0] shumaguan_a4;
always @(posedge shizhong or negedge res)
begin
if(~ res)
begin
shumaguan_a1 <= 0;
shumaguan_a2 <= 0;
shumaguan_a3 <= 0;
shumaguan_a4 <= 0;
end
else
begin
/**************************************************/
shumaguan_a1 <= ad_a1[3:0];
shumaguan_a2 <= ad_a1[7:4];
shumaguan_a3 <= ad_a1[11:8];
shumaguan_a4 <= ad_a1[15:12];
/**************************************************/ //数码管1
case(shumaguan_a1)
0: shumaguan_1 <= seg_0; // 0;
1: shumaguan_1 <= seg_1; // 1;
2: shumaguan_1 <= seg_2; // 2;
3: shumaguan_1 <= seg_3; // 3;
4: shumaguan_1 <= seg_4; // 4;
5: shumaguan_1 <= seg_5; // 5;
6: shumaguan_1 <= seg_6; // 6;
7: shumaguan_1 <= seg_7; // 7;
8: shumaguan_1 <= seg_8; // 8;
9: shumaguan_1 <= seg_9; // 9;
10: shumaguan_1 <= seg_A; // 10;
11: shumaguan_1 <= seg_B; // 11;
12: shumaguan_1 <= seg_C; // 12;
13: shumaguan_1 <= seg_D; // 13;
14: shumaguan_1 <= seg_E; // 14;
15: shumaguan_1 <= seg_F; // 15;
//default: shumaguan_1 <= seg_off; // 熄灭;
endcase
/**************************************************/ //数码管2
case(shumaguan_a2)
0: shumaguan_2 <= seg_0; // 0;
1: shumaguan_2 <= seg_1; // 1;
2: shumaguan_2 <= seg_2; // 2;
3: shumaguan_2 <= seg_3; // 3;
4: shumaguan_2 <= seg_4; // 4;
5: shumaguan_2 <= seg_5; // 5;
6: shumaguan_2 <= seg_6; // 6;
7: shumaguan_2 <= seg_7; // 7;
8: shumaguan_2 <= seg_8; // 8;
9: shumaguan_2 <= seg_9; // 9;
10: shumaguan_2 <= seg_A; // 10;
11: shumaguan_2 <= seg_B; // 11;
12: shumaguan_2 <= seg_C; // 12;
13: shumaguan_2 <= seg_D; // 13;
14: shumaguan_2 <= seg_E; // 14;
15: shumaguan_2 <= seg_F; // 15;
//default: shumaguan_2 <= seg_off; // 熄灭;
endcase
/**************************************************/ //数码管3
case(shumaguan_a3)
0: shumaguan_3 <= seg_0; // 0;
1: shumaguan_3 <= seg_1; // 1;
2: shumaguan_3 <= seg_2; // 2;
3: shumaguan_3 <= seg_3; // 3;
4: shumaguan_3 <= seg_4; // 4;
5: shumaguan_3 <= seg_5; // 5;
6: shumaguan_3 <= seg_6; // 6;
7: shumaguan_3 <= seg_7; // 7;
8: shumaguan_3 <= seg_8; // 8;
9: shumaguan_3 <= seg_9; // 9;
10: shumaguan_3 <= seg_A; // 10;
11: shumaguan_3 <= seg_B; // 11;
12: shumaguan_3 <= seg_C; // 12;
13: shumaguan_3 <= seg_D; // 13;
14: shumaguan_3 <= seg_E; // 14;
15: shumaguan_3 <= seg_F; // 15;
//default: shumaguan_3 <= seg_off; // 熄灭;
endcase
/**************************************************/ //数码管4
case(shumaguan_a4)
0: shumaguan_4 <= seg_0; // 0;
1: shumaguan_4 <= seg_1; // 1;
2: shumaguan_4 <= seg_2; // 2;
3: shumaguan_4 <= seg_3; // 3;
4: shumaguan_4 <= seg_4; // 4;
5: shumaguan_4 <= seg_5; // 5;
6: shumaguan_4 <= seg_6; // 6;
7: shumaguan_4 <= seg_7; // 7;
8: shumaguan_4 <= seg_8; // 8;
9: shumaguan_4 <= seg_9; // 9;
10: shumaguan_4 <= seg_A; // 10;
11: shumaguan_4 <= seg_B; // 11;
12: shumaguan_4 <= seg_C; // 12;
13: shumaguan_4 <= seg_D; // 13;
14: shumaguan_4 <= seg_E; // 14;
15: shumaguan_4 <= seg_F; // 15;
//default: shumaguan_4 <= seg_off; // 熄灭;
endcase
/**************************************************/
end
end

endmodule



[suyoupeng]

Dual-Pulse Signal Generator

RST reset.
ENT next State / output.(key release event)
+/-  up/down.

four operating states:
1:(LED1:on,LED2:off) First high pulse duration.(1-999)
2:(LED1:off,LED2:on) First low pulse duration.(1-999)
3:(LED1:on,LED2:on) Second high pulse duration.(0-999)
*3.1:Second low pulse duration copies the first low pulse duration.
4:(LED1:on,LED2:blink) Output Channel Selection(1-6).+Output count.(0-999)

[suyoupeng]

Two complementary PWM outputs

You can try developing a center-aligned power PWM with two complementary outputs on the EPM570-based dual-pulse generator platform.

Original post URL [Spam Link removed]

[sudaqiang2026]

 I’ll switch to my alt to spam.