They pretty much have an use all the same terminology and data timing points as Quartus' timing report, yet the 1 single number figure they want you to calculate by hand with a calculator is the FMAX? I just want an Idea of how much work I need to do to stretch my design or it's expand-ability at a glance before digging into the difficult numbers.
Please be more clear when you say, "you can create a block"?
Something like this? The calculation in question is comparing the magnitude of 2 bytes, with an upper and lower value. I just wanna make sure the same logic is re-used and the sampled clock just de-selected, switched and not some whole new logic re-created, lets be efficient here.
always @(posedge clk_1)begin
if(enable==1'b0) begin
calculation
....
end
end
always @(posedge clk_2)begin
if(enable==1'b1) begin
calculation
....
end
end
Yeah something like that Brian.
the "calculation" , should this be defined as a function? For the "compiler" to understand I wanna re-use this, if the upper and lower limits are the same for both.
Or is it gonna be smart and re-use what it can?
My little LC3 project will run at 100 MHz on an Artix 7 100T but timing fails at 200 MHz. I didn't iterate over values to find the highest possible frequency because the crystal oscillator is 100 MHz and that is as fast as I want to push the design. In ISE they used to tell you the maximum possible frequency. I haven't found that datapoint in Vivado. I'm sure it's there somewhere but I haven't run across it.They removed the feature in Vivado:
https://www.xilinx.com/support/answers/57304.html
I find it kind of funny that with a bloody computer, and soooooo much on screen data and tables to show you everything that you have to read that thread, and use the formula given to you in that thread to calculate the FMAX on your own. Where the formula is ' 1/(T-WNS) ' and T is your given clock period. Though, on their timing reports video:
https://www.xilinx.com/video/hardware/timing-summary-report.html
They pretty much have an use all the same terminology and data timing points as Quartus' timing report, yet the 1 single number figure they want you to calculate by hand with a calculator is the FMAX? I just want an Idea of how much work I need to do to stretch my design or it's expand-ability at a glance before digging into the difficult numbers.
its not simultaneously. mutually exclusive.
Worst case stress test would be 150mhz.
All logic blocks do the exact same frikkin thing, its just a different in, and a bit slower.
Both pins of the type clk#_p
My original question was regarding the syntax, and now I was forced to explain alot more than I wanted to.
So these calculations are considered DSP and not flip flop or gates?
Sweet deal!
A lot. The tools stop optimizing as soon as the timing is met. If you want higher speed, the tools may be able to make it, but at the cost of extra optimization, which may take hours. There's no way to find out aside of actually trying.
A lot. The tools stop optimizing as soon as the timing is met. If you want higher speed, the tools may be able to make it, but at the cost of extra optimization, which may take hours. There's no way to find out aside of actually trying.And to me that behavior makes perfect sense, especially if you consider that they have to support parts with insane amount of resources, so finding the absolute best solution can take ridiculously long time, and in most cases when you have a well-constrained design, you don't really need the absolute best.
All logic blocks do the exact same frikkin thing, its just a different pin, and a bit slower.
Are you sure that's true.
So, how is a main system clock supposed to be generated, am I doing this right?
To sample a 150mhz clock I need something 3x, so 450mhz
I was just wondering what the Instantiation was for, I thought instantiations were for testbenches?
ALTCTKCTRL gave me 2 files that I can play with, the rest to me is all to be ignored and chinese.
So for anything that has a relation with the switchover should be found in ALTPLL, not ALTCLKCTRL, correct?
Earlier I mentioned that you can't find an edge by using if pos_edge(mysignal) inside an always @ (posedge clk) because the clk edge won't coincide with the transition on mysignal. What you do is keep a delayed copy of mysignal (what it was before the current clk event) and use a bit of logic to see that there is a difference between the current value and the previous value.
Like this:
https://www.chipverify.com/verilog/verilog-positive-edge-detector