My first FPGA code

[lawrence11]

You need to go back to basics, and describe succinctly what you are trying to do. In your current code you don't use spi_mosi at all, so I am not sure it acutally does anything

Thanks you hamster, I love these sort of discussions, they are very elightening.

But I am confused by what you said, because I am just using the same method that he is using

http://referencedesigner.com/tutorials/verilog/verilog_32.php

He writes : assign r_next = {s_in, r_reg[N-1:1]};   ------> I write: assign {some_connection,important_byte}={spi_mosi, some_string[n-1:1]};

Basically the same as he, but since I have 2 different datatypes I concatenate immediatly. What am I suposed to do to be like him but seperate my some_string before I make it available for
higher up modules. I am just trying to apply an example to my case, wich is a bit different.

module  spi_rcv (important_byte,some_connection);

Like I said, should I totally ignore any organization, just 1 contiguous register, externalize those wires in my module, then  bit mask in the higher up module the 8 bit and 176 bits there.

Like this---->  module spi_rcv (all_my_wires);

[lawrence11]

Ok Hamster, is this a better form of reset? Or does it absolutely should be be tied to the spi_clock edge occurence? Am I...incuring latches due to timing bullshit if I use an asynch reset?

?If so hurray !!!! , Latches... Yeah!!! awesome. I'll never get that I said to myself, that's just complicated stuff experts deal with.

                  

Code: [Select]

                                                always  begin //here I guess I am just using the fastest internal clock possible?
if (reset_spi_reg=='b1) begin
                        some_string<=0; //
assign{some_connection,important_byte}=some_string; // Is this even relevant since I should have a reset line across every ram bit? I'm confused
     

         end
end  
   

     

         always @(negedge spi_clk) begin
// yeah I use negative, because my pin is a neg edge signal, do I GAIN EFFICIENCY in LUTS?
//doing negedge things with negedge pins?? because if its bad I'll just use posedge
         

            if (reset_spi_reg == 0) begin //

                     
                     

[hamster_nz]

Ok Hamster, is this a better form of reset? Or does it absolutely should be be tied to the spi_clock edge occurence? Am I...incuring latches due to timing bullshit if I use an asynch reset?

It still isn't the design pattern that the synthesis tools expect.

For your chosen FPGA platform you want to find the equivalent 'style guide' - for Xilinx Vivado it is https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug901-vivado-synthesis.pdf and for Altera it is https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/qts/qts_qii51007.pdf
.

As a gross simplification, the tools look for these patterns and then maps them onto the FPGA hardware. If you use the pattern the tool is expecting to see, you get the result you are hoping for.

And it is also the same pattern that other HDL writers are expecting to see, and so will intuitively understand - if you do something in an odd way, people will start looking at the code sideways as they try to work out what patterns you are using.

The recommended pattern for Vivado for something with inputs ("DI"), outputs ("DO"), an asynchronous reset ("ARST") and a clock ("CLK") is:

Code: [Select]

module EXAMPLE (DI, CLK, ARST, DO);
  input [7:0] DI;
  input CLK, ARST;
  output [7:0] DO;
  reg [7:0] DO;

always @(posedge CLK or posedge ARST)
  begin
     if (ARST == 1'b1)
       DO <= 8'b00000000;
     else
        DO <= DI;
     endmodule
  end

(so I stand corrected on using the "posedge" on a reset signal is the recommended way).

I must also point out that you don't use lots of these tiny five snippets to build your design - you merge the patterns into each other where it makes sense, and cross your fingers and hope that you don't give the synthesis tools the wrong ideas.

You also don't have to follow these patterns, but things work a lot smoother if you do.

[lawrence11]

Here is what I want

Save some stuff in a register, that can be reset to 0, and pass it to a main_design.=, in parallel format.

It would be nice to use block ram? Like I know these are flip flopsl, but there is alot more ram bits than there is flip flops.

Can I make this with ram bits and just have a some_string[2000:0], AND also somehow have a parallel connection on this ram, If I just access a single supreme datatype.

Because you "cant access" more than 2 things at the same time using RAM, but what if you only access "one huge thing".

[hamster_nz]

Well that is literally this:

Code: [Select]

`timescale 1ns / 1ps

module spi_rcv(
    input spi_clk,
    input spi_reset,
    input spi_mosi,
    output [7:0] important,
    output [15:0] the_rest
    );

   reg [23:0] shift_reg;
   
   assign important = shift_reg[23:16];
   assign the_rest = shift_reg[15:0];
   
always @(negedge spi_clk or negedge spi_reset)
   begin
      if(spi_reset == 1'B0) begin
         // Reset if spi_reset is low
         shift_reg <= 24'b0;
      end else begin
         // Must be the falling spi_clk that triggered us
         shift_reg <= {spi_mosi, shift_reg[23:1]};
      end
   end
endmodule

(I threw it through Xilinx ISE to check syntax was correct and checked resource usage - but didn't test bench it)

[lawrence11]

So this is gonna be a strictly flip flop thing, from the looks of it then. I thought this could be stored in ram bits, and then each ram bit could have a parallel connection to some inner logic.

Apparently, on the max10, there is only gonna be 1 flip flop per logic element, and there can be max of 25000 logic elements.

So if I use 2000 flips flops I use 10% of my logic elements, partly used.

[hamster_nz]

So this is gonna be a strictly flip flop thing, from the looks of it then. I thought this could be stored in ram bits, and then each ram bit could have a parallel connection to some inner logic.

Apparently, on the max10, there is only gonna be 1 flip flop per logic element, and there can be max of 25000 logic elements.

So if I use 2000 flips flops I use 10% of my logic elements, partly used.

If you do it this way, yes. If you want access to 2000 bits at the same time (i.e same clock cycle) you need 2000 storage elements that can be concurrently accessed. That requires 2000 flip flops. There is nothing particularly wrong with using 2000 FFs though, you might do this if you were trying to match a pattern in an input stream

If you only need to access a few bits at a time, you can write the bits to memory as they arrive, then recall them later.

Have a read of this to see what resources you can use in the MAX 10 see this PDF:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/m10_architecture.pdf

[lawrence11]

So basically, I need 2000 flip flops no matter what, because I need a constant presence of 2000 bits at the same time, wich I do.

I was under the impression that I could do a RAM register as wide as I wanted, but I can only access 1 register at a time( saw that in a video), wich in my case was perfect. But still, I need flip flops to store ot to connect in permanence to ram bits.

I understand now.

I will try to explore that pdf, but I fear it will be intense, more intense than 1000 page stm32 documents.

edit: not so bad this document, not so bad.

btw, I notice that quartus compilation report doesnt show me flips flops used, just logic elements, registers, memory bits., but the xilinx compilation report seems to tell people, from images I saw, am I looking at the right place?

[hamster_nz]

So basically, I need 2000 flip flops no matter what, because I need a constant presence of 2000 bits at the same time, wich I do.

No, should you need to use the value stored in all 2000 bits at the same time (i.e. in the same tick of the clock) you need to have 2000 flip flops.

If you need to store 2048 bits but only need to access them eight at 8 bits at a time, then you could use a 256x8 RAM memory block.

The other slight complication is that (as a rule of thumb) memory blocks can only be initialized when the FPGA is configured/loaded. So you can not reset all 256 entries to zero when the reset signal is asserted. It would take your logic 256 cycles to write zeros to each address in the memory block.

Sure, you can code to set every element in the array to zero when reset is asserted, and it will give you slow, bulky logic that will do that rather than using the way-more efficient memory blocks.

Once again, you need to choose a design pattern that you know will map onto the physical RAM blocks available in your FPGA. So at least skim-reading the style guide to see what can work is time well spent.

[lawrence11]

Anybody know whats wrong with my code? spi_rcv compiles and was made by hamster_nz, and spi_rcv_tb is my testbench code, it was made by me and doesnt work.

Hamster, how would you do this? with a $readmemb please, I wanna test this feature.

So I started by assign variable=1 or0, and then 1'b1 and 1'b0, still not work

Code: [Select]

module spi_rcv(
    input spi_clk,
    input spi_reset,
    input spi_mosi,
    output [7:0] important,
    output [15:0] the_rest
    );

   reg [23:0] shift_reg;
   
   assign important = shift_reg[23:16];
   assign the_rest = shift_reg[15:0];
   
always @(negedge spi_clk or negedge spi_reset)
   begin
      if(spi_reset == 1'b0) begin
         // Reset if spi_reset is low
         shift_reg <= 24'b0;
      end else begin
         // Must be the falling spi_clk that triggered us
         shift_reg <= {spi_mosi, shift_reg[23:1]};
      end
   end

endmodule

Code: [Select]

`timescale 1ns/100ps

module spi_rcv_tb;
wire spi_clk,spi_mosi,spi_reset;
reg [h:0] message;
parameter h=23;
reg [15:0] bit_indexer;// not used now, using a local reg inside task.

spi_rcv spi_rcv_inst(.spi_clk(spi_clk),.spi_mosi(spi_mosi),.spi_reset(spi_reset));

initial
       begin
$readmemb("message.txt",message);
assign spi_reset=1'b1;
assign spi_clk=1'b1;
end

task send_spi_task;
reg [15:0] i; // indexer can I initialize here?
reg [7:0] f;// frequency in ns can I initialize here?

           begin
  i=0;   // or here?
  f=50; // or here?
 
     if(i<h+1) begin
  assign spi_clk=1'b1;
  assign spi_mosi=message[i]; // how to express in terms of 1'b1 or 1'b0???
  #50
  assign spi_clk=1'b0;
  i=i+1;
  #50;
  end
  end
endtask

endmodule

[lawrence11]

heres another contribution, another nice image I made.

[hamster_nz]

I am not experienced at Verilog test benches. But this should get you at least started. It is based loosely off of your code:

Code: [Select]

`timescale 1ns/100ps

module spi_rcv_tb;

parameter h=23;

reg spi_clk,spi_mosi,spi_reset;
wire [7:0] important;
wire [15:0] the_rest;

reg [h:0] message;
reg [15:0] i;

spi_rcv spi_rcv_inst(
   .spi_clk(spi_clk),
   .spi_mosi(spi_mosi),
   .spi_reset(spi_reset),
   .important(important),
   .the_rest(the_rest));

initial
   begin

//       $readmemb("message.txt",message);
      message     = 24'b100011000110001100011001;
      spi_reset   = 1'b1;
      spi_clk     = 1'b1;
      spi_mosi    = 1'b0;

      // A few clocks before reset
      for(i = 0; i < 3; i = i + 1) begin
         spi_clk=1'b1;
         #50
         spi_clk=1'b0;
         #50;
      end

      // Assert the reset
      spi_reset   = 1'b0;

      // A few clocks in reset
      for(i = 0; i < 3; i = i + 1) begin
         spi_clk=1'b1;
         #50
         spi_clk=1'b0;
         #50;
      end

      // Release the reset
      spi_reset   = 1'b1;
           
      // Now start presenting the data
      i=0;   // or here?
      f=50; // or here?
      for(i = 0; i < 30; i = i + 1) begin
         spi_clk=1'b1;
         if(i<h+1) begin
            spi_mosi=message[i]; // how to express in terms of 1'b1 or 1'b0???
         end
         #50
         spi_clk=1'b0;
         i=i+1;
         #50;
      end
     
      // Test bench finished
      $finish;
   end
           
endmodule

It doesn't test everything - just that the reset works and that data bits are clocked through the shift register, (matching your image for what you are trying to implement).

I didn't include using '$readmem' because:

a) You know what you want to do (use "$readmem()"), but not how to do it. That doesn't add up. Somebody who is as new to Verilog as you are would not have thought of this, however you know the precise name of the function.

b) You have far more pressing things to work on than reading data from external files. For now stick with using data declared explicitly in your test bench.

c) File names and locations will be different depending on the tools you are using and how you have set your project up. I don't want to make more problems  finding out where you should put your data files during simulation when using your toolset.

[lawrence11]

Thanks hamster , as always.

But honestly I am getting frustrated by this language, I try to follow documents, watch videos, read notes, wich say in testbenches you should use tasks.

They assign stuff inside the task, just like I do, and I get an error? What gives?

Whats wrong on the left hand side, I am doing exactly like they do.

[lawrence11]

Ok Hamster, I am not satisfied, because I dont understand my mistakes. But since you dont use Verilog I guess this is hard for you.

I read a few things about tasks, Ok , I wanna explore this keyword and see what it does. Some people say you should program testbenches using this.

Is anybody here competent enough in Verilog to make a simple test bench, using a "TASK" that doesnt give you error, using this simple spi_rcv that compiles.

I dont wanna start off leaving dark corners, and crossing out scary words of a language.

And I dont really have any pressing matters, I just wanna mess around and complete a project from A to Z, so that I can mess around further and maybe get good.

But if I start off leaving dark corners I cant get good.

[hamster_nz]

Your code didn't work because you never start the task in your initial block.

See https://www.chipverify.com/verilog/verilog-tasks

[lawrence11]

Aaaaa, I see. I defined but didnt call. Makes sense. Boy... These compiler messages should say better things honestly, cant they make this an educative experience and provide good messages?

Guess we see now who done these things and can spot a problem in 30 seconds, vs the people who cant analyze @ the speed where these questions are nothing but a sentence.

Heres another question mark?

The whole file compiles but I cant see any pulses. Now I'm thinking my workflow is wrong.

edit: oops, sim time. 100ps

Anyways, I still should see all my stuff from both my modules on the object tab

[lawrence11]

file


AAA simulation run time.

Anyways I hate this simulator, you cant even clear the dam screen without clicking 3 buttons

still, why cant I see both my stuff in spi_rcv and spi_rcv in the object tab?

Its like, I cant get more than 2 modules in objects?

[rstofer]

But if I start off leaving dark corners I cant get good.

If you want to explore all the corners of Verilog (or anything, really) you better set aside a very long time to do it.  There is a natural progression from newbie to expert and time is the main ingredient.  And lots of code!

It would be better to progress along with a structured set of tutorials and get to these corner conditions when they actually come up.  Everybody around here knows more about VHDL than I do yet I can still build complex systems using just a very few features of the language.  Sure, all the experts would immediately trounce on my code and show where it is seriously deficient but I don't worry about that because I know the systems actually work.

In none of my projects have I ever used a procedure or function.  I have never used the simulator either.  I write code for synthesis only and I do my debugging with a logic analyzer using actual hardware.  Simulation is not hardware!

[lawrence11]

I feel like going that route as well, just run it in hardware and probe.

Problem is that the synthesis can takes like 15 minutes sometime.

I read a thread where somebody took like 7 days to synthesize.

[lawrence11]

I know what you are telling yourselves.

"He is a high maintenance whiny noob boy."

WRONG!

This is BULLCRAP!

Tasks, synthesis, programming style that suit your FPGA...

When are they gonna make this simple? And write warnings take more things into account.

[rstofer]

I feel like going that route as well, just run it in hardware and probe.

Problem is that the synthesis can takes like 15 minutes sometime.

I read a thread where somebody took like 7 days to synthesize.

When I moved from Xilinx ISE to Xilinx Vivado, build time went through the roof.  So I built up a faster computer with an I7-7700K and a 1TB SSHD along with 32GB of very fast memory.  It's still not instantaneous but it's not bad.  I can build a complete RISC processor in less than 3 minutes but the project is only a couple of thousand lines.

You aren't going to run into week long builds any time soon or on chips that hobbyists can afford to buy.

On the same machine, using ISE, I can build a 10,000 line project in about 2 minutes.  That's within my short attention span.

Here's why I never got started with simulation:  I envisioned a situation where the CPU is booting the OS and a few thousand instruction in, things goes sideways because some instruction had a side effect I didn't code.  I wanted the processor to run a factory disk image without modification.  I couldn't even figure out how to get to that point in the simulation and since I was using 1-hot encoding on a 120 state FSM, I would have to display 120 signals (or somehow get a hex value) just to know where I was in executing some instruction.  I didn't understand how to do that with a test bench so I never bothered to learn how to use the simulator.

Simulation of trivial logic blocks seems pretty straightforward.  Debugging an entire computer system (CPU, Card Reader, Printer, Typewriter, Keyboard, Disk Drive and Plotter) is a little more involved.  I didn't see where simulation brought anything to the dance.  It's not like 'wait for 10 ns' synthesizes.

Everybody has their own approach.  Mine is undoubtedly wrong but it works for me.

[rstofer]

When are they gonna make this simple? And write warnings take more things into account.

Only the high priests of logic design get into HDL and FPGA or ASIC hardware design.  Mere mortals need not apply!  Arduino coders aren't even in the same league.  Hardware is called hardware because it is hard!

Xilinx has a ton of documentation as does every other manufacturer.  So, all you have to do is read it!  The problem is, you won't understand most of it because you aren't up against a problem that some particular application note deals with.  You can realistically only read the ones that apply, when they apply.  But it's all out there.  There are books, YouTube Videos (kudos to VHDLWhiz.com) and all kinds of training material.  Again, it won't stick unless you have an application.

I highly recommend newcomers start simple:  Build the LC3 (or LC3b) RISC processor from what you can find on the web (it's all there) or from the book by Patt and Patel
https://www.amazon.com/Introduction-Computing-Systems-Gates-Beyond/dp/0072467509
No HDL is given, they build the machine using microcode and this would be a workable solution in some HDL as well.  In fact, oversize the microcode store, use a .hex file to include the microcode and the processor is easily expandable.  It's a really nice project that includes all of the usual building blocks.

[lawrence11]

When are they gonna make this simple? And write warnings take more things into account.

Only the high priests of logic design get into HDL and FPGA or ASIC hardware design.  Mere mortals need not apply!  Arduino coders aren't even in the same league.  Hardware is called hardware because it is hard!

Xilinx has a ton of documentation as does every other manufacturer.  So, all you have to do is read it!  The problem is, you won't understand most of it because you aren't up against a problem that some particular application note deals with.  You can realistically only read the ones that apply, when they apply.  But it's all out there.  There are books, YouTube Videos (kudos to VHDLWhiz.com) and all kinds of training material.  Again, it won't stick unless you have an application.

I highly recommend newcomers start simple:  Build the LC3 (or LC3b) RISC processor from what you can find on the web (it's all there) or from the book by Patt and Patel
https://www.amazon.com/Introduction-Computing-Systems-Gates-Beyond/dp/0072467509
No HDL is given, they build the machine using microcode and this would be a workable solution in some HDL as well.  In fact, oversize the microcode store, use a .hex file to include the microcode and the processor is easily expandable.  It's a really nice project that includes all of the usual building blocks.

I'm just a mere mortal, but I'm like a bulldog mortail, I never let go. I know all I'm missing is a bit of education, now if I had a dedicated teacher to answer my questions, I would become a high priest pretty frikkin fast.

Those kids at school got an edge, they ca do the homework and ask questions, whie the rest f us, get stuck in the mud with crap like "documentation".

[rstofer]

Those kids at school got an edge, they ca do the homework and ask questions, whie the rest f us, get stuck in the mud with crap like "documentation".

Do you expect the average college professor to know the state-of-the-art in HDL programming?  My guess is they max out somewhere just beyond 'blink an LED'.  There are exceptions, of course, but I wouldn't count on learning cutting edge stuff in a university setting.

The way to do it is to write code.  Then watch some videos and see if there are better ways to write code.  Each iteration improves on the prior incantation.  What is almost certain is that you can't get 10 years experience in much less than 10 years.  Read books and see how they coded a similar project.

Sure enough, your time will be spent about evenly split between documentation/app notes and writing code.

Here is some tutorial stuff from Intel (Altera) that also references prerequisites.
https://www.intel.com/content/www/us/en/programmable/support/training/course/ihdl230.html

Pick a project, start writing and when it works, throw it out and do it again with style.  The best Fortran programs were written when the programmer dropped the box of punched cards.  The story of my life circa 1970...

[NorthGuy]

Those kids at school got an edge, they ca do the homework and ask questions, whie the rest f us, get stuck in the mud with crap like "documentation".

Asking questions will not take you very far ... If you don't give up, you will soon get to the point where your questions are best answered by reading "documentation".