RUMOR: Intel looking to buy Altera

[Stonent]

http://www.forbes.com/sites/aarontilley/2015/03/28/intel-altera-acquisition-rumor/

[techydude]

rumor no more:

http://www.itnews.com.au/News/404713,intel-to-buy-altera-for-22-billion.aspx

[Richard Crowley]

Acquisition completed....
http://newsroom.intel.com/community/intel_newsroom/blog/2015/12/28/intel-completes-acquisition-of-altera

[MT]

The future:

Words such as "expects", "intends", "plans", "believes", "seeks", "estimates", "continues", "may", "will", "should", and variations of such words and similar expressions are intended to identify forward-looking statements.
 
Statements that refer to or are based on projections, uncertain events or assumptions also identify forward-looking statements. These statements are not guarantees of results and are subject to risks and uncertainties that could cause actual results to differ materially from those anticipated in the forward-looking statements.

[Armxnian]

"We will apply Moore's Law to grow today's FPGA business"

Uh... we need new tech like quantum computing, not a 10% increase in CPU/FPGA performance every year...

[AndyC_772]

Why?

My main complaint about Altera products is that they're way too expensive. A small FPGA like an EP4CE6 is still about £8 and has been for years; they've concentrated on bigger / faster / costlier, and completely failed to expand the range into smaller, lower cost components.

Maybe if Intel are genuinely interested in making IoT products, then that'll mean more FPGAs targeted at the consumer market. That's a good thing, IMHO.

[andersm]

The future:

Haven't you ever seen a press release from a publicly listed company before?

[EEVblog]

"We will apply Moore's Law to grow today's FPGA business"

One does not "apply Moore's law" like ohms law 
You simply continue to innovate process technology, and maybe, with hindsight, "Moore's law" will still hold after that iteration.

[grumpydoc]

"We will apply Moore's Law to grow today's FPGA business"

One does not "apply Moore's law" like ohms law 
You simply continue to innovate process technology, and maybe, with hindsight, "Moore's law" will still hold after that iteration.

Indeed - Moore's "law" was merely an observation

It is amazing that we have continued to "keep up" but sooner or later we're going to start hitting some insurmountable physical limits.

[Richard Crowley]

Haven't you ever seen a press release from a publicly listed company before?

Apparently he hasn't.  God save us from the lawyers and the bean-counters.
But mostly from the Idiots who bring lawsuits against companies for thinking that projections are some kind of guarantee.  They don't even know what they will have for lunch tomorrow   

[Howardlong]

I wonder what they'll do with the ARM SoCs.

[poorchava]

Why?

My main complaint about Altera products is that they're way too expensive. A small FPGA like an EP4CE6 is still about £8 and has been for years; they've concentrated on bigger / faster / costlier, and completely failed to expand the range into smaller, lower cost components.

Maybe if Intel are genuinely interested in making IoT products, then that'll mean more FPGAs targeted at the consumer market. That's a good thing, IMHO.

Well,  I think Altera and Xilinx never aimed for the low-end market. This has been Lattice's and Actel's territory for some time.

Sent from my HTC One M8s using Tapatalk.

[marshallh]

RTFM for answers to all your questions:
http://intelacquiresaltera.transactionannouncement.com/wp-content/uploads/2015/11/CustomerFAQ_FINALNov30.pdf


The short version is that nothing will change, at least in the short term, other than becoming Intel PSG and possibly new markings.
By teh way, if you RFQ the cheap parts and expensive parts, you'll find that you can only get maneuvering room on the pricey ones. Costs of the smaller devices are dominated by die size and packaging. (Die size of a EP4CE6 is still pretty big...) And once you have this size of a die, there's no reason to not put tons of IO pads around the periphery.

[Howardlong]

RTFM for answers to all your questions:
http://intelacquiresaltera.transactionannouncement.com/wp-content/uploads/2015/11/CustomerFAQ_FINALNov30.pdf

The short version is that nothing will change, at least in the short term, other than becoming Intel PSG and possibly new markings.

Regrettably almost not worth the paper it's written on. If you've ever been at the sharp end of an M&A you'll know that soothing remarks like these are part and parcel of it.

They may have "no plan to discontinue existing products" now, at least not that they'll admit to, but that's exactly what all takeovers state, until a few months time...

It's also difficult to understand the continuous attempt to mention IoT, I see little if any fit for Altera parts in consumer driven products unless the pricing and marketing is dramatically reshaped, which it might well be.

[marshallh]

I'm not sure what attraction to IoT garbage is. Literally nothing Altera makes is suitable for IoT applications. Seems like misguided industry hype.

You are probably right about the future plans. If they restructure with dollar signs as the target, they'll be stupid to not axe the lowend parts and only keep the highend families. At which point we will be looking elsewhere...

[Armxnian]

One does not "apply Moore's law" .

That is exactly what one does. As long as Intel satisfies another cycle of Moore's law, customers will flock. Observation in the past or not, they have taken advantage and used Moore's law as a cover up for what they are really capable of. They have zero real competition in the consumer market and are also dominant in many enterprise environments. Anything that takes some of their market share and revenue away is kept alive so they don't run into trouble with the law in regards to being a monopoly. Their business side is as genius as their engineering department. They release only what they need to keep "innovating". Intel has their plans laid out for years to come. They anually "leak" some of it to keep us salivating over the next 8 core CPU.

[Psi]

Had to be done

[miguelvp]

Both Google and Microsoft (Bing) use FPGAs on their data centers or at least they are experimenting with that notion.

I could definitely use a Xeon processor with FPGA fabric, might not happen yet, but it's coming.

Think about it, configurable hardware driven protocols on a data center saving some watts.

Maybe Intel is not saying much about it yet, but an FPGA co-processor is pretty cool and I bet it's in the works.

[Psi]

imagine a cpu pipeline with programmable hardware instructions.

Or a cpu that automatically preemptively configures itself to replace common instruction sequences into a single instruction in hardware.

[Armxnian]

Why use a CPU then in that case? The purpose of a CPU is to run everything well, not a single thing ridiculously fast. What would your product lineup be? 10 different processors with different frequencies and core counts, multiplied by 50 different versions that excel at a single operation? The other option would be to have a single modern cpu that excels at many different tasks? Then you have a 50GHz i7. Neither of those two are realistic.

A co processor fpga communicating via the pcie bus sounds cool, kind of like what a gpu does. But what are the practical uses, and why hasen't it already been done? More and more instruction sets are being added with every generation, seems like it's working pretty well.

That customer FAQ linked on the previous page summarised it pretty well. Intel just wants its name on more stuff. Nothing more.

[AndyC_772]

Configurable peripherals in a small microcontroller would be nice. Suppose I want to have a processor read a value from an ADC at exactly regular intervals.

One option would be to set up a timer. Maybe it has a couple of outputs; one which can toggle a GPIO to start acquisition, and then another output a short time later which calls an ISR. The ISR wiggles a few more GPIOs, or maybe kicks off a DMA transfer which in turn uses an SPI peripheral to suck the data out of the ADC. Then, when the DMA transfer is complete, another ISR is called which wiggles another GPIO, sticks the ADC result in a buffer, and signals to the foreground task that it's available.

All this is a PITA to set up, as well as taking up potentially valuable CPU time.

How much better would it be to simply create a peripheral in programmable logic which does exactly this? Kick off a timer at start up, wiggle pins as necessary, then only signal the host CPU when the final data is already in a FIFO?

Better yet, signal the host CPU when that ADC data has already been filtered, analysed, averaged, interpolated, checked for outliers and generally passed as valid and meaningful to the top level application?

FPGA fabric in a CPU would be a great thing, but not to make the CPU faster.

[daqq]

A co processor fpga communicating via the pcie bus sounds cool, kind of like what a gpu does. But what are the practical uses, and why hasen't it already been done? More and more instruction sets are being added with every generation, seems like it's working pretty well.

Actually, there are specific cards that do this - though they are mostly specialized industry specific things. See:

http://www.nallatech.com/

At the moment it's useful for high performance computing, network acceleration and such. I'm pretty sure people can up with ways to use an FPGA cooprocessor once they are no longer more expensive than several computers.

See: https://newsroom.intel.com/docs/DOC-1512 - while this is not meant as a cooprocesor to offload the heavy math and such, it's still a step to that place.

FPGA fabric in a CPU would be a great thing, but not to make the CPU faster.

I can imagine software specific acceleration being outsourced to an FPGA rather than use the CPU. Making effectively your own instructions as the software needs would give you far more power. Just look at how well the software industry has adapted to using GPU acceleration. Now imagine say, a database searcher/filter done in hardware - you could just stream a whole database through a bunch of logic blocks without the CPU even looking at the content, a pre"compiled" logic could check against a bunch of conditions on the run in a pipe line like structure, stick those that comply to the search into an outgoing FIFO.

How much better would it be to simply create a peripheral in programmable logic which does exactly this? Kick off a timer at start up, wiggle pins as necessary, then only signal the host CPU when the final data is already in a FIFO?

Look at the PSoC devices from Cypress.

[timb]

Configurable peripherals in a small microcontroller would be nice. Suppose I want to have a processor read a value from an ADC at exactly regular intervals.

One option would be to set up a timer. Maybe it has a couple of outputs; one which can toggle a GPIO to start acquisition, and then another output a short time later which calls an ISR. The ISR wiggles a few more GPIOs, or maybe kicks off a DMA transfer which in turn uses an SPI peripheral to suck the data out of the ADC. Then, when the DMA transfer is complete, another ISR is called which wiggles another GPIO, sticks the ADC result in a buffer, and signals to the foreground task that it's available.

All this is a PITA to set up, as well as taking up potentially valuable CPU time.

How much better would it be to simply create a peripheral in programmable logic which does exactly this? Kick off a timer at start up, wiggle pins as necessary, then only signal the host CPU when the final data is already in a FIFO?

It exists. Check out the Cypress PSoC line. It's between an FPGA and CPLD in terms of performance. Can be programmed in VHDL, with a Schematic interface *or* you can directly program the custom ALU bits.

They're very nice and full of awesomeness.


Sent from my Smartphone

[AndyC_772]

Thanks guys, will check them out.

[andersm]

Intel has their plans laid out for years to come.

Given that it takes around 4 years to develop processors of that complexity, you'd bloody well hope they have. Any company that doesn't have some kind of a roadmap is pretty sure not to be very long-lived.

Unless there's something that's been worked on in secret, I can't imagine there will be any product announcement for five years, provided Intel are even interested in putting their cores in FPGAs. The most visible change will probably be Altera pushing Wind River even harder as the preferred software provider for their SoCs.