VHDL Port Declaration issues in Lattice Diamond

[MuriTheMyth]

Hi folks:

I'm new to Lattice Diamond and I ran into some weird problem when trying to work in there.

As shown in the picture, the port "clk" and "s" are declared in the same line. But the first script with "clk" in line 17 passed the syntax check, and the second with "s" in the same place failed.

I tried to search online and I still can't see why.

A big thank you for your time and patience in advance.

Sincerely,
Muri

[SiliconWizard]

Shouldn't it be

Code: [Select]

architecture bhv of srlatch

[coppercone2]

I would consider bribing the port authority