FNIRSI-1013D "100MHz" tablet oscilloscope

[gadak]

Not work. And installing the firmware deletes the calibration data

[tokar]

I confirm, it does not work (ch 2, 50mV/div).

[Atlan]

Only one sector on the sd card is written and there are more variables.

I don't know whether to enable writing to 2 sectors and change the control from 256 to 512.

Or move offsets. I assume a 16bit record needs 2 positions. 9 values (16bit)  will be written from offset 10 to 28

#define CHANNEL1_SETTING_OFFSET                    10    // 9*16bit   
#define CHANNEL2_SETTING_OFFSET                    40    // 9*16bit   
#define TRIGGER_SETTING_OFFSET                       70    // 8*16bit   
#define OTHER_SETTING_OFFSET                         100   // 9x16bit   
#define CURSOR_SETTING_OFFSET                      130   // 6x16bit
#define MEASUREMENT_SETTING_OFFSET          160   //26*16bit
#define CALIBRATION_SETTING_OFFSET              200   //14*16bit
#define INPUT_CALIBRATION_SETTING_OFFSET 230   //14*32bit

It does not contain the area where the calibration data is. I move the values a bit and it will work.

try this:

[Atlan]

I converted it to multiples of 16.

PC, you don't have a table somewhere about what the sampling frequency is if the value 2000 is written into the fpga.  In the long time base mode.  I assume that it is possible to change the frequency in order to achieve more uniform sampling when changing from about 100ms to 50s

[Atlan]

It works?

[pcprogrammer]

I converted it to multiples of 16.

PC, you don't have a table somewhere about what the sampling frequency is if the value 2000 is written into the fpga.  In the long time base mode.  I assume that it is possible to change the frequency in order to achieve more uniform sampling when changing from about 100ms to 50s

Within the FPGA there is a 32 bit counter to divide the clock down. The value set for the sampling frequency is used as the divider, but I need to consult my work to give the formula and the clock frequency. Will get back to you on this.

Edit: I looked at the verilog file here.

There is a variable "sample_rate_divider" that is used to make the sample clock. It is set with the FPGA command 0x0D.

The main clock runs at 200MHz. When "sample_rate_divider" is 0 the 200MHz is divided by 2 and the sample clock is 100MHz. This is the clock signal for the ADC's and the sample memory. For the software it means a sampling rate of 200MSa/s.

When set to 1 the 200MHz is divided by 4 giving a sample clock of 50MHz. For 3 it means dividing by 8 giving 25MHz.

The sample clock is based on the formula:  clk = 200MHz / ((sample_rate_divider + 1) * 2)
The sample rate is then:  rate = clk * 2

This only applies for when both ADC's are used to get the interleaved samples. When only reading data from one ADC the sample rate equals the clock rate.

[Atlan]

Well thank you.  So that I set the sampling frequency so that the samples are spread over the interval according to the selected time per div. 50s/div..... 100ms/div

[tokar]

...
try this:

Yesterday I didn't see the binary file. Today I downloaded it and tried it. It calibrates normally. Positive and negative voltages are shown correctly on the screen.
I don’t like the autoset time (sometimes long) - from 2 to 14 seconds, but it works.
CH 2 manual gain does not work.

[Atlan]

Implemented long time mode, with support for trigger auto, normal, single. v0.023g



The setting of the falling rising edge must be programmed. Correct overview of waveforms and images in long time mode.
Autoset from version 0.022f

Fixed some errors that were found.

[gadak]

Firmware 0.023g Calibration is successful, but auto set works very slowly, hangs up if the measurement range changes downward in voltages. For example, at 11 to 12 volts auto set works faster than from 9 volts to 1 volt. Ch2 less than 6 mV does not display ch1 less than 3 mV does not display

[tokar]

v0023g. Range 5 V/div.
Channel 1, Ulim =21.7V
Channel 2, Ulim =20.5V
If you press auto-tune when the signals are limited (red), the device goes into a stupor (“beam” and the pointers move to the edges of the screen, the voltmeter turns off, the range value disappears). You can get out of the situation by reducing the voltage below the limiting threshold and pressing auto-set (does not work separately, manual mode and turning off the power do not help). Under the same conditions, and the polarity changes to negative, generation (excitation) occurs. The way out of the situation is similar.

[Atlan]

PC: Is it possible to use the SPI interface to control the AD9833 generator?

[pcprogrammer]

PC: Is it possible to use the SPI interface to control the AD9833 generator?

In theory I would say yes, but you need an additional chip select signal and adapt the software to disable the use of the FLASH and control the new chip select. Also check the clock phase and polarity of the AD9833. The software might need to set that too when switching to the AD9833.

There are two free pins on the MCU, but connecting a wire to one of them might be a bit tricky.

The peripheral is described in the user manual, but as for all the other things in the chip it is sparse.

[Atlan]

If I remove the flash, can I use all the necessary pins?  Alternative firmware does not access the flash at all?

[pcprogrammer]

If I remove the flash, can I use all the necessary pins?  Alternative firmware does not access the flash at all?

Sure. For as far as I can recall it is now all done on the SD card, and the flash is not used, despite code being there to access it.

[tokar]

Maybe this will be useful:
data on 25Q16 at addresses 0x 1FD000 - 0x 1FD1F3 changes when loading a new version, calibrating, setting the time. It is possible that changes occur during other operations.

[Atlan]

Nothing should be written there...

In the long mode, programmed trigger to the rising or falling edge.

The hardware trigger does not work in long mode.  It works, but does not provide information whether it is a rising or falling edge.  So I turned it off.  And the detection is done by software.

I added a condition to the autoset for 5V/div, maybe it won't freeze when it's in red, I haven't tried.

[tokar]

v0023h.
Range 5 V/div. The signal (positive/negative) in limit mode works fine and does not freeze.
Viewing the recorded WAV (X-stretch/compress) is only possible through the ACQ menu. Briefly touching the screen causes the image to disappear (must change time/div). You need to open the image again. Is this how it should be? Or am I doing something wrong?
Pressing and holding your finger on the screen allows you to move the image around the screen - it works correctly.

[Atlan]

There were 2 subroutines for loading values ​​for long mode and erasing the display.  Since they were almost the same, I created one.  I probably forgot the condition for viewing wav.  It is also necessary to disable sampling change in browsing mode and adjust the ACQ menu.

[Atlan]

Since I have enough other work, this project has slowed down.  The plan is to divide the signal shift into the hardware part in real time, and the software part in wav mode.  That should solve the automatic problem.  Will anyone be interested in the assembly of the signal generator?  It will also lose the ability to run flood firmware.  Although there is the possibility of adding an i2c circuit to control the gain of the input amplifier for better sensitivity.  What would enable, leave the flash.

It would also be a nice project for a bachelor's thesis.  Take the flat, copy the layout, modify critical things, redo the input part, add the generator and rtc.  And finally, a new program for fpga.

[naiclub]

Since I have enough other work, this project has slowed down.  The plan is to divide the signal shift into the hardware part in real time, and the software part in wav mode.  That should solve the automatic problem.  Will anyone be interested in the assembly of the signal generator?  It will also lose the ability to run flood firmware.  Although there is the possibility of adding an i2c circuit to control the gain of the input amplifier for better sensitivity.  What would enable, leave the flash.

It would also be a nice project for a bachelor's thesis.  Take the flat, copy the layout, modify critical things, redo the input part, add the generator and rtc.  And finally, a new program for fpga.

I want to do this. Is there anyone who can do this? Can you take me to do it?

[pcprogrammer]

Get a cheap Arduino nano clone or STM32F103 based bluepill and an AD9833 module from aliexpress and connect them together. Search for some code on the net and stick it in to make it work.

Or check out for instance this article: https://www.instructables.com/Arduino-Controlled-AD9833-Function-Generator-With-/
Or this one https://circuitdigest.com/microcontroller-projects/build-your-own-function-generator-with-arduino-and-ad9833-module

Search on google for "arduino ad9833 dds signal generator" and you will find all sorts of projects like this.

[Atlan]

I was thinking of rebuilding the entire pcb of the oscilloscope.

[naiclub]

I was thinking of rebuilding the entire pcb of the oscilloscope.

Do you have a detailed circuit diagram? I happen to have a file of one person who is Russian. But when I try to compile the file and it doesn't go through, it's stuck here.

[alesfilip]

You need install RotaryEncoder Arduino Library