Author Topic: FPGA VGA Controller for 8-bit computer (Read 426425 times)

asmi · « **Reply #2450 on:** February 13, 2021, 01:03:28 am »

Quote from: BrianHG on February 12, 2021, 11:08:46 pm

DDR3 is as simple to run as DDR2, DDR except for the different power-up settings and a few new commands and # of clock cycles. Maybe a punishment for not writing your own HDMI transmitter would be writing your own DDR3.sv. Micron does have a DDR3 Verilog testbench code which was designed to validate/verify functionality of your DDR3.sv controller which you can run in ModelSim. Sorta like my testbench code which drives and tests the 3 Geometry unit sections wired together to render an output.

I'm afraid that's not going to be quite that simple. Even the minimal DDR3 frequency (303 MHz) is beyond what's possible to statically capture (i.e. write IO constraints such that P&R will ensure IO timings are always held over entire PVT range) on all FPGAs available to hobbyists. That means you will have to do a runtime calibration to find the right delay to capture data safely, as well as ensure proper alignment of DQ to DQS signals at the memory device side. Also due to fly-by routing these delays are going to be different for each byte group. And you will have to repeat these calibrations every once in a while at runtime because data alignment is dependent on temperature of dies.
To help illustrate the complexity, take a look at attached table which shows resources required for various external memory types for the same 72 bit data bus. As you can see, DDR3 requires quite a bit more resources than DDR2, and pretty much all of that additional logic goes towards calibration. If you care to read, Xilinx UG586 has very detailed explanation of how memory controller works, and can provide you with some insights even if you will end up rolling out your own.

BrianHG · « **Reply #2451 on:** February 13, 2021, 02:17:14 am »

That double extra LUT and gates is not from the ZQ CALIBRATION Long and Short pattern generator, or for it's timeout timer.

asmi · « **Reply #2452 on:** February 13, 2021, 03:39:49 am »

Quote from: BrianHG on February 13, 2021, 02:17:14 am

That double extra LUT and gates is not from the ZQ CALIBRATION Long and Short pattern generator, or for it's timeout timer.

Then what it is?

My point is I think you are trying to bite more than you can chew. To my knowledge, HW-agnostic DDR3 controller does not exist at this point, and there's got to be a reason for it.

Speaking of which - I have tried generating UniPHY-based DDR3 controller for MAX10 device (for the DECA boards I received today), and generator failed with some cryptic messages. Before I tried doing it for CV with the same results - it generates "something", but ultimately fails so I don't really know if whatever it's generated is usable or not. I've been using the most recent Quartus Lite version (20.1.1 I think) just to be sure. Have you tried generating it, and if so - did it work?

BrianHG · « **Reply #2453 on:** February 13, 2021, 04:35:54 am »

Quote from: asmi on February 13, 2021, 03:39:49 am

Quote from: BrianHG on February 13, 2021, 02:17:14 am
That double extra LUT and gates is not from the ZQ CALIBRATION Long and Short pattern generator, or for it's timeout timer.
Then what it is?

My point is I think you are trying to bite more than you can chew. To my knowledge, HW-agnostic DDR3 controller does not exist at this point, and there's got to be a reason for it.
Speaking of which - I have tried generating UniPHY-based DDR3 controller for MAX10 device (for the DECA boards I received today), and generator failed with some cryptic messages. Before I tried doing it for CV with the same results - it generates "something", but ultimately fails so I don't really know if whatever it's generated is usable or not. I've been using the most recent Quartus Lite version (20.1.1 I think) just to be sure.

Look at a DDR3 command table compared to a DDR2. DDR2 has only 2 different read and write commands. DDR3 has 4 different read and 4 different write commands depending on burst length you want to RX/TX. That is 2 fold the difficulty for the state machine, so, double the LUTs, unless you want to sacrifice performance. Yes, the calibration eats some additional gates, but not double the LUT unless ther developer of the new ram controller made some poor programming choices, or to achieve the higher required FMAX, there was no choice but to rely less on combinational logic and add LUTs.

The calibration is needed to the ram to work properly. If you are operating <=400MHz, you can trick the calibration by transmitting the test pattern a little late, like 500ps, then move your clock DQ & DQS phase back to 0ps during operation if you want to avoid re-calibration. There is no way running a 800MHz ram chip at 400MHz will make enough heat in the chip or your FPGA to throw out the timing by over over 500ps on a 800MHz ram chip with 1600mtps. So long as your FPGA is generating and driving the DDR3 clocks. With an external clock buffer, forget it, you need to continuously re-calibrate as too many uncertainties creep in over time.

As for the Quartus, if the DDR3 compiler give you a weird 'ERROR, like unfound linux command during generation', Nockieboy finally got his to compile. The DDR3 generator needs Linux runtime/command shell environment for Win10 installed with an added 'path' setting in the system. You would have to ask him as I'm still on Win7 and cannot use the latest Quartus ram compiler.

BrianHG · « **Reply #2454 on:** February 13, 2021, 04:54:09 am »

Lattice seems to have a configurable DDR3 verilog library function.

Also, with 1 single line change to my .bmp rendering test-bench, their Active_HDL runtime simulator seems to work fine. The setup.do also needs a few changes to match the available feature set. I'll upload the new testbench tomorrow which will support both ModelSim and ActiveHDL. I don't think this bug is connected to Xilinx, unless Xilinx was having trouble with the $fwrite (fpointer,"%u",'a32bitX15word-array') command. I had to change it to a loop which would point to each individual word in the array, 1 $frwite at a time to make ActiveHDL accept it.

I might have to install Xilinx to see why their RTL simulator wont work.
This testbench was not designed for gate level / timing simulation, purely RTL only.

Their simulation speed is comparable to ModelSim, just a little slower on the compile. Something like 4 seconds VS 2 seconds. Waveform view, scroll speed, command line functions are much better in modelsim.

asmi · « **Reply #2455 on:** February 13, 2021, 05:08:09 am »

Quote from: BrianHG on February 13, 2021, 04:35:54 am

There is no way running a 800MHz ram chip at 400MHz will make enough heat in the chip or your FPGA to throw out the timing by over over 500ps on a 800MHz ram chip with 1600mtps.

My FPGA gets up to 60°C (with heatsink attached!), and DDR3 chip is in mid-40. So there is quite a bit of temperature change. BGAs usually reject quite a bit of heat into the power/ground planes. And if your board is compact and has got other components which do the same (typically DC-DC converters are designed that way, and each FPGA board usually has a number of them), heat can actually ascend from those power/ground planes to chips and warm them up. Not no mention that heating reference planes and prepreg also changes their physical properties. I don't exactly know if it's bad enough for relatively low DDR3 frequencies (~400 MHz is very low as DDR3 JEDEC specs go all the way to 2133 MT/1066 MHz IIRC), but the effect is there, and can cause issues if your design is marginal to begin with.

I know that Xilinx DDR3 memory controller uses on-chip ADC with attached temperature sensor to help maintain calibration, and even with that it still does dummy reads every 1 ms (if the bus is idle) to maintain DQ/DQS timing. Again - not sure how necessary it really is for low frequencies, but the fact that they went into trouble implementing that tells me they think it's important enough for reliability. Their controller is guaranteed to work in entire PVT envelope, unlike many homebred ones which are typically only tested at "normal" lab conditions and so nobody knows what's gonna happen if you try running it in any other conditions.

Quote from: BrianHG on February 13, 2021, 04:35:54 am

As for the Quartus, if the DDR3 compiler give you a weird 'ERROR, like unfound linux command during generation', Nockieboy finally got his to compile. The DDR3 generator needs Linux runtime/command shell environment for Win10 installed with an added 'path' setting in the system. You would have to ask him as I'm still on Win7 and cannot use the latest Quartus ram compiler.

I have WSL2 installed, but it still doesn't work. Not sure about the "path" part though.

BrianHG · « **Reply #2456 on:** February 13, 2021, 05:17:42 am »

Sorry, it's not a path, but bash which needs to be installed. Discussion here:
https://community.intel.com/t5/Intel-Quartus-Prime-Software/DDR3-megawizard-generation-error-in-Quartus-20-1/td-p/1244332

BrianHG · « **Reply #2457 on:** February 13, 2021, 05:46:34 am »

Quote from: asmi on February 13, 2021, 05:08:09 am

but the effect is there, and can cause issues if your design is marginal to begin with.

Marginal? My PCB are tested running in an insulated heated oven at 125 degrees Celsius operating with consumer grade IC, but 125 degree caps for 24 hours before release. A single bit error is a fail. Before I learned my lesson, yes, I had some embarrassing field failures. Oven baked burn in is the only way to go when publicly releasing hardware. Non of my heat treated units have failed in the field.

However, I do \know how to manipulate Quartus to layout all it's IO pin buffers to the actual final clocked logic cell offering the tightest timing with reference to the PLL.

asmi · « **Reply #2458 on:** February 13, 2021, 01:41:42 pm »

Quote from: BrianHG on February 13, 2021, 05:17:42 am

Sorry, it's not a path, but bash which needs to be installed. Discussion here:
https://community.intel.com/t5/Intel-Quartus-Prime-Software/DDR3-megawizard-generation-error-in-Quartus-20-1/td-p/1244332

Did all of that - still doesn't work:

Code: [Select]

Info: DDR3C: Variation language : Verilog
Info: DDR3C: Output directory : D:\Andrey\Projects\Altera\DECA_DDR
Info: DDR3C: Generating variation file D:\Andrey\Projects\Altera\DECA_DDR\DDR3C.v
Info: DDR3C: Generating synthesis files
<html>Info: Generating <b>altera_mem_if_ddr3_emif</b> "<b>DDR3C</b>" for QUARTUS_SYNTH
<html>Info: "<b>DDR3C</b>" instantiated <b>altera_mem_if_ddr3_emif</b> "<b>DDR3C</b>"
<html>Info: "<b>DDR3C</b>" instantiated <b>altera_mem_if_ddr3_pll</b> "<b>pll0</b>"
Info: Generating clock pair generator
Info: Generating altgpio
Info: 
Info: *****************************
Info: 
Info: Remember to run the DDR3C_p0_pin_assignments.tcl
Info: script after running Synthesis and before Fitting.
Info: 
Info: *****************************
Info: 
<html>Info: "<b>DDR3C</b>" instantiated <b>altera_mem_if_ddr3_phy_core</b> "<b>p0</b>"
<html>Info: "<b>DDR3C</b>" instantiated <b>altera_mem_if_ddr3_afi_mux</b> "<b>m0</b>"
Error: Error during execution of "{C:/intelfpga_lite/20.1/quartus//../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally
Error: Execution of command "{C:/intelfpga_lite/20.1/quartus//../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt" failed
Error: /mnt/c/intelfpga_lite/20.1/quartus/bin64/uniphy_mcc.exe -ac_code sequencer_mc/ac_rom.s -inst_code sequencer_mc/inst_rom.s -ac_rom ../DDR3C_s0_AC_ROM.hex -inst_rom ../DDR3C_s0_inst_ROM.hex -header sequencer/sequencer_auto.h -vheader ../sequencer_auto_h.sv -ac_rom_init sequencer/sequencer_auto_ac_init.c -inst_rom_init sequencer/sequencer_auto_inst_init.c -DAC_ROM_USER_ADD_0=0_0000_0000_0000 -DAC_ROM_USER_ADD_1=0_0000_0000_1000 -DAC_ROM_MR0=0001000010001 -DAC_ROM_MR0_CALIB= -DAC_ROM_MR0_DLL_RESET=0001100010000 -DAC_ROM_MR1=0000001000100 -DAC_ROM_MR1_OCD_ENABLE= -DAC_ROM_MR2=0000000000000 -DAC_ROM_MR3=0000000000000 -DAC_ROM_MR0_MIRR=0001000001001 -DAC_ROM_MR0_DLL_RESET_MIRR=0001010001000 -DAC_ROM_MR1_MIRR=0000000100100 -DAC_ROM_MR2_MIRR=0000000000000 -DAC_ROM_MR3_MIRR=0000000000000 -DQUARTER_RATE=0 -DHALF_RATE=1 -DFULL_RATE=0 -DNON_DES_CAL=0 -DAP_MODE=0 -DGUARANTEED_READ_BRINGUP_TEST=0 -DMEM_ADDR_WIDTH=13 -DHARD_PHY=0
Error: UniPHY Sequencer Microcode Compiler
Error: Copyright (C) 2020  Intel Corporation. All rights reserved.
Error: Info: Reading sequencer_mc/ac_rom.s ...
Error: Info: Reading sequencer_mc/inst_rom.s ...
Error: Info: Writing ../DDR3C_s0_AC_ROM.hex ...
Error: Info: Writing ../DDR3C_s0_inst_ROM.hex ...
Error: Info: Writing sequencer/sequencer_auto_ac_init.c ...
Error: Info: Writing sequencer/sequencer_auto_inst_init.c ...
Error: Info: Writing sequencer/sequencer_auto.h ...
Error: Info: Writing sequencer/sequencer_auto.h ...
Error: Info: Writing ../sequencer_auto_h.sv ...
Error: Info: Microcode compilation successful
Error: /mnt/c/intelfpga_lite/20.1/quartus/../nios2eds/sdk2/bin/nios2-bsp hal sequencer_bsp .. --default_sections_mapping sequencer_mem --use_bootloader DONT_CHANGE
Error: nios2-bsp: Using /mnt/c/intelfpga_lite/20.1/nios2eds/sdk2/bin/bsp-set-defaults.tcl to set system-dependent settings.
Error: nios2-bsp: Updating existing BSP because sequencer_bsp/settings.bsp exists.
Error: nios2-bsp: Using SOPC design file ../pre_compile.sopcinfo found in ..
Error: nios2-bsp: Running "nios2-bsp-update-settings --settings sequencer_bsp/settings.bsp --bsp-dir sequencer_bsp --sopc ../pre_compile.sopcinfo --script /mnt/c/intelfpga_lite/20.1/nios2eds/sdk2/bin/bsp-set-defaults.tcl default_sections_mapping sequencer_mem use_bootloader DONT_CHANGE "
Error: child process exited abnormally
Error: Cannot find sequencer/sequencer.elf
<html>Error: An error occurred<br>    while executing<br>"error "An error occurred""<br>    (procedure "_error" line 8)<br>    invoked from within<br>"_error "Cannot find $seq_file""<br>    ("if" then script line 2)<br>    invoked from within<br>"if {[file exists $seq_file] == 0} {<br>		_error "Cannot find $seq_file"<br>	}"<br>    (procedure "alt_mem_if::util::seq_mem_size::get_max_memory_usage" line 14)<br>    invoked from within<br>"alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf""<br>    invoked from within<br>"set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf"]]"<br>    ("if" then script line 2)<br>    invoked from within<br>"if { !$do_only_rw_mgr_mc && !($bfm_mode || $hps_mode)} {<br>		set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequenc..."<br>    (procedure "generate_qsys_sequencer_sw" line 943)<br>    invoked from within<br>"generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0  $nios_hex_file_name $ac_rom_init_file_name ..."<br>    invoked from within<br>"set seq_mem_size_list [generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0  $nios_hex_file_name ..."<br>    ("if" else script line 2)<br>    invoked from within<br>"if {[::alt_mem_if::util::qini::qini_value alt_mem_if_seq_size_request 0] > 0} {<br>		set seq_mem_size [::alt_mem_if::util::qini::qini_value alt_mem_if_se..."<br>    (procedure "alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer" line 238)<br>    invoked from within<br>"alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}"<br>    invoked from within<br>"set qsys_sequencer_files_list [alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}]"<br>    (procedure "alt_mem_if::gen::uniphy_gen::generate_sequencer_files" line 3)<br>    invoked from within<br>"alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "DDR3" $tmpdir QUARTUS_SYNTH"<br>    invoked from within<br>"foreach generated_file [alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "DDR3" $tmpdir QUARTUS_SYNTH] {<br>		set file_name [file tail $genera..."<br>    (procedure "generate_synth" line 8)<br>    invoked from within<br>"generate_synth DDR3C_s0"
<html>Info: "<b>DDR3C</b>" instantiated <b>altera_mem_if_ddr3_qseq</b> "<b>s0</b>"
Error: Generation stopped, 1 or more modules remaining
<html>Info: Done "<b>DDR3C</b>" with 7 modules, 29 files
Info: DDR3C: Generating simulation model
<html>Info: Generating <b>altera_mem_if_ddr3_emif</b> "<b>DDR3C</b>" for SIM_VERILOG
<html>Info: "<b>DDR3C</b>" instantiated <b>altera_mem_if_ddr3_emif</b> "<b>DDR3C</b>"
<html>Info: "<b>DDR3C</b>" instantiated <b>altera_mem_if_ddr3_pll</b> "<b>pll0</b>"
Info: Generating clock pair generator
Info: Generating altgpio
<html>Info: "<b>DDR3C</b>" instantiated <b>altera_mem_if_ddr3_phy_core</b> "<b>p0</b>"
<html>Info: "<b>DDR3C</b>" instantiated <b>altera_mem_if_ddr3_afi_mux</b> "<b>m0</b>"
Error: Error during execution of "{C:/intelfpga_lite/20.1/quartus//../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally
Error: Execution of command "{C:/intelfpga_lite/20.1/quartus//../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt" failed
Error: /mnt/c/intelfpga_lite/20.1/quartus/bin64/uniphy_mcc.exe -ac_code sequencer_mc/ac_rom.s -inst_code sequencer_mc/inst_rom.s -ac_rom ../DDR3C_s0_AC_ROM.hex -inst_rom ../DDR3C_s0_inst_ROM.hex -header sequencer/sequencer_auto.h -vheader ../sequencer_auto_h.sv -ac_rom_init sequencer/sequencer_auto_ac_init.c -inst_rom_init sequencer/sequencer_auto_inst_init.c -DAC_ROM_USER_ADD_0=0_0000_0000_0000 -DAC_ROM_USER_ADD_1=0_0000_0000_1000 -DAC_ROM_MR0=0001000010001 -DAC_ROM_MR0_CALIB= -DAC_ROM_MR0_DLL_RESET=0001100010000 -DAC_ROM_MR1=0000001000100 -DAC_ROM_MR1_OCD_ENABLE= -DAC_ROM_MR2=0000000000000 -DAC_ROM_MR3=0000000000000 -DAC_ROM_MR0_MIRR=0001000001001 -DAC_ROM_MR0_DLL_RESET_MIRR=0001010001000 -DAC_ROM_MR1_MIRR=0000000100100 -DAC_ROM_MR2_MIRR=0000000000000 -DAC_ROM_MR3_MIRR=0000000000000 -DQUARTER_RATE=0 -DHALF_RATE=1 -DFULL_RATE=0 -DNON_DES_CAL=0 -DAP_MODE=0 -DGUARANTEED_READ_BRINGUP_TEST=0 -DMEM_ADDR_WIDTH=13 -DHARD_PHY=0
Error: UniPHY Sequencer Microcode Compiler
Error: Copyright (C) 2020  Intel Corporation. All rights reserved.
Error: Info: Reading sequencer_mc/ac_rom.s ...
Error: Info: Reading sequencer_mc/inst_rom.s ...
Error: Info: Writing ../DDR3C_s0_AC_ROM.hex ...
Error: Info: Writing ../DDR3C_s0_inst_ROM.hex ...
Error: Info: Writing sequencer/sequencer_auto_ac_init.c ...
Error: Info: Writing sequencer/sequencer_auto_inst_init.c ...
Error: Info: Writing sequencer/sequencer_auto.h ...
Error: Info: Writing sequencer/sequencer_auto.h ...
Error: Info: Writing ../sequencer_auto_h.sv ...
Error: Info: Microcode compilation successful
Error: /mnt/c/intelfpga_lite/20.1/quartus/../nios2eds/sdk2/bin/nios2-bsp hal sequencer_bsp .. --default_sections_mapping sequencer_mem --use_bootloader DONT_CHANGE
Error: nios2-bsp: Using /mnt/c/intelfpga_lite/20.1/nios2eds/sdk2/bin/bsp-set-defaults.tcl to set system-dependent settings.
Error: nios2-bsp: Updating existing BSP because sequencer_bsp/settings.bsp exists.
Error: nios2-bsp: Using SOPC design file ../pre_compile.sopcinfo found in ..
Error: nios2-bsp: Running "nios2-bsp-update-settings --settings sequencer_bsp/settings.bsp --bsp-dir sequencer_bsp --sopc ../pre_compile.sopcinfo --script /mnt/c/intelfpga_lite/20.1/nios2eds/sdk2/bin/bsp-set-defaults.tcl default_sections_mapping sequencer_mem use_bootloader DONT_CHANGE "
Error: child process exited abnormally
Error: Cannot find sequencer/sequencer.elf
<html>Error: An error occurred<br>    while executing<br>"error "An error occurred""<br>    (procedure "_error" line 8)<br>    invoked from within<br>"_error "Cannot find $seq_file""<br>    ("if" then script line 2)<br>    invoked from within<br>"if {[file exists $seq_file] == 0} {<br>		_error "Cannot find $seq_file"<br>	}"<br>    (procedure "alt_mem_if::util::seq_mem_size::get_max_memory_usage" line 14)<br>    invoked from within<br>"alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf""<br>    invoked from within<br>"set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf"]]"<br>    ("if" then script line 2)<br>    invoked from within<br>"if { !$do_only_rw_mgr_mc && !($bfm_mode || $hps_mode)} {<br>		set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequenc..."<br>    (procedure "generate_qsys_sequencer_sw" line 943)<br>    invoked from within<br>"generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0  $nios_hex_file_name $ac_rom_init_file_name ..."<br>    invoked from within<br>"set seq_mem_size_list [generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0  $nios_hex_file_name ..."<br>    ("if" else script line 2)<br>    invoked from within<br>"if {[::alt_mem_if::util::qini::qini_value alt_mem_if_seq_size_request 0] > 0} {<br>		set seq_mem_size [::alt_mem_if::util::qini::qini_value alt_mem_if_se..."<br>    (procedure "alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer" line 238)<br>    invoked from within<br>"alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}"<br>    invoked from within<br>"set qsys_sequencer_files_list [alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}]"<br>    (procedure "alt_mem_if::gen::uniphy_gen::generate_sequencer_files" line 3)<br>    invoked from within<br>"alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "DDR3" $tmpdir SIM_VERILOG"<br>    invoked from within<br>"foreach generated_file [alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "DDR3" $tmpdir SIM_VERILOG] {<br>		set file_name [file tail $generate..."<br>    (procedure "generate_verilog_sim" line 7)<br>    invoked from within<br>"generate_verilog_sim DDR3C_s0"
<html>Info: "<b>DDR3C</b>" instantiated <b>altera_mem_if_ddr3_qseq</b> "<b>s0</b>"
Error: Generation stopped, 1 or more modules remaining
<html>Info: Done "<b>DDR3C</b>" with 7 modules, 21 files
Info: Generated simulation scripts for Modelsim in D:/Andrey/Projects/Altera/DECA_DDR/DDR3C_sim/mentor directory.
Info: Generated simulation scripts for VCS and VCS MX in D:/Andrey/Projects/Altera/DECA_DDR/DDR3C_sim/synopsys directory.
Info: Generated simulation scripts for NCSIM in D:/Andrey/Projects/Altera/DECA_DDR/DDR3C_sim/cadence directory.
Info: Generated simulation scripts for Riviera-PRO in D:/Andrey/Projects/Altera/DECA_DDR/DDR3C_sim/aldec directory.

BrianHG · « **Reply #2459 on:** February 13, 2021, 02:08:46 pm »

Quote from: asmi on February 13, 2021, 01:41:42 pm

Quote from: BrianHG on February 13, 2021, 05:17:42 am
Sorry, it's not a path, but bash which needs to be installed. Discussion here:
https://community.intel.com/t5/Intel-Quartus-Prime-Software/DDR3-megawizard-generation-error-in-Quartus-20-1/td-p/1244332
Did all of that - still doesn't work:
Code: [Select]
Info: DDR3C: Variation language : Verilog Info: DDR3C: Output directory : D:\Andrey\Projects\Altera\DECA_DDR Info: DDR3C: Generating variation file D:\Andrey\Projects\Altera\DECA_DDR\DDR3C.v Info: DDR3C: Generating synthesis files <html>Info: Generating altera_mem_if_ddr3_emif "DDR3C" for QUARTUS_SYNTH <html>Info: "DDR3C" instantiated altera_mem_if_ddr3_emif "DDR3C" <html>Info: "DDR3C" instantiated altera_mem_if_ddr3_pll "pll0" Info: Generating clock pair generator Info: Generating altgpio Info: Info: ***************************** Info: Info: Remember to run the DDR3C_p0_pin_assignments.tcl Info: script after running Synthesis and before Fitting. Info: Info: ***************************** Info: <html>Info: "DDR3C" instantiated altera_mem_if_ddr3_phy_core "p0" <html>Info: "DDR3C" instantiated altera_mem_if_ddr3_afi_mux "m0" Error: Error during execution of "{C:/intelfpga_lite/20.1/quartus//../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally Error: Execution of command "{C:/intelfpga_lite/20.1/quartus//../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt" failed Error: /mnt/c/intelfpga_lite/20.1/quartus/bin64/uniphy_mcc.exe -ac_code sequencer_mc/ac_rom.s -inst_code sequencer_mc/inst_rom.s -ac_rom ../DDR3C_s0_AC_ROM.hex -inst_rom ../DDR3C_s0_inst_ROM.hex -header sequencer/sequencer_auto.h -vheader ../sequencer_auto_h.sv -ac_rom_init sequencer/sequencer_auto_ac_init.c -inst_rom_init sequencer/sequencer_auto_inst_init.c -DAC_ROM_USER_ADD_0=0_0000_0000_0000 -DAC_ROM_USER_ADD_1=0_0000_0000_1000 -DAC_ROM_MR0=0001000010001 -DAC_ROM_MR0_CALIB= -DAC_ROM_MR0_DLL_RESET=0001100010000 -DAC_ROM_MR1=0000001000100 -DAC_ROM_MR1_OCD_ENABLE= -DAC_ROM_MR2=0000000000000 -DAC_ROM_MR3=0000000000000 -DAC_ROM_MR0_MIRR=0001000001001 -DAC_ROM_MR0_DLL_RESET_MIRR=0001010001000 -DAC_ROM_MR1_MIRR=0000000100100 -DAC_ROM_MR2_MIRR=0000000000000 -DAC_ROM_MR3_MIRR=0000000000000 -DQUARTER_RATE=0 -DHALF_RATE=1 -DFULL_RATE=0 -DNON_DES_CAL=0 -DAP_MODE=0 -DGUARANTEED_READ_BRINGUP_TEST=0 -DMEM_ADDR_WIDTH=13 -DHARD_PHY=0 Error: UniPHY Sequencer Microcode Compiler Error: Copyright (C) 2020 Intel Corporation. All rights reserved. Error: Info: Reading sequencer_mc/ac_rom.s ... Error: Info: Reading sequencer_mc/inst_rom.s ... Error: Info: Writing ../DDR3C_s0_AC_ROM.hex ... Error: Info: Writing ../DDR3C_s0_inst_ROM.hex ... Error: Info: Writing sequencer/sequencer_auto_ac_init.c ... Error: Info: Writing sequencer/sequencer_auto_inst_init.c ... Error: Info: Writing sequencer/sequencer_auto.h ... Error: Info: Writing sequencer/sequencer_auto.h ... Error: Info: Writing ../sequencer_auto_h.sv ... Error: Info: Microcode compilation successful Error: /mnt/c/intelfpga_lite/20.1/quartus/../nios2eds/sdk2/bin/nios2-bsp hal sequencer_bsp .. --default_sections_mapping sequencer_mem --use_bootloader DONT_CHANGE Error: nios2-bsp: Using /mnt/c/intelfpga_lite/20.1/nios2eds/sdk2/bin/bsp-set-defaults.tcl to set system-dependent settings. Error: nios2-bsp: Updating existing BSP because sequencer_bsp/settings.bsp exists. Error: nios2-bsp: Using SOPC design file ../pre_compile.sopcinfo found in .. Error: nios2-bsp: Running "nios2-bsp-update-settings --settings sequencer_bsp/settings.bsp --bsp-dir sequencer_bsp --sopc ../pre_compile.sopcinfo --script /mnt/c/intelfpga_lite/20.1/nios2eds/sdk2/bin/bsp-set-defaults.tcl default_sections_mapping sequencer_mem use_bootloader DONT_CHANGE " Error: child process exited abnormally Error: Cannot find sequencer/sequencer.elf <html>Error: An error occurred while executing "error "An error occurred"" (procedure "_error" line 8) invoked from within "_error "Cannot find $seq_file"" ("if" then script line 2) invoked from within "if {[file exists $seq_file] == 0} { _error "Cannot find $seq_file" }" (procedure "alt_mem_if::util::seq_mem_size::get_max_memory_usage" line 14) invoked from within "alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf"" invoked from within "set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf"]]" ("if" then script line 2) invoked from within "if { !$do_only_rw_mgr_mc && !($bfm_mode || $hps_mode)} { set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequenc..." (procedure "generate_qsys_sequencer_sw" line 943) invoked from within "generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0 $nios_hex_file_name $ac_rom_init_file_name ..." invoked from within "set seq_mem_size_list [generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0 $nios_hex_file_name ..." ("if" else script line 2) invoked from within "if {[::alt_mem_if::util::qini::qini_value alt_mem_if_seq_size_request 0] > 0} { set seq_mem_size [::alt_mem_if::util::qini::qini_value alt_mem_if_se..." (procedure "alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer" line 238) invoked from within "alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}" invoked from within "set qsys_sequencer_files_list [alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}]" (procedure "alt_mem_if::gen::uniphy_gen::generate_sequencer_files" line 3) invoked from within "alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "DDR3" $tmpdir QUARTUS_SYNTH" invoked from within "foreach generated_file [alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "DDR3" $tmpdir QUARTUS_SYNTH] { set file_name [file tail $genera..." (procedure "generate_synth" line 8) invoked from within "generate_synth DDR3C_s0" <html>Info: "DDR3C" instantiated altera_mem_if_ddr3_qseq "s0" Error: Generation stopped, 1 or more modules remaining <html>Info: Done "DDR3C" with 7 modules, 29 files Info: DDR3C: Generating simulation model <html>Info: Generating altera_mem_if_ddr3_emif "DDR3C" for SIM_VERILOG <html>Info: "DDR3C" instantiated altera_mem_if_ddr3_emif "DDR3C" <html>Info: "DDR3C" instantiated altera_mem_if_ddr3_pll "pll0" Info: Generating clock pair generator Info: Generating altgpio <html>Info: "DDR3C" instantiated altera_mem_if_ddr3_phy_core "p0" <html>Info: "DDR3C" instantiated altera_mem_if_ddr3_afi_mux "m0" Error: Error during execution of "{C:/intelfpga_lite/20.1/quartus//../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally Error: Execution of command "{C:/intelfpga_lite/20.1/quartus//../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt" failed Error: /mnt/c/intelfpga_lite/20.1/quartus/bin64/uniphy_mcc.exe -ac_code sequencer_mc/ac_rom.s -inst_code sequencer_mc/inst_rom.s -ac_rom ../DDR3C_s0_AC_ROM.hex -inst_rom ../DDR3C_s0_inst_ROM.hex -header sequencer/sequencer_auto.h -vheader ../sequencer_auto_h.sv -ac_rom_init sequencer/sequencer_auto_ac_init.c -inst_rom_init sequencer/sequencer_auto_inst_init.c -DAC_ROM_USER_ADD_0=0_0000_0000_0000 -DAC_ROM_USER_ADD_1=0_0000_0000_1000 -DAC_ROM_MR0=0001000010001 -DAC_ROM_MR0_CALIB= -DAC_ROM_MR0_DLL_RESET=0001100010000 -DAC_ROM_MR1=0000001000100 -DAC_ROM_MR1_OCD_ENABLE= -DAC_ROM_MR2=0000000000000 -DAC_ROM_MR3=0000000000000 -DAC_ROM_MR0_MIRR=0001000001001 -DAC_ROM_MR0_DLL_RESET_MIRR=0001010001000 -DAC_ROM_MR1_MIRR=0000000100100 -DAC_ROM_MR2_MIRR=0000000000000 -DAC_ROM_MR3_MIRR=0000000000000 -DQUARTER_RATE=0 -DHALF_RATE=1 -DFULL_RATE=0 -DNON_DES_CAL=0 -DAP_MODE=0 -DGUARANTEED_READ_BRINGUP_TEST=0 -DMEM_ADDR_WIDTH=13 -DHARD_PHY=0 Error: UniPHY Sequencer Microcode Compiler Error: Copyright (C) 2020 Intel Corporation. All rights reserved. Error: Info: Reading sequencer_mc/ac_rom.s ... Error: Info: Reading sequencer_mc/inst_rom.s ... Error: Info: Writing ../DDR3C_s0_AC_ROM.hex ... Error: Info: Writing ../DDR3C_s0_inst_ROM.hex ... Error: Info: Writing sequencer/sequencer_auto_ac_init.c ... Error: Info: Writing sequencer/sequencer_auto_inst_init.c ... Error: Info: Writing sequencer/sequencer_auto.h ... Error: Info: Writing sequencer/sequencer_auto.h ... Error: Info: Writing ../sequencer_auto_h.sv ... Error: Info: Microcode compilation successful Error: /mnt/c/intelfpga_lite/20.1/quartus/../nios2eds/sdk2/bin/nios2-bsp hal sequencer_bsp .. --default_sections_mapping sequencer_mem --use_bootloader DONT_CHANGE Error: nios2-bsp: Using /mnt/c/intelfpga_lite/20.1/nios2eds/sdk2/bin/bsp-set-defaults.tcl to set system-dependent settings. Error: nios2-bsp: Updating existing BSP because sequencer_bsp/settings.bsp exists. Error: nios2-bsp: Using SOPC design file ../pre_compile.sopcinfo found in .. Error: nios2-bsp: Running "nios2-bsp-update-settings --settings sequencer_bsp/settings.bsp --bsp-dir sequencer_bsp --sopc ../pre_compile.sopcinfo --script /mnt/c/intelfpga_lite/20.1/nios2eds/sdk2/bin/bsp-set-defaults.tcl default_sections_mapping sequencer_mem use_bootloader DONT_CHANGE " Error: child process exited abnormally Error: Cannot find sequencer/sequencer.elf <html>Error: An error occurred while executing "error "An error occurred"" (procedure "_error" line 8) invoked from within "_error "Cannot find $seq_file"" ("if" then script line 2) invoked from within "if {[file exists $seq_file] == 0} { _error "Cannot find $seq_file" }" (procedure "alt_mem_if::util::seq_mem_size::get_max_memory_usage" line 14) invoked from within "alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf"" invoked from within "set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf"]]" ("if" then script line 2) invoked from within "if { !$do_only_rw_mgr_mc && !($bfm_mode || $hps_mode)} { set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequenc..." (procedure "generate_qsys_sequencer_sw" line 943) invoked from within "generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0 $nios_hex_file_name $ac_rom_init_file_name ..." invoked from within "set seq_mem_size_list [generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0 $nios_hex_file_name ..." ("if" else script line 2) invoked from within "if {[::alt_mem_if::util::qini::qini_value alt_mem_if_seq_size_request 0] > 0} { set seq_mem_size [::alt_mem_if::util::qini::qini_value alt_mem_if_se..." (procedure "alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer" line 238) invoked from within "alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}" invoked from within "set qsys_sequencer_files_list [alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}]" (procedure "alt_mem_if::gen::uniphy_gen::generate_sequencer_files" line 3) invoked from within "alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "DDR3" $tmpdir SIM_VERILOG" invoked from within "foreach generated_file [alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "DDR3" $tmpdir SIM_VERILOG] { set file_name [file tail $generate..." (procedure "generate_verilog_sim" line 7) invoked from within "generate_verilog_sim DDR3C_s0" <html>Info: "DDR3C" instantiated altera_mem_if_ddr3_qseq "s0" Error: Generation stopped, 1 or more modules remaining <html>Info: Done "DDR3C" with 7 modules, 21 files Info: Generated simulation scripts for Modelsim in D:/Andrey/Projects/Altera/DECA_DDR/DDR3C_sim/mentor directory. Info: Generated simulation scripts for VCS and VCS MX in D:/Andrey/Projects/Altera/DECA_DDR/DDR3C_sim/synopsys directory. Info: Generated simulation scripts for NCSIM in D:/Andrey/Projects/Altera/DECA_DDR/DDR3C_sim/cadence directory. Info: Generated simulation scripts for Riviera-PRO in D:/Andrey/Projects/Altera/DECA_DDR/DDR3C_sim/aldec directory.

Please make a separate thread. 8 bit GPU has nothing to do with a dev board's compilation errors.
And without Win10, I will obviously wont get that far unless I use an older version of Quartus.

asmi · « **Reply #2460 on:** February 14, 2021, 12:24:35 am »

Quote from: nockieboy on February 12, 2021, 11:53:32 am

asmi has been singing the virtues of Xilinx for months now and if he's happy to help out where he can, perhaps it's not such a bad idea. Naturally, there'd be a huge learning curve for me with the tool chain etc, but maybe it's time to address that elephant in the room?

I would be happy to help. Also I do think you overestimate the learning curve - it's going to be much easier than you perhaps expect, because fundamentally it's the same flow - you add source files, you run simulations until everything works like it should (in Vivado it's possible to add simulation-only sources to reduce the clutter in the main tree), then you run elaboration and set up IO pin mapping, then you run place&route, generate bitstream - and that's it! You can also program FPGA straight from the IDE, as well as program attached flash devices.
There is additional flow through IP integrator, but you can leave it alone at first and do RTL-only designs. This is kind of Altera's qsys system builder flow, but implemented right IMHO. But if you want to see cool stuff you can do with IPI, I can guide you through that as well.
There are much more functionality in the IDE, but you can kind of ignore it at first until you are comfortable with the basics.

BrianHG · « **Reply #2461 on:** February 15, 2021, 12:24:22 am »

OK, I said I wouldn't do anything to the GPU Geometry testbench, but I been playing with Lattice Diamond FPGA who uses Active-HDL instead of ModelSim for code development and debugging. I only had to make one change to the code and a new setup script for Active-HDL. I've attached the updated test-bench which now works on both HDL simulators.

Here are the setup instructions for both environments:
(For Active-HDL, just run Active-HDL all on it's own outside Lattice Diamond, it is located in your start menu, Lattice/Accessories)
(Same for ModelSim, just run it on it's own, located in Intel FPGA/Modelsim)

Code: [Select]

/*
 * GPU_GEO_tb.sv, for ModelSim and ***NEW Active-HDL.
 *
 * Features control from a source ascii text file script,
 * and a 256 color .BMP picture file generator.
 * Tested on free Altera ModelSim 10 & 20.  Built in parameter
 * (USE_ALTERA_IP) when disabled prevents the use of any Altera specific IP functions.
 *
 * Written by Brian Guralnick.
 *
 * v 0.6.001   Feb 01, 2021
 *
 * To setup simulation, Start Modelsim, The goto 'File - Change Directory' and select this files directory. 
 * Then in the transcript, type:
 * do setup_ms.do
 * (or if you want to enable the Altera megafunction IP, LPM_MULT & SCFIFO)
 * do setup_altera.do
 * 
 * To change the 'TB_COMMAND_SCRIPT_FILE' source script file string and re-run the simulation, type:
 *
 * do test_8bitfont.do
 * do test_45deg.do
 * do test_art.do
 * do test_blitter.do
 * do test_blitter_hires.do
 * do test_vwait.do
 *
 *
 *****************************************************************************
 * For Active-HDL (Comes with Lattice Diamond FPGA developement enviroment.)
 *****************************************************************************
 *
 * Go to 'File - New / Design'
 *        Create an empty design.
 *        Choose Verilog for HDL language, ignore 'Target Technology'.
 *        Type in 'GPU_GEO_tb' for design name.
 *        Next/Finish.
 *        
 * Unzip all the files directly into the 'src' directory inside the 'GPU_GEO_tb' folder.
 * In the console, type:
 *
 * do setup_active-hdl.do
 *
 * *** The result 'xxxx.bmp' and 'GEO_tb_command_results.txt' files generated by
 *     the simulation will be located in the main 'GPU_GEO_tb' folder.
 *
 * Active-HDL does not support the changing of a string in a .sv file,
 * so to run the different tb ascii script demos, you need to copy the:
 *
 * GEO_tb_art.txt
 * GEO_tb_Blitter.txt
 * GEO_tb_Blitter_hires.txt
 * GEO_tb_45deg_zilog.txt
 * GEO_tb_8bit_font.txt
 * GEO_tb_vwait.txt
 *
 * over the 'GEO_tb_command_list.txt' file, then do a restart & run simulation.
 *
 */

Enjoy.
( Stand alone V4 ELLIPSE generator and .BMP generator here -> https://www.eevblog.com/forum/fpga/systemverilog-example-testbench-which-saves-a-bmp-picture-and-executes-a-script/msg3465172/#msg3465172 )

nockieboy · « **Reply #2462 on:** February 15, 2021, 11:24:56 am »

The case for $/LE is a strong one, but also so is availability of the parts. Both of these considerations work against the Cyclones. So the real decision is: Lattice or Xilinx?

I've done some quick research on Mouser (I'm REALLY busy with work for the next few weeks, but it seems pointless putting hours into the DDR3 controller until we decide which FPGA family we're moving to). A straight filter search on Mouser for an FPGA with between 20k-50k LEs, more than 1600Kbits of internal RAM and more than 110 I/OS, then ordered by price to look at the cheapest result spits out the following:

Maker Model LEs Embedded memory I/Os Package Price
Xilinx XC7S25-1CSGA225C 23,360 1,620kbit 150 CSBGA-225 £24.23
Lattice LFE5U-45F-6BG256C 44,000 1,944kbit 197 CABGA-256 £12.09

Based on these metrics, Lattice is the clear winner, unless there's hidden details in the datasheets that could swing it? Also, bearing in mind my usual provisos (I've never soldered BGAs before, other than a cheap soldering iron and even cheaper AliExpress hot air gun, I've got no other special equipment), I think it would be wise and very beneficial for me to create a cheap dev board for the Lattice device. This would double as learning/practice for BGA soldering, but also provide a test bed for developing the GPU HDL further and before going all-out on the next GPU card iteration.

Plus, as a minor side effect, it would also put an open-source Lattice dev board out in the wild for anyone else who might otherwise be put off trying Lattice FPGAs because of the lack of cheap dev boards.

In other news, the DECA boards arrived just now. Can confirm there is no camera module in the box, just the board, couple of USB cables, Ethernet cable and power supply.

BrianHG · « **Reply #2463 on:** February 15, 2021, 11:40:51 am »

Quote from: nockieboy on February 15, 2021, 11:24:56 am

Maker Model LEs Embedded memory I/Os Package Price
Xilinx XC7S25-1CSGA225C 23,360 1,620kbit 150 CSBGA-225 £24.23
Lattice LFE5U-45F-6BG256C 44,000 1,944kbit 197 CABGA-256 £12.09

No, No, No, what is the price of the LFE5U-85F-6BG381C, 84,000 & 3,744kbit, 205 IOs.

Don't you want 1080p full motion MJPEG200 video playback & a full 3D accelerator?

BTW, XC7A35T-1FTG256I would have been a bit larger.

nockieboy · « **Reply #2464 on:** February 15, 2021, 12:07:58 pm »

Quote from: BrianHG on February 15, 2021, 11:40:51 am

Quote from: nockieboy on February 15, 2021, 11:24:56 am
Lattice LFE5U-45F-6BG256C 44,000 1,944kbit 197 CABGA-256 £12.09

No, No, No, what is the price of the LFE5U-85F-6BG381C, 84,000 & 3,744kbit, 205 IOs.

Don't you want 1080p full motion MJPEG200 video playback & a full 3D accelerator?

I knew I would miss something.

The LFE5U-85F-6BG381C is £24, all but for a few pence.

Quote from: BrianHG on February 15, 2021, 11:40:51 am

BTW, XC7A35T-1FTG256I would have been a bit larger.

Bit more expensive at £30 too. Until I'm happy that I can solder BGAs without screwing it up, I'm uncomfortable spending too much on an FPGA to learn on.

So the revised comparison looks like this:

Maker Model LEs Embedded memory I/Os Package Price
Xilinx XC7A35T-1FTG256I 33,280 1,800kbit 170 FBGA-225 £24.23
Lattice LFE5U-85F-6BG381C 84,000 3,744kbit 205 CABGA-381 £23.83

BrianHG · « **Reply #2465 on:** February 15, 2021, 12:22:36 pm »

Ok, then see if the 'LFE5U-45F-6BG381C' exists. It should be pin-pin compatible with the -85F. It only appears to be missing 2 IOs in total.

asmi · « **Reply #2466 on:** February 15, 2021, 01:32:46 pm »

Quote from: nockieboy on February 15, 2021, 12:07:58 pm

XC7A35T-1FTG256I

"I" in the end stands for industrial temps, it's more expensive than "C" variant.
Also - if you want cheap, you've got to go here

Or here for 50T part. They've got a full assortment of Artix'es. Quality - unknown, price - cheap

Should be good enough for soldering practice.

asmi · « **Reply #2467 on:** February 15, 2021, 02:17:47 pm »

Quote from: nockieboy on February 15, 2021, 11:24:56 am

In other news, the DECA boards arrived just now. Can confirm there is no camera module in the box, just the board, couple of USB cables, Ethernet cable and power supply.

Yea, mine arrived too. BrianHG, if you want one, pls send me your address in PM and I will send it to you for free as a token of my appreciation for everything you've done over here to help others.

nockieboy · « **Reply #2468 on:** February 15, 2021, 05:38:20 pm »

Quote from: BrianHG on February 15, 2021, 12:22:36 pm

Ok, then see if the 'LFE5U-45F-6BG381C' exists. It should be pin-pin compatible with the -85F. It only appears to be missing 2 IOs in total.

It does, right here. Just over £14. This is the one you'd recommend starting with? That's a 0.8mm-pitch package - would that be easy enough with a stencil, some light application of solder paste and a hot plate/air gun combination? If I'm going to be soldering BGAs, I'm probably going to need to invest in a hot plate of some kind.

asmi · « **Reply #2469 on:** February 15, 2021, 06:19:06 pm »

With Lattice part you will face the same issue you have with CV, namely lack of memory controller IP (or any other useful IPs for that matter). So why switching then? What benefits will Lattice part have over CV that will justify the switch, as well as possibly higher expense of having to go for 6 layer board due to 0.8 mm ball pitch? Currently there is a BIG jump in price between 4 layer boards and 6 layer ones, and JLCPCB's 6 layer stackup is no good for high-speed designs which require all 4 signal layers.

BrianHG · « **Reply #2470 on:** February 15, 2021, 08:16:12 pm »

Quote from: asmi on February 15, 2021, 01:32:46 pm

Quote from: nockieboy on February 15, 2021, 12:07:58 pm
XC7A35T-1FTG256I
"I" in the end stands for industrial temps, it's more expensive than "C" variant.
Also - if you want cheap, you've got to go here Or here for 50T part. They've got a full assortment of Artix'es. Quality - unknown, price - cheap Should be good enough for soldering practice.

The Lattice part prices are at Arrow, Digikey & Future Electronics, for single pieces, not Aliexpress...
Yes, I know 0.8mm makes things a little more difficult, but sacrificing some of those extra IOs we can squeeze a 4 layer PCB. Our only time critical paths will be the DDR3.
\
Yes, looking at Lattice dev tools, there is a learning curve and documentation could be better as I use their version of a Megafunction Wizard 'Clarity Designer' to work out a lot about configuring the function as I just got the HDMI_PLL module to work, but having trouble simulation & telling Diamond what the external clock input frequency to avoid warnings, warnings, warnings. Perhaps I have yet to find the right documentation sources. And we still appear to have a separate timing constraints file which needs to be separate of the source code like Quartus, but at least now, with a common cross compatible .sv test bench architecture, I know I can render a timing constraints file by running a sim TB of my code only once before adding it to the .sdc file.

Xilinx does make the DDR3 black box easy, but there is something specific I want to do with all this spare time, so, this is why I started to engineer my code to be bottom end SystemVerilog, targeting 3 way platform support, (4 way with GOWIN which will be last after finishing a number of other useful functions which would cost many some real $$$).

I left Xilinx third because I bet they will be MUCH less trouble than Lattice Diamond, as this will force my code to have a number of eccentricities already prepared/worked out.

SiliconWizard · « **Reply #2471 on:** February 16, 2021, 04:05:55 pm »

Quote from: asmi on February 15, 2021, 06:19:06 pm

With Lattice part you will face the same issue you have with CV, namely lack of memory controller IP (or any other useful IPs for that matter). So why switching then? What benefits will Lattice part have over CV that will justify the switch, as well as possibly higher expense of having to go for 6 layer board due to 0.8 mm ball pitch? Currently there is a BIG jump in price between 4 layer boards and 6 layer ones, and JLCPCB's 6 layer stackup is no good for high-speed designs which require all 4 signal layers.

Nope, there are a lot of Lattice IPs including memory controllers for DDR/DDR2/DDR3. Problem is, those memory controllers are NOT free. (Available on the Lattice IP server.) Whereas Xilinx ones are free to use AFAIK. I have no clue how much the licenses are - you need to contact sales. So sure Xilinx is ahead here.

asmi · « **Reply #2472 on:** February 16, 2021, 04:31:11 pm »

Quote from: SiliconWizard on February 16, 2021, 04:05:55 pm

Nope, there are a lot of Lattice IPs including memory controllers for DDR/DDR2/DDR3. Problem is, those memory controllers are NOT free. (Available on the Lattice IP server.)

That's as good as non-existent in my book.

BrianHG · « **Reply #2473 on:** February 20, 2021, 07:59:01 am »

Has anyone used Efinix?
Take a look here: ' https://www.digikey.com/en/products/detail/efinix-inc/T85F484C3/11591358 '

That's 20.29$ for 1 single 84K-gate, 4 megabit, 256 IO FPGA, with 1066 MTPS DDR3 controller.
They use a regular FTDI usb chip for the programmer making it easy to place your own firmware programmer on your pcb.

Or, 25.37$ for 112K-gate, 5.5 megabit ram, 256 IO.
https://www.digikey.com/en/products/detail/efinix-inc/T120F484C3/11591376

However, It's like I cannot find the software dev tool download or complete documentation other than some video walk through, available ICs and dev boards.

I guess it's kinda useless for a public domain project if no one can get the compiler utilities.

SiliconWizard · « **Reply #2474 on:** February 20, 2021, 04:43:13 pm »

Quote from: BrianHG on February 20, 2021, 07:59:01 am

Has anyone used Efinix?
Take a look here: ' https://www.digikey.com/en/products/detail/efinix-inc/T85F484C3/11591358 '

Nope, but I've heard of them and they looked interesting.

Quote from: BrianHG on February 20, 2021, 07:59:01 am

However, It's like I cannot find the software dev tool download or complete documentation other than some video walk through, available ICs and dev boards.

Same here. When I looked, I was unable to get anything really needed to get started. Looks like you need to contact the vendor to be able do do anything?


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