By the way, I'm no expert, but I think the R/C part is probably not working as a filter here?Correct. Both R32&C and R34&C are to make delays, not to act as filters.
To be precise the setup in combination with the gates is what gives the signal its delay. The R/C combination is still a low pass filter. Just look at the signals on the capacitor and see how the edge of the signal is filtered into a slope.
Also when you raise the frequency of the input signal it will reach a point that the circuit does not work anymore.
Added an image plucked from the net to show this filtering.
1. We don't know the value of the Cs but I'd wager the gate delay contributes very much less delay than the RC.
2. Yes, RC forms a low pass filter but that is not the aim here. The values of R and C were not computed to give some specified value of attenuation at some specified frequency. Rather they were computed so that the exponentially rising or decaying waveform reaches approximately 50% after some required time.
To be precise the setup in combination with the gates is what gives the signal its delay. The R/C combination is still a low pass filter. Just look at the signals on the capacitor and see how the edge of the signal is filtered into a slope.
Also when you raise the frequency of the input signal it will reach a point that the circuit does not work anymore.
Added an image plucked from the net to show this filtering.
Looking at a datasheet for a CD4030 when powered from 10V Vin low is max 3V and Vin high is min 7V, so depending on the actual supply voltage and the Vout of the first gate the times can be calculated. But for this the value of the capacitor needs to be known. I would have to search for the formula to do so. I do remember that t = R * C, and that after ~5t the capacitor is at near the supplied voltage.
I have not done an analysis but would not be surprised if the range of actual delay times encountered differed by as much as 20% of the calculated value.
Here a bit more about the filters to make the delay. Think Fourier and how a square wave is made up from an infinite set of sine waves with different frequencies and amplitudes.
The RC combination filters the sine waves with frequencies above the -3dB point.
The RC combination filters the sine waves with frequencies above the -3dB point.The textbook doctrine may not apply here. In this case, or cases similar to this, the frequencies it blocks (or not) depend on the threshold voltage of the gate.
I would like a bit more discussion about the feedback of the upper half of the circuit through R78 (later maybe more in-depth analysis of the other parts of the circuit).
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I think now I've figured out, indeed it's like a Schmitt trigger characteristic to reduce the bouncing between L/H when crossing the threshold. But this is only for the falling edge, which is more necessary because it's less steep. Will double check and update with more analysis ...
Please next time try to make the subject line more specific.
Thank you.
The gate threshold voltage has nothing to do with the sine wave frequencies being blocked. The threshold voltage in combination with the RC time are what make up the delay the circuit is designed for.
Mark that I mention sine wave and not square wave. I know it is semantics, but what I'm trying to get across is that any RC combination is a filter, no matter the intent of the circuit. Sure it can be used to make a delayed signal, which is done in this case.
The circuit with R78 can be seen as a network with two supplies (or sinks) and as such you can do calculations on it.
But a simple view is that when the output of the gate goes high it will slightly raise the voltage at the input and with that make sure that it stays above the threshold until the other supply (essentially the voltage across the capacitor) lowers so much that it falls below the threshold and the output of the gate will then also go low, and with doing this it will drop the voltage at the input below the threshold to make sure it stays below the threshold. It might be that they needed it to suppress some noise and adding this resistor made it stable.
Just like a Schmitt trigger circuit, as you already found out yourself.
1. Thinking in terms of sine waves and their frequencies is not helpful when analysing these RC plus gate delays. Instead consider the time domain. Start with zero voltage on the capacitor and then apply a voltage step to the input R. Any decent textbook on circuit analysis will show the derivation of the formula for the voltage on the capacitor after a time t.
Vout = Vin(1-exp(-t/RC))
Where Vin is the height of the step and exp() means e (that 2.718 ... number) raised to the power of the number in the ().
Using that formula it is possible from R and C to compute the time to reach a target voltage or conversely to compute the RC product to reach a target voltage after a desired delay. For example if the target voltage is 50% of the step height then
Vout/Vin = 0.5 = 1-exp(-t/RC)
exp(-t/RC) = 0.5
take natural logarithm of each side
-t/RC = -0.693
RC=t/0.693 or t = 0.693RC
The same analysis holds if we start with the voltage having been applied for a sufficiently long time that the capacitor has been fully charged and then it is changed to zero so that the capacitor discharges through the resistor. Vout = Vin(exp(-t/RC))
And here I think you went wrong. See this thread for info about "Thevenin Equivalent"
The RC time is not based on the 10K resistor, but the resulting resistance of the parallel and series resistors.
That is why I wrote about calculations on networks in the earlier post where I gave a simple view on the positive feedback.
There are several ways to approach such networks. You can use Kirchhoff's laws or use Thevenin's equivalent or Norton's theorem.
Yes, and your adjustment still feels wrong.
It has been to long since doing this kind of math, ...
..., but you are using C * R1, which is not the correct base for doing the calculations.
The numbering of your resistors is wrong for proper formulating this, but since both 10K resistors are named R1 and of the same value I'm using it in both terms.
The RC time in this case is C * ((R1 * (R1' + R2)) / (2R1 + R2))) Due to the fact that R2 is big compared to R1 the difference is not that big. Only ~120 Ohms.
The capacitor will only charge to the Thevenin equivalent voltage, which is calculated by V * ((R1' + R2) / (2R1 + R2)), which is only slightly less then V.
These are the values to use in the calculation for determining the voltage across the capacitor over time.
Edit: to explain, the resistance to use for the RC time is also based on the Thevenin equivalent of them being in parallel, that is R1 is parallel to the series resistance of R1' and R2.
1. I think we are agreed that the charge and discharge of the capacitor are not symmetrical and it is the longer one (diode path not operating) that is of interest. In which case it is the discharge curve you should focus on.
As advised by pcprogrammer you ned to calculate the source voltage and resistance equivalent to the resistors you have and the voltages applied to them. ...
... When the HIGH to LOW threshold is reached and the gate changes state the equivalent circuit will change and so will the discharge curve. It will be slightly faster but that is not really of any consequence if it is only the delay to the switching time that you are working out.
2. It is true that in theory the capacitor never becomes fully charged or discharged. However the discrepancy from the asymptotic value becomes small.
Below is the percentage discrepancy for some values of t= nRC:
n=1: 36.8%
n=2: 13.5%
n=3: 4.98%
n=4: 1.83%
n=5: 0.67%
n=6: 0.25%
To gain some insight in why the equivalent voltage and resistance just take a look at this video.
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