FPGA 101 - Making awesome stuff with FPGAs
Listened up to the point where the presenter admitted he didn't know why FPGA vendors choose 18 bit widths for embedded multipliers and then had to do a facepalm and turn it off.
Listened up to the point where the presenter admitted he didn't know why FPGA vendors choose 18 bit widths for embedded multipliers and then had to do a facepalm and turn it off.
Well, regarding the bit width, I would be thrilled to hear your answer about it. Using 18 bit because the memory width is a multiple of 9 bit is the best answer I found so far, but still, it is rather arbitrary as you hardly want to multiply the parity bit. 16 bit would require less resources and run at a higher frequency, which may, or may not improve overall performance.
Just watched it and all my questions have been answered. Basically PSHDL isn’t aimed at asynchronous designs with multiple clocks, it's aimed at synchronous designs with a single clock.
PSHDL is aimed at the educational/hobbyist market and it isn’t trying to replace VHDL or Verilog, its aim is to become the Arduino for FPGA’s.
Sorry for digging up things this old, but this is not correct. PSHDL does not have any limitations regarding the number of clock domains. The only limitation that is imposed artificially is that you can not simulate combinatorial loops in PSHDL. And this limitation is only there because I think most people are creating those by mistake, rather than choice. It would be possible to support it rather easily.
However the common case of just having a single clock synchronous design is the case PSHDL is optimized for.
There is also an updated 30C3 version of the talk:
Listened up to the point where the presenter admitted he didn't know why FPGA vendors choose 18 bit widths for embedded multipliers and then had to do a facepalm and turn it off.
Well, regarding the bit width, I would be thrilled to hear your answer about it. Using 18 bit because the memory width is a multiple of 9 bit is the best answer I found so far, but still, it is rather arbitrary as you hardly want to multiply the parity bit. 16 bit would require less resources and run at a higher frequency, which may, or may not improve overall performance.
http://www.altera.com/literature/hb/cyc3/cyc3_ciii51003.pdfParity checking for error detection is possible with the parity bit along with internal
logic resources. Cyclone III family devices M9K memory blocks support a parity bit
for each storage byte. You can use this bit optionally as a parity bit, or as an additional
data bit. No parity function is actually performed on this bit.
I will just leave it up to the reader to infer the meaning of this passage.
This EEVblog video inspired me to produce this T-shirt artwork from an edited (numbers removed and flipped horizontally)
public domain human brain drawing and a
freeware font (Digitrix) which
allows commercial use. Anyone can grab this and make T-shirts from it for sale.
All I ask is that I get a free one if you do. The file will be downloaded as a PNG which has a much larger file size while loosing some fine resolution over the original BMP. If you want the original BMP, let me know and I'll email it to you:
Human Brain - Field Programmable Gate Array
http://i142.photobucket.com/albums/r100/EGoldstein1984/BrainFPGA_zpsb5c49699.png