Here is my CycloneIII prototype board that I made year and a half ago. I remember I cut my finger badly while trying to drill a hole in SMT adapter to connect bottom pad of the QFP to the ground. Whole bunch of decoupling caps soldered on other side (not shown). Chip in the corner is CPLD, MAX from Altera - I killed it by reprogramming too many times. Rainbow ribbon cable toing to ADC extension board that only works at 10-15MHz due to lack of bus transeivers and poor signal integrity.
Still I had much more fun with this design than with complete dev board - I can solder and un-solder things at will.
Found a prices for the USB blaster was a bit dear, but found a MAX II CPLD dev kit for half the price that includes a USB blaster.
With all of that said, I'm a hardware guy and love FPGAs... Keep the videos coming!I'm a software guy and I love FPGAs too In VHDL you can even use variables, procedures, functions and loops. But you have to keep in mind that it needs A LOT of logic units, because a loop is kind of unrolled and synthesized in parallel, same for procedures and functions. You have to sequence it with state machines from time to time, when it gets to big or when the timing requirements are not met anymore because of too long logic chains. Hardware guys don't like my VHDL code
No doubt, FPGAs are awesome, but one thought always comes up as this is being discussed.
A hobbyist to hobbyist question: What would YOU do with an FPGA ?
Something that is not there yet or even unseen and unheard of ...
My $50 saleae logic analyser clone can be configured as a USB blaster
For those of you that don't like to learn VHDL or Verilog, I developed a new language that focuses on being more C-like and easier to learn. It is called PSHDL.
There is also a Web UI where you can code online and get the generated code. In the near future you will also be able to simulate your code in your browser, but that currently only works in Dartium. But you can also generate C and Java Code out of it for simulation purposes.
In PSHDL you still have to learn how to "program" hardware, but at least a few common mistakes that are easy to make with VHDL or Verilog are avoided.
Check it out at http://pshdl.org or the new and much more advanced editor at http://beta.pshdl.org
There is also a blog and twitter to follow the development of it. The ultimate aim is to generate the Arduino for FPGAs!
If you have any questions about it feel free to contact me.
IF clk'event AND clk = '1' THEN
interesting_signal_meta <= interesting_signal;
IF interesting_signal_meta = '0' THEN
do one thing...;
ELSE
do some other thing...;
END IF;
END IF;
Metastability: a pain in the backside if you don't really know what it is and how to work around it, but really not that big a deal once you understand the circumstances under which it can bite.
I've lost count of the number of times I've written code like:Code: [Select]IF clk'event AND clk = '1' THEN
interesting_signal_meta <= interesting_signal;
IF interesting_signal_meta = '0' THEN
do one thing...;
ELSE
do some other thing...;
END IF;
END IF;
Metastability: a pain in the backside if you don't really know what it is and how to work around it, but really not that big a deal once you understand the circumstances under which it can bite.
I've lost count of the number of times I've written code like:Code: [Select]IF clk'event AND clk = '1' THEN
interesting_signal_meta <= interesting_signal;
IF interesting_signal_meta = '0' THEN
do one thing...;
ELSE
do some other thing...;
END IF;
END IF;
signal sreg : std_logic_vector(SYNC_STAGES-1 downto 0);
attribute altera_attribute of sreg : signal is "-name SYNCHRONIZER_IDENTIFICATION FORCED";
That's the point I was trying to make... nothing in the FPGA uses interesting_signal directly apart from the input to the latch. Everything else uses interesting_signal_meta, which (we presume!) has settled to a definite 1 or 0 by the time of the clock pulse immediately after the one on which it latches interesting_signal.
In some cases - perhaps if the clock speed is high, or the FPGA is particularly susceptible to this effect - it can be a good idea to cascade two or more latches. I know Altera give the option of 1, 2 or more synchronisation stages on their dual-port SRAMs for this reason, though I've never personally needed more than one stage.
...Throw that at the little PIC or AVR and this is what will happen :
it will jump out of its socket , scamper to the far corner of your circuit board , roll over on it's back , curl up it's tiny little legs and simply die...
...You should see his photography setupthis is the machine doing it :
http://www.flickr.com/photos/fotoopa_hs/sets/72157627714453063/
driven by a single cyclone FPGA.
Just an FYI, clk'event and rising_edge are not equivalent. rising_edge specifically looks for a transition 0 (and other things) to 1, whereas old style just checked that clk was 1. While new designs should probably use rising_edge, if you went back and changed all of your old designs you might well run into different behavior, especially in your simulations.
-------------------------------------------------------------------
-- edge detection
-------------------------------------------------------------------
function rising_edge (signal s : STD_ULOGIC) return BOOLEAN is
begin
return (s'event and (To_X01(s) = '1') and
(To_X01(s'last_value) = '0'));
end function rising_edge;
function falling_edge (signal s : STD_ULOGIC) return BOOLEAN is
begin
return (s'event and (To_X01(s) = '0') and
(To_X01(s'last_value) = '1'));
end function falling_edge;
--------------------------------------------------------------------
function To_X01 (s : STD_ULOGIC) return X01 is
begin
return (cvt_to_x01(s));
end function To_X01;
constant cvt_to_x01 : logic_x01_table := (
'X', -- 'U'
'X', -- 'X'
'0', -- '0'
'1', -- '1'
'X', -- 'Z'
'X', -- 'W'
'0', -- 'L'
'1', -- 'H'
'X' -- '-'
);
coincidentally, SparkFun just released an FPGA dev board for $75 US:
https://www.sparkfun.com/products/11953
coincidentally, SparkFun just released an FPGA dev board for $75 US:
https://www.sparkfun.com/products/11953
For those of you that don't like to learn VHDL or Verilog, I developed a new language that focuses on being more C-like and easier to learn. It is called PSHDL.
There is also a Web UI where you can code online and get the generated code. In the near future you will also be able to simulate your code in your browser, but that currently only works in Dartium. But you can also generate C and Java Code out of it for simulation purposes.
In PSHDL you still have to learn how to "program" hardware, but at least a few common mistakes that are easy to make with VHDL or Verilog are avoided.
Check it out at http://pshdl.org or the new and much more advanced editor at http://beta.pshdl.org
There is also a blog and twitter to follow the development of it. The ultimate aim is to generate the Arduino for FPGAs!
If you have any questions about it feel free to contact me.
I had a look at your website and I remembered doing CPLD designs using ‘Abel’ and having to handwrite state machines to do the main sequential processing.
One of the problems with ‘Abel’ was that engineers really needed to know about Digital Design if they wanted to use it for things more complex than the typical Address decoding etc. One of the problems would be knowing about things like Metastability, especially if your design has multiple clocks. Looking at PSHDL (only briefly) is was wondering if it hasn’t reintroduced some of the issues which no longer seem to be a problem with current two main HDL’s.