SystemVerilog has UVM and a lot of BFMs available. It can be the only language to use in certain highly complex projects where we want to use its many special features to create constrained random stimulus assertion based test benches.
Are there any users on this forum that moved from VHDL to SystemVerilog? How was your journey, please share with everyone.
Goodluck. Many of us here seem to be dead VHDL or dead Verilog/SystemVerilog. At least this is the take away impression I've gotten over the past few years.
My journey from old fashioned Verilog to SystemVerilog focused around my weird test-benches which have gone as far as directly rendering .bmp pictured directly from a .sv geometry drawing engine where my test-bench would read an ascii test text file with functions combined with source coordinates, rendering a final picture as test results using ModelSim. I do not know if this is possible with VHDL. My example source code, which was documented for beginners is available here on eevblog if you need examples.
I slowly moved from Verilog into SV around the time I started working with AXI bus a lot, and so connecting 40+ signals every time wasn't much fun, SV's interface made this painless as just one connection is required for entire bus. That was too good of a feature to pass by. And now I use interfaces in just about any of my modules, except for some very simple ones. Add some other creature comfort features like not having to type a signal name twice while connecting a module if signal name is the same as port name, and you have a winner.
I did study both VHDL and Verilog in University (SV wasn't a thing yet when I was there), but chose Verilog every time I had a choice (obviously had to use VHDL during VHDL labs). VDHL code tend to have too low of an SNR for my taste.
But... just you wait for resident VDHLers to show up in force over here, and tell you how bad SV is, even though most of them know jack shit about it
My journey from old fashioned Verilog to SystemVerilog focused around my weird test-benches which have gone as far as directly rendering .bmp pictured directly from a .sv geometry drawing engine where my test-bench would read an ascii test text file with functions combined with source coordinates, rendering a final picture as test results using ModelSim. I do not know if this is possible with VHDL. My example source code, which was documented for beginners is available here on eevblog if you need examples.
I'm interested in this, do you have a link?
My journey from old fashioned Verilog to SystemVerilog focused around my weird test-benches which have gone as far as directly rendering .bmp pictured directly from a .sv geometry drawing engine where my test-bench would read an ascii test text file with functions combined with source coordinates, rendering a final picture as test results using ModelSim. I do not know if this is possible with VHDL. My example source code, which was documented for beginners is available here on eevblog if you need examples.
I'm interested in this, do you have a link?
Entry level which executes a script, runs an ellipse generator and saves a .bmp with a setup instruction on how to use ModelSim and Active-HDL without their sluggish full Quartus/Lattice Diamond running (skip straight to version 4...):
https://www.eevblog.com/forum/fpga/systemverilog-example-testbench-which-saves-a-bmp-picture-and-executes-a-script/High level which contains a full geometry processor including 2D blitter bitmap functions with binary data loading:
https://www.eevblog.com/forum/fpga/fpga-vga-controller-for-8-bit-computer/msg3465124/#msg3465124
I slowly moved from Verilog into SV around the time I started working with AXI bus a lot, and so connecting 40+ signals every time wasn't much fun, SV's interface made this painless as just one connection is required for entire bus. That was too good of a feature to pass by. And now I use interfaces in just about any of my modules, except for some very simple ones. Add some other creature comfort features like not having to type a signal name twice while connecting a module if signal name is the same as port name, and you have a winner.
I did study both VHDL and Verilog in University (SV wasn't a thing yet when I was there), but chose Verilog every time I had a choice (obviously had to use VHDL during VHDL labs). VDHL code tend to have too low of an SNR for my taste.
But... just you wait for resident VDHLers to show up in force over here, and tell you how bad SV is, even though most of them know jack shit about it
I too moved from Verilog to SystemVerilog for the sole reason of being able to pass unpacked arrays as inputs/outputs. This alone makes it worth it in my opinion. Its extremely useful.