Oh crap, I've lost count on how many times did I make the same mistake!
Little length and matching cleanup. We are assuming that this matches the length from the IO pins on the eval board below. The goal is at the end where the 100ohm termination resistors are located, the overall length of the +&- tracks are identical.
We cant do anything about the differences through the connector itself, only correct after the connector so it will undo the length difference introduced before the first connector on the bottom.
Uhh that was a silly mistake with the header - I don't know if it was an issue with the type of header I'd used or what, but it was clearly wrong - well done for spotting that one.
Have updated the schematic and PCB with the other changes - should be up to date so far.
Little length and matching cleanup. We are assuming that this matches the length from the IO pins on the eval board below. The goal is at the end where the 100ohm termination resistors are located, the overall length of the +&- tracks are identical.
We cant do anything about the differences through the connector itself, only correct after the connector so it will undo the length difference introduced before the first connector on the bottom.
So you mean correct for any differences in length created on the EasyFPGA board itself?
Why cant my Adobe reader see your schematic. It says I need a font package.
I don't like downloading unknown addons or upgrading to spy-ware...
It really shouldn't make me feel better, but knowing I'm not the only one who makes these mistakes does make me feel like I should be less harsh on myself.
Why cant my Adobe reader see your schematic. It says I need a font package.
I don't like downloading unknown addons or upgrading to spy-ware...
Oooh... no idea? I've not changed any fonts in it or anything. It was using Times New Roman and Verdana... Hmmm.. try this one?
Little length and matching cleanup. We are assuming that this matches the length from the IO pins on the eval board below. The goal is at the end where the 100ohm termination resistors are located, the overall length of the +&- tracks are identical.
We cant do anything about the differences through the connector itself, only correct after the connector so it will undo the length difference introduced before the first connector on the bottom.
So you mean correct for any differences in length created on the EasyFPGA board itself?Follow my picture. The traces are going to the same pins, just that they run vertical before the +&- go into their 50ohm parallel routing. The EasyFPGA looks like it takes a similar vertical route from IO pin to the connector. We are just following the same parallel vertical trace flow and by the time the 2 traces go parallel on your HDMI PCB, the difference in length should be ~cancelled out.
Also nitpicking, but personally it would bother me that single trace on top right of the connector going around the last trace.
Owzat?
And what BrianHG said re: trace matching.
Nockieboy, you didn't have to do that change, mariush could have not possibly been talking about the DDC and HPD lines. These signals operate at 100KHz. You could run circles around the PCB going through each layer and it would still work.
Module #2: This will be an Intel megafunction which takes in the pixel Clk, Clk_10x which will be the serial output clock, and the 4x channels from module #1. It will output 4 parallel serial streams which will feed the LVDS output butters.
Yeah, I know, but I have a bit of OCD when it comes to fine-tuning stuff like this. I could happily spend the next week tweaking signal traces and component positioning to make it as efficient as possible (within my level of skill and knowledge, obviously).
Module #2: This will be an Intel megafunction which takes in the pixel Clk, Clk_10x which will be the serial output clock, and the 4x channels from module #1. It will output 4 parallel serial streams which will feed the LVDS output butters.Are you sure you will need a 10x clock? On Xilinx devices output SERDES operates in DDR mode, so it only requires 5x clock (because DDR). So for 720p you only need 371.25 MHz for the pixel clock as opposed to 742.5 MHz. This is why it's possible to achieve 720p while being completely in spec (global clock buffers can only go up to 630 MHz or so).
Oh, and one more thing - if you will be OK with 24/25 Hz refresh rate as opposed to 60 Hz, you can do full 1080p with the same bandwidth (or slightly lower for 24 Hz) as 720p@60.
Yeah, I know, but I have a bit of OCD when it comes to fine-tuning stuff like this. I could happily spend the next week tweaking signal traces and component positioning to make it as efficient as possible (within my level of skill and knowledge, obviously).If I were you, I'd rather look at the 3D model of the board with all parts on there and see if I can actually hand-assemble it. For example, the passive connected to the right bottom pin of that QFN looks to me a bit too close to the QFN to actually solder it with an iron without touching the QFN. Try to think about the order in which you will be soldering parts and see if something might be in the way of a soldering iron at some point in assembly.
I assume you are going to hand-solder it, if not, pls ignore everything I just said.
Also, just in case you guys didn't see it first time around, I would like to once again suggest going for 0.8 mm thick board as opposed to regular 1.6 mm. This should lower trace impedance and bring it a bit closer to 50 Ohm as they are supposed to be.
Oh, and one more thing - if you will be OK with 24/25 Hz refresh rate as opposed to 60 Hz, you can do full 1080p with the same bandwidth (or slightly lower for 24 Hz) as 720p@60.
It all looks okay to my untrained eye?
I don't see orientation mark for the QFN on a silkscreen - but maybe it's just a bad angle.
I would work a bit on a silkscreen, but layout-wise it looks OK to me, at least on the first sight.
Yes, the pin 1 ID is missing...